OPA3875IDBQR

Burr Brown Products from Texas Instruments OPA3875 SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 Triple 2:1 High-Speed Video Multiplexer FEATURES • • • • • • • • • • • • • 700MHz SMALL-SIGNAL BANDWIDTH (AV = +2) 425MHz, 4VPP BANDWIDTH 0.1dB GAIN FLATNESS to 150MHz 4ns CHANNEL SWITCHING TIME LOW SWITCHING GLITCH: 40mVPP 3100V/µs SLEW RATE 0.025%/0.025° DIFFERENTIAL GAIN, PHASE HIGH GAIN ACCURACY: 2.0V/V ±0.4% DESCRIPTION The OPA3875 offers a very wideband, 3-channel, 2:1 multiplexer in a small SSOP-16 package. Using only 11mA/ch, the OPA3875 provides three, gain of +2, video amplifier channels with > 400MHz large-signal bandwidth (4VPP). Gain accuracy and switching glitch are improved over earlier solutions using a new (patented) input stage switching approach. This technique uses current steering as the input switch while maintaining an overall closed-loop design. Gain matching between each of the 3-channel pairs is also significantly improved using this technique (700MHz small-signal bandwidth at a gain of 2, the OPA3875 gives a typical 0.1dB gain flatness to > 150MHz. System power may be reduced using the chip enable feature for the OPA3875. Taking the chip enable line high powers down the OPA3875 to 100kHz f > 100kHz RL = 150Ω RL = 150Ω VO = ±2V VO = 0.5V Step VO = 1.4V Step CHANNEL-TO-CHANNEL PERFORMANCE Gain Match Channel to Channel, RL = 150Ω All inputs, RL = 150Ω Output Offset Voltage Mismatch All Hostile Crosstalk Channel-to-Channel Crosstalk CHANNEL AND CHIP-SELECT PERFORMANCE SEL (Channel Select) Swtiching Time EN (Chip Select) Switching Time RL = 150Ω Turn On Turn Off SEL (Channel Select) Switching Glitch EN (Chip-Select) Switching Glitch All Hostile Disable Feedthrough Maximum Logic 0 Minimum Logic 1 EN Logic Input Current SEL Logic Input Current DC PERFORMANCE Output Offset Voltage Average Output Offset Voltage Drift Input Bias Current Average Input Bias Current Drift Gain Error (from 2V/V) INPUT Input Voltage Range Input Resistance Input Capacitance Channel Selected Channel Deselected Chip Disabled ±2.8 1.75 0.9 0.9 0.9 V MΩ pF pF pF typ typ typ typ typ C C C C C VO = ±2V 0.4 1.4 RIN = 0Ω, G = +2V/V RIN = 0Ω, G = +2V/V ±5 ±18 ±2.5 ±14 ±15.8 ±50 ±19.5 ±40 1.5 ±17 ±50 ±20.5 ±40 1.6 mV µV/°C µA nA/°C % max max max max max A B A B A All Inputs to Ground, At Matched Load All Inputs to Ground, At Matched Load 50MHz, Chip Disabled (EN = High) EN, SEL EN, SEL 0V to 4.5V 0V to 4.5V 75 160 4 9 60 40 15 –68 0.8 2.0 100 200 0.8 2.0 125 250 0.8 2.0 150 300 ns ns ns mVPP mVPP dB V V µA µA typ typ typ typ typ typ max min max max C C C C C C B B A A All three outputs f = 50MHz, RL = 150Ω f = 50MHz, RL = 150Ω ±0.05 ±0.1 ±3 -50 –58 ±0.25 ±0.5 ±9 ±0.3 ±0.6 ±10 ±0.35 ±0.7 ±12 % % mV dB dB max max max typ typ A A A C C 700 425 150 2.0 2.0 –68 6.7 3.8 0.025 0.025 3100 460 600 2800 2700 2600 2.02 1.98 –65 7.0 4.2 2.03 1.97 –64 7.2 4.6 2.05 1.95 –63 7.4 4.9 525 390 515 380 505 370 MHz MHz MHz V/V V/V dBc nV/√Hz pA/√Hz % ° V/µs ps ps min min typ max min max max max typ typ min typ typ B B C B B B B B C C B C C +25°C MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to 70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) (1) (2) (3) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C tested specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient +36°C at high temperature limit for over temperature specifications. Submit Documentation Feedback 3 OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2, RL = 150Ω, unless otherwise noted. OPA3875 TYP PARAMETER OUTPUT Output Voltage Range Output Current Output Resistance VO = 0V, Linear Operation Chip enabled Chip Disabled, Maximum Chip Disabled, Minumum Output Capacitance POWER SUPPLY Specified Operating Voltage Minimum Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Maximum Quiescent Current Power-Supply Rejection Ratio (+PSRR) (–PSRR) THERMAL CHARACTERISTICS Specified Operating Range D Package Thermal Resistance θJA DBQ SSOP-16 Junction-to-Ambient 85 °C/W typ C –40 to +85 °C typ C Chip Selected, VS = ±5V Chip Selected, VS = ±5V Chip Deselected Input-Referred Input-Referred 33 33 0.9 56 55 ±5 ±3.0 ±6.3 34 31 1.2 50 51 ±3.0 ±6.3 35 30 1.4 48 49 ±3.0 ±6.3 36 27 1.5 47 48 V V V mA mA mA dB dB typ min max max min max min min C B A A A A A A Chip Disabled ±3.5 ±70 0.3 800 800 2 912 688 915 685 918 682 ±3.4 ±50 ±3.35 ±45 ±3.3 ±40 V mA Ω Ω Ω pF min min typ max min typ A A C A A C CONDITIONS +25°C MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to 70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) 4 Submit Documentation Feedback OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V At G = +2 and RL = 150Ω, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE 7 6 1 Frequency Response Left Scale 0.3 8 7 LARGE-SIGNAL FREQUENCY RESPONSE RL = 150W G = +2V/V Normalized Gain Flatness (dB) 0.2 0.1 0 6 5 4 3 2 1 0 -1 -2 -3 0 100 200 300 400 500 600 700 Frequency (100MHz/div) 800 900 1000 VO = 5VPP VO = 2VPP VO = 4VPP VO = 1VPP Gain (dB) 4 3 2 1 0 1M 10M 100M Frequency (Hz) 1G VO = 500mVPP RL = 150W G = +2V/V Gain Flatness Right Scale -0.1 -0.2 -0.3 -0.4 Figure 1. NONINVERTING PULSE RESPONSE 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 Time (1ns/div) 100MHz Square-Wave Input Small-Signal 0.4VPP Left Scale RL = 150W G = +2V/V 2.5 Large-Signal 4VPP Right Scale 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 Gain (dB) Figure 2. ALL INPUT DISABLE FEEDTHROUGH vs FREQUENCY -20 Large-Signal Output Voltage (V) Small-Signal Output Voltage (V) -30 -40 Input-Referred EN = +5V Isolation (dB) -50 -60 -70 -80 -90 -100 -110 1M 10M 100M Frequency (Hz) 1G Figure 3. RECOMMENDED RS vs CAPACITIVE LOAD 80 8 7 0.1dB Peaking Targeted 70 60 50 Figure 4. FREQUENCY RESPONSE vs CAPACITIVE LOAD Gain to Capacitive Load (dB) 6 5 4 3 2 1 0 -1 -2 -3 75W NOTE: (1) 1kW is optional. 75W x2 CL = 10pF RS (W) 40 30 20 10 0 1 10 100 1000 Capacitive Load (pF) CL = 47pF RS CL 1kW (1) CL = 100pF CL = 22pF 1 10 Frequency (MHz) 100 400 Figure 5. Figure 6. Submit Documentation Feedback 5 OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2 and RL = 150Ω, unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE -60 -65 -70 -75 -80 3rd-Harmonic -85 dBc = dB Below Carrier -90 100 Resistance (W) 1k VO = 2VPP f = 10MHz 2nd-Harmonic -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 3rd-Harmonic dBc = dB Below Carrier 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2nd-Harmonic HARMONIC DISTORTION vs SUPPLY VOLTAGE VO = 2VPP RL = 150W f = 10MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) Supply Voltage (±V) Figure 7. HARMONIC DISTORTION vs FREQUENCY -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 1 10 Frequency (MHz) dBc = dB Below Carrier 100 3rd-Harmonic VO = 2VPP RL = 150W -50 -55 Figure 8. HARMONIC DISTORTION vs OUTPUT VOLTAGE RL = 150W f = 10MHz 2nd-Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) -60 -65 -70 -75 -80 -85 -90 -95 -100 0.5 1.5 2nd-Harmonic 3rd-Harmonic dBc = dB Below Carrier 2.5 3.5 4.5 5.5 6.5 7.0 Output Voltage Swing (VPP) Figure 9. TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -50 5 RL = 100W Load Power at Matched 50W Load dBc = dB Below Carrier 4 3 2 1W Internal Power Limit Figure 10. OUTPUT VOLTAGE AND CURRENT LIMITIATIONS Third-Order Spurious Level (dBc) -60 VOUT (V) -70 50MHz -80 20MHz -90 10MHz 1 0 -1 -2 -3 -4 100W Load Line 25W Load Line 50W Load Line 1W Internal Power Limit -100 -6 -4 -2 0 2 4 6 8 10 Single-Tone Load Power (dBm) -5 -200 -150 -100 -50 0 IO (mA) 50 100 150 200 Figure 11. Figure 12. 6 Submit Documentation Feedback OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2 and RL = 150Ω, unless otherwise noted. CHANNEL SWITCHING 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 CHANNEL-TO-CHANNEL SWITCHING TIME Output Voltage (V) Output Voltage (V) Output Voltage Output Voltage 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 VSEL RL = 150W VIN_Ch1 = 400MHz, 1VPP VIN_Ch0 = 0VDC Time (5ns/div) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 Channel Select (V) VSEL VIN_Ch0 = +0.5VDC VIN_Ch1 = -0.5VDC Time (5ns/div) Figure 13. CHANNEL SWITCHING GLITCH Output Voltage (mV) 30 20 10 0 -10 6 VSEL 4 2 0 -2 Time (10ns/div) -20 Output Voltage (V) Figure 14. DISABLE/ENABLE TIME 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 Output Voltage 40 At Matched Load (0V input both channels) VEN Channel Select (V) VIN_Ch1 = 0V VIN_Ch0 = 200MHz, 1VPP Time (20ns/div) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 Figure 15. DISABLE/ENABLE SWITCHING GLITCH Output Voltage (V) 20 15 10 5 -20 At Matched Load -30 -40 Input-Referred Figure 16. CHANNEL-TO-CHANNEL CROSSTALK Crosstalk (dB) 0 -5 -10 6 VEN 4 2 0 -2 Time (100ns/div) -50 -60 -70 -80 -90 1M B0 Selected B1 Driven Enable Voltage (V) R1 Selected R0 Driven 10M 100M Frequency (Hz) 1G Figure 17. Figure 18. Submit Documentation Feedback Enable Voltage (V) Channel Select (V) 7 OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2 and RL = 150Ω, unless otherwise noted. ALL HOSTILE AND ADJACENT-CHANNEL CROSSTALK vs FREQUENCY 0 Input-Referred -10 -20 1k Disabled CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 10k -30 -40 -50 -60 All Hostile Crosstalk -70 -80 1M 10M 100M Frequency (Hz) 1G Adjacent Channel Crosstalk Output Impedance (W) Crosstalk (dB) 100 10 1 Enabled 0.1 100k 1M 10M Frequency (Hz) 100M 1G Figure 19. INPUT IMPEDANCE vs FREQUENCY 10M 60 Figure 20. PSRR vs FREQUENCY Power-Supply Rejection Ratio (dB) -PSRR 50 +PSRR 40 30 20 10 0 100 1M Input Impedance (W) 100k 10k 1k 100 100k 1M 10M Frequency (Hz) 100M 1G 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) Figure 21. SUPPLY CURRENT vs TEMPERATURE 40 38 36 5.0 4.5 Figure 22. TYPICAL DC DRIFT OVER TEMPERATURE Output Offset Voltage (VOS) Left Scale 10 9 Output Offset Voltage (mV) 34 32 30 28 26 24 22 20 -50 -25 0 25 50 75 100 125 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -50 -25 0 25 50 75 100 125 Input Bias Current (IB) Right Scale 7 6 5 4 3 2 1 0 Ambient Temperature (°C) Ambient Temperature (°C) Figure 23. Figure 24. 8 Submit Documentation Feedback Input Bias Current (mA) 4.0 8 Supply Current (mA) OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2 and RL = 150Ω, unless otherwise noted. INPUT VOLTAGE AND CURRENT NOISE 100 Voltage Noise (nV/ÖHz) Current noise (pA/ÖHz) 10 Voltage Noise (6.7nV/ÖHz) Input Current Noise (3.8pA/ÖHz) 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 25. Submit Documentation Feedback 9 OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 APPLICATIONS INFORMATION 2:1 HIGH-SPEED VIDEO MULTIPLEXER OPERATION The OPA3875 can be used as a triple 2:1 high-speed video multiplexer, as illustrated in the front page schematic for an RGB signal. Figure 26 shows a simplified version of the front page schematic in which one output is shown with its input and output impedance matching resistors. that the 75Ω input matching impedance is set here by the parallel combination of 92Ω and 402Ω. In order not to disturb the sync, color burst, and blanking if present, the inverting amplifiers are only switched on during active video. LOGO INSERTER Figure 28 illustrates the principle of overlaying a picture in a picture. The picture comes through U1; the signal to be overlayed comes through U2. Here we have a reference voltage of 0.714V in channel 2 indicating that we will highlight a section of the picture with white (for NTSC-related RGB video). How much white comes through depends on the combination of select 1 and select 2 pins as well as the series output resistance of each OPA3875. To match the 75Ω output impedance of the video cable, the parallel combination of the series output resistance (R and nR) needs to be 75Ω. The two select pins gives us 2 bits of control. By selecting n = 2, you have the capability of a 0% highlight (full original video signal), 33% highlight, 66% highlight, and 100% highlight (all white). By selecting n = 3, you have 0%, 25%, 75%, and 100% highlight capabilities, etc. +5V RGB VIDEO INVERTER Figure 27 illustrates an extension of the previously shown RGB switching circuit with a noninverting signal going through channel 1 and an inverted signal going through channel two. Here, the output impedance of the OPA3875 is set to 75Ω. Looking at the input part of this circuit, we see that the RGB signal is inverted with an OPA3693 fixed gain set in an inverting configuration with a reference voltage on the noninverting node. The reference voltage, set here at 0.714V, has a gain of 1 at the output of the OPA3691 as the input signal is AC-coupled (not represented here). This bias voltage is required to prevent the video from swinging negative. Note also 1/3 OPA3875 VIN_1 75W 75W VOUT 402W VIN_2 75W x1 402W x1 -5V Channel Select EN Figure 26. Triple 2:1 High-Speed Video Multiplexer 10 Submit Documentation Feedback OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 +5V OPA3875 RIN 92W 402W GIN 92W x1 402W x1 75W ROUT BIN 92W 300W 1/3 OPA3693 x1 300W 402W 402W 75W GOUT x1 VREF 300W 300W 1/3 OPA3693 75W BOUT 402W x1 402W VREF 300W 300W 1/3 OPA3693 x1 VREF VREF = 0.749V Channel Select -5V EN Figure 27. RGB Video Inverter Submit Documentation Feedback 11 OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 +5V U1 OPA3875 RIN 75W 402W GIN 75W x1 402W RO BIN 75W x1 402W x1 402W RO BOUT x1 402W 402W x1 VREF GOUT x1 RO ROUT -5V Select 1 Select 2 EN U2 OPA3875 x1 nRO 402W x1 402W nRO x1 402W x1 402W nRO x1 402W 402W x1 VREF VREF = 0.714V RO || nRO = 75W -5V EN Figure 28. Logo Inserter 12 Submit Documentation Feedback OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 ADC INPUT MUX Figure 29 shows the OPA3875 used as a multiplexer in a high-speed data acquisition signal chain. +5V 250W OPA3875 VCC VIN1 x1 250W IN 250W 402W 402W VCM IN 1/2 ADS5232 +3.3V 250W 250W +3.3V VCC VIN2 x1 250W IN 250W 402W 402W VCM IN 1/2 ADS5232 250W VCC 250W +3.3V VIN3 x1 250W IN 250W VCM IN 402W 402W 1/2 ADS5232 VIN4 x1 250W VIN5 x1 VIN6 x1 -5V Channel Select EN Figure 29. ADC Input Multiplexer Submit Documentation Feedback 13 OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 DESIGN-IN TOOLS DEMONSTRATION FIXTURES A printed circuit board (PCB) is available to assist in the initial evaluation of circuit performance using the OPA3875. The fixture is offered free of charge as an unpopulated PCB, delivered with a user's guide. The summary information for this fixture is shown in Table 1. Table 1. OPA3875 Demonstration Fixture PRODUCT OPA3875IDBQ PACKAGE SSOP-16 ORDERING NUMBER DEM-TIV-SSOP-3A LITERATURE NUMBER SBOU043 the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This isolation resistor does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS versus capacitive load and the resulting frequency response at the load; see Figure 5 and Figure 6, respectively. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA3875. Long PCB traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA3875 output pin (see the Board Layout Guidelines section). The demonstration fixture can be requested at the Texas Instruments web site at (www.ti.com) through the OPA3875 product folder. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA875 is available through the Texas Instruments web site at www.ti.com. Use three of these models to simulate the OPA3875. These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance nor do they predict channel-to-channel effects. DC ACCURACY The OPA3875 offers excellent DC signal accuracy. Parameters that influence the output DC offset voltage are: • Output offset voltage • Input bias current • Gain error • Power-supply rejection ratio • Temperature Leaving both temperature and gain error parameters aside, the output offset voltage envelope can be described as shown in Equation 1: VOSO_envelope = VOSO + (RS·Ib) x G ± |5 - (VS+)| x 10 ± |-5 - (VS+)| x 10 - PSRR20 - PSRR+ 20 - CMRR 20 OPERATING SUGGESTIONS DRIVING CAPACITIVE LOADS One of the most demanding, yet very common load conditions is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve ADC linearity. A high-speed device such as the OPA3875 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the device open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease + VCM x 10 With: VOSO: Output offset voltage RS: Input resistance seen by R0, R1, G0, G1, B0, or B1. Ib: Input bias current G: Gain VS+: Positive supply voltage VS–: Negative supply voltage PSRR+: Positive supply PSRR PSRR–: Negative supply PSRR 14 Submit Documentation Feedback OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 Evaluating the front-page schematic, using a worst-case, +25°C offset voltage, bias current and PSRR specifications and operating at ±6V, gives a worst-case output equal to Equation 2: ±14mV + 75W x ±18mA x 2 ± |5 - 6| x 10 ± |-5 - (-6)| x 10 = ±22.7mV - 51 20 - 50 20 NOISE PERFORMANCE The OPA3875 offers an excellent balance between voltage and current noise terms to achieve low output noise. As long as the AC source impedance looking out of the noninverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. Figure 30 shows this device noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. +5V DISTORTION PERFORMANCE The OPA3875 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Also, providing an additional supply decoupling capacitor (0.01µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2X rate while the 3rd-harmonic increases at a little less than the expected 3X rate. Where the test power doubles, the 2nd-harmonic increases only by less than the expected 6dB, whereas the 3rd-harmonic increases by less than the expected 12dB. This also shows up in the two-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20MHz, with 4dBm/tone into a matched 50Ω load (that is, 1VPP for each tone at the load, which requires 4VPP for the overall 2-tone envelope at the output pin), the Typical Characteristics show a 82dBc difference between the test-tone power and the 3rd-order intermodulation spurious levels. en x1 RS ib 1/3 OPA3875 eo eRS 4kTRS 402W x1 402W -5V Channel Select EN Figure 30. Noise Model The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 3 shows the general form for the output noise voltage using the terms shown in Figure 30. eo = 2 en + (ibRS) + 4kTRS 2 2 Dividing this expression by the device gain (2V/V) gives the equivalent input-referred spot noise voltage at the noninverting input as shown in Equation 4. en = en + (ibRS) + 4kTRS 2 2 Evaluating these two equations for the OPA3875 circuit and component values shown in Figure 26 gives a total output spot noise voltage of 13.6nV/√Hz and a total equivalent input spot noise voltage of 6.8nV/√Hz. This total input-referred spot noise voltage is higher than the 6.7nV/√Hz specification for the mux voltage noise alone. This number reflects the noise added to the output by the bias current noise times the source resistor. Submit Documentation Feedback 15 OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 THERMAL ANALYSIS Heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as discussed in this document. In no case should the maximum junction temperature be allowed to exceed +150°C. Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but, for a grounded resistive load, is at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 × RL), where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA3875 in the circuit of Figure 26 operating at the maximum specified ambient temperature of +85°C with all three outputs driving a grounded 100Ω load to +2.5V: PD = 10V ´ 36mA + 3(5 /4 ´ (100W || 804W)) = 571mW Maximum TJ = +85°C + (0.57W ´ 85°C/W) = 133°C 2 b) Minimize the distance (< 0.25") from the power-supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 9, 11, 13, and 15) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA3875. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially leaded resistors can also provide good high-frequency performance. Again, keep their leads and PCB trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Other network components, such as noninverting input termination resistors, should also be placed close to the package. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Figure 5. Low parasitic capacitive loads (< 5pF) may not need an RS because the OPA3875 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the Distortion versus Load plots. This worst-case condition is approaching the maximum +150°C junction temperature. Normally, this extreme case is not encountered. Careful attention to internal power dissipation is required. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high frequency amplifier such as the OPA3875 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output pin can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. 16 Submit Documentation Feedback OPA3875 www.ti.com SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006 With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA3875 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA3875 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in Figure 5. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA3875 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA3875 onto the board. INPUT AND ESD PROTECTION The OPA3875 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies as shown in Figure 31. +VCC External Pin Internal Circuitry -VCC Figure 31. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA3875), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible because high values degrade both noise performance and frequency response. Submit Documentation Feedback 17 PACKAGE OPTION ADDENDUM www.ti.com 29-Jan-2007 PACKAGING INFORMATION Orderable Device OPA3875IDBQ OPA3875IDBQG4 OPA3875IDBQR OPA3875IDBQRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP Package Drawing DBQ DBQ DBQ DBQ Pins Package Eco Plan (2) Qty 16 16 16 16 75 75 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Device Package Pins Site Reel Diameter (mm) 330 Reel Width (mm) 12 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8 W Pin1 (mm) Quadrant 12 PKGORN T1TR-MS P OPA3875IDBQR DBQ 16 MLA 6.4 5.2 2.1 TAPE AND REEL BOX INFORMATION Device OPA3875IDBQR Package DBQ Pins 16 Site MLA Length (mm) 390.0 Width (mm) 348.0 Height (mm) 63.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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