OPA392, OPA2392
SBOS926F – JANUARY 2021 – REVISED DECEMBER 2023
OPAx392 Precision, Low-Offset-Voltage, Low-Noise, Low-Input-Bias-Current,
Rail-to-Rail I/O, e-trim™ Operational Amplifiers
1 Features
3 Description
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The OPAx392 family of operational amplifiers
(OPA392, OPA2392, and OPA4392) features ultra-low
offset, offset drift, and input bias current with rail-to-rail
input and output operation. In addition to precision
dc accuracy, the ac performance is optimized for
low noise and fast-settling transient response. These
features make the OPAx392 an excellent choice
for driving high-precision analog-to-digital converters
(ADCs) or buffering the output of high-resolution,
digital-to-analog converters (DACs).
Low offset voltage: ±10 µV (maximum)
Low-drift: ±0.18 µV/°C
Low input bias current: 10 fA
Low noise: 4.4 nV/√Hz at 10 kHz
Low 1/f noise: 2 µVPP (0.1 Hz to 10 Hz)
Low supply voltage operation: 1.7 V to 5.5 V
Low quiescent current: 1.22 mA
Fast settling: 0.75 µs (1 V to 0.1%)
Fast slew rate: 4.5 V/µs
High output current: +65/–55-mA short circuit
Gain bandwidth: 13 MHz
Rail-to-rail input and output
Specified temperature range: –40°C to +125°C
EMI and RFI filtered inputs
2 Applications
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Multiparameter patient monitor
Electrocardiogram (ECG)
Chemistry and gas analyzer
Optical module
Analog input module
Process analytics (pH, gas, concentration, force
and humidity)
Gas detector
Analog security camera
Merchant DC/DC
Pulse oximeter
Inter-DC interconnect (long-haul, submarine)
Data acquisition (DAQ)
Precision Current
Shunt Monitor
3.3 V
The OPAx392 feature TI's e-trim™ operational
amplifier technology to achieve ultra-low offset
voltage and offset voltage drift without any input
chopping or auto-zero techniques. This technique
enables ultra-low input bias current for sensor inputs
or photodiode current-to-voltage measurements,
creating high-performance transimpedance stages for
optical modules or medical instrumentation.
Device Information
PART NUMBER
OPA392
OPA2392
OPA4392(2)
PACKAGE(1)
CHANNELS
Single
DBV (SOT-23, 5)
Single
DCK (SC70, 5)(2)
Single
YBJ (DSBGA, 6)
Dual
D (SOIC, 8)
Dual
DGK (VSSOP, 8)(2)
Dual
DSG (WSON, 8)(2)
Dual
YBJ (DSBGA, 9)
Quad
PW (TSSOP, 14)(2)
Quad
RTE (WQFN, 16)(2)
+
VIN
OPA392
ADC
±
(1)
(2)
For more information, see Section 11.
Preview information (not Production Data).
3.3 V
Precision Current
Source
±
DAC
OPA392
+
±
OPA392
Optical Power
Monitor
ADC
+
OPAx392 Applications in Optical Modules
OPAx392 Input Offset Voltage Distribution
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
OPA392, OPA2392
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SBOS926F – JANUARY 2021 – REVISED DECEMBER 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Device Comparison Table...............................................3
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information: OPA392.................................... 7
6.5 Thermal Information: OPA2392.................................. 7
6.6 Electrical Characteristics.............................................8
6.7 Typical Characteristics.............................................. 10
7 Detailed Description......................................................17
7.1 Overview................................................................... 17
7.2 Functional Block Diagram......................................... 17
7.3 Feature Description...................................................18
2
7.4 Device Functional Modes..........................................18
8 Application and Implementation.................................. 19
8.1 Application Information............................................. 19
8.2 Typical Application.................................................... 19
8.3 Power Supply Recommendations.............................22
8.4 Layout....................................................................... 22
9 Device and Documentation Support............................23
9.1 Device Support......................................................... 23
9.2 Documentation Support............................................ 23
9.3 Receiving Notification of Documentation Updates....23
9.4 Support Resources................................................... 23
9.5 Trademarks............................................................... 23
9.6 Electrostatic Discharge Caution................................24
9.7 Glossary....................................................................24
10 Revision History.......................................................... 24
11 Mechanical, Packaging, and Orderable
Information.................................................................... 25
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4 Device Comparison Table
DEVICE
CHANNELS
OPA392
PACKAGE
No
DBV (SOT-23, 5)
No
DCK (SC70, 5)(1)
Yes
YBJ (DSBGA, 6)
No
D (SOIC, 8)
No
DGK (VSSOP, 8)(1)
Single
OPA2392
Dual
OPA4392(1)
(1)
SHUTDOWN
Quad
Yes
YBJ (DSBGA, 9)
No
PW (TSSOP, 14)(1)
Yes
RTE (WQFN, 16)(1)
Preview information (not Production Data).
5 Pin Configuration and Functions
OUT
1
V±
2
+IN
3
5
V+
+IN
1
V±
2
±IN
3
5
V+
4
OUT
+
±
±
+
4
±IN
Not to scale
Not to scale
Figure 5-1. OPA392 DBV Package, 5-Pin SOT-23
(Top View)
Figure 5-2. OPA392 DCK Preview Package, 5-Pin
SC70 (Top View)
1
2
A
OUT
V+
B
–IN
EN
C
+IN
V–
Not to scale
Figure 5-3. OPA392 YBJ Package, 6-Pin DSBGA (Top View)
Table 5-1. Pin Functions: OPA392
PIN
NAME
TYPE
NO.
DESCRIPTION
DBV (SOT-23)
DCK (SC70)
YBJ (DSBGA)
EN
—
—
B2
Input
Enable pin. High = amplifier enabled.
–IN
4
3
B1
Input
Inverting input
+IN
3
1
C1
Input
Noninverting input
OUT
1
4
A1
Output
Output
V–
2
2
C2
Power
Negative (lowest) power supply
V+
5
5
A2
Power
Positive (highest) power supply
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OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
OUT A
1
–IN A
2
+IN A
3
V–
4
Not to scale
Thermal
Pad
8
V+
7
OUT B
6
–IN B
5
+IN B
Not to scale
Figure 5-4. OPA2392 D Package, 8-Pin SOIC and
DGK Preview Package, 8-Pin VSSOP (Top View)
Figure 5-5. OPA2392 DSG Preview Package, 8-Pin
WSON With Exposed Thermal Pad (Top View)
1
2
3
A
OUT A
V+
OUT B
B
–IN A
EN
–IN B
C
+IN A
V–
+IN B
Not to scale
Figure 5-6. OPA2392 YBJ Package, 9-Pin DSBGA (Top View)
Table 5-2. Pin Functions: OPA2392
PIN
NO.
NAME
4
TYPE
DESCRIPTION
D (SOIC),
DGK (VSSOP)
DSG (WSON)
YBJ (DSBGA)
EN
—
—
B2
Input
Enable pin. High = both amplifiers enabled.
–IN A
2
2
B1
Input
Inverting input, channel A
+IN A
3
3
C1
Input
Noninverting input, channel A
–IN B
6
6
B3
Input
Inverting input, channel B
+IN B
5
5
C3
Input
Noninverting input, channel B
OUT A
1
1
A1
Output
Output, channel A
OUT B
7
7
A3
Output
Output, channel B
V–
4
4
C2
Power
Negative (lowest) power supply
Positive (highest) power supply
V+
8
8
A2
Power
Thermal Pad
—
Thermal pad
—
—
Connect thermal pad to V–
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V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
+IN A
1
V+
2
–IN D
11
13
4
12
+IN D
11
V–
Thermal Pad
+IN B
3
10
+IN C
–IN B
4
9
–IN C
8
V+
OUT C
+IN D
OUT D
12
14
3
7
+IN A
EN CD
±IN D
OUT A
13
15
2
6
±IN A
EN AB
OUT D
–IN A
14
5
1
OUT B
OUT A
16
SBOS926F – JANUARY 2021 – REVISED DECEMBER 2023
Not to scale
Figure 5-7. OPA4392 PW Preview Package, 14-Pin
TSSOP (Top View)
Not to scale
Figure 5-8. OPA4392 RTE Preview Package, 16-Pin
WQFN (Top View)
Table 5-3. Pin Functions: OPA4392
PIN
NAME
NO.
TYPE
DESCRIPTION
PW (TSSOP)
RTE (WQFN)
EN AB
—
6
Input
Enable pin for A and B amplifiers. High = amplifiers A and B are enabled.
EN CD
—
7
Input
Enable pin for C and D amplifiers. High = amplifiers C and D are enabled.
–IN A
2
16
Input
Inverting input, channel A
+IN A
3
1
Input
Noninverting input, channel A
–IN B
6
4
Input
Inverting input, channel B
+IN B
5
3
Input
Noninverting input, channel B
–IN C
9
9
Input
Inverting input, channel C
+IN C
10
10
Input
Noninverting input, channel C
–IN D
13
13
Input
Inverting input, channel D
+IN D
12
12
Input
Noninverting input, channel D
OUT A
1
15
Output
Output, channel A
OUT B
7
5
Output
Output, channel B
OUT C
8
8
Output
Output, channel C
OUT D
14
14
Output
Output, channel D
Thermal Pad
—
Thermal Pad
Power
Connect thermal pad to V–
V–
11
11
Power
Negative (lowest) power supply
V+
4
2
Power
Positive (highest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VS
Supply voltage, VS = (V+) – (V–)
Input voltage, all pins
MAX
Single-supply
6
Dual-supply
Common-mode
UNIT
V
±3
(V–) – 0.5
Differential
(V+) + 0.5
V
(V+) – (V–) + 0.2
Input current, all pins
±10
Output short circuit(2)
Continuous
Continuous
mA
TA
Operating temperature
–55
150
°C
TJ
Junction temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
6
VS
Supply voltage
TA
Specified temperature
Single-supply
Dual-supply
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NOM
MAX
1.7
5.5
±0.85
±2.75
–40
125
UNIT
V
°C
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6.4 Thermal Information: OPA392
OPA392
THERMAL
METRIC(1)
DBV (SOT-23)
YBJ (DSBGA)
5 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
187.1
135.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
107.4
1.1
°C/W
RθJB
Junction-to-board thermal resistance
57.5
38.8
°C/W
ΨJT
Junction-to-top characterization parameter
33.5
0.4
°C/W
ΨJB
Junction-to-board characterization parameter
57.1
38.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2392
OPA2392
THERMAL METRIC(1)
D (SOIC)
DGK (VSSOP)
YBJ (DSBGA)
UNIT
8 PINS
8 PINS
9 PINS
RθJA
Junction-to-ambient thermal resistance
131.7
165
110.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
71.4
53
0.7
°C/W
RθJB
Junction-to-board thermal resistance
75.2
87
32.1
°C/W
ΨJT
Junction-to-top characterization parameter
21.8
4.9
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
74.4
85
32.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
at TA = 25°C, VS = 1.7 V to 5.5 V (single-supply) or VS = ±0.85 V to ±2.75 V (dual-supply), RL = 10 kΩ connected to VS / 2,
VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5.0 V
VOS
Input offset voltage
VS = 5.0 V,
VCM = (V+) – 200 mV
±1
±10
OPA2392D
±1
±20
OPA392YBJ,
OPA2392YBJ
±1
±25
±2
±30
±2
±85
OPA2392YBJ
VS = 5.0 V,
TA = –40°C to +125°C(1)
±100
VCM = V–,
TA = –40°C to +125°C(1)
±125
TA = 0°C to 85°C
dVOS/dT
Input offset voltage drift
Power supply rejection
ratio
PSRR
TA = –40°C to
VS = 5.0 V
±0.16
+125°C(1)
±0.6
VCM = 5.0 V,
TA = –40°C to +125°C(1)
±0.18
TA = –40°C to +125°C(1)
μV/°C
±0.9
±30
VCM = V–
μV
±80
μV/V
INPUT BIAS CURRENT
±0.01
Input bias current(1)
IB
±5
TA = –40°C to +125°C
±30
±0.01
Input offset current(1)
IOS
±0.8
TA = –40°C to +85°C
pA
±0.8
TA = –40°C to +85°C
±5
TA = –40°C to +125°C
±30
pA
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
VCM = (V+) – 0.3
80
VCM = (V+) – 0.3
10.4
6.5
Input voltage noise density f = 1 kHz
nV/√Hz
4.4
f = 10 kHz
iN
μVPP
3.2
42
f = 10 Hz
eN
2.0
VCM = (V+) – 0.3
Input current noise density f = 1 kHz
VCM = (V+) – 0.3
5.8
OPA392DBV
70
OPA392YBJ, OPA2392
25
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
range
VCM
CMRR
Common-mode rejection
ratio
V–
(V–) < VCM < (V+) – 1.5 V
(V–) < VCM < (V+),
TA = –40°C to +125°C(1)
75
TA = –40°C to +125°C
VS = 5.5 V
V+
V
120
113
66
97
88
111
dB
INPUT CAPACITANCE
8
ZID
Differential
1013 || 2.8
Ω || pF
ZICM
Common-mode
1013 || 3.5
Ω || pF
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6.6 Electrical Characteristics (continued)
at TA = 25°C, VS = 1.7 V to 5.5 V (single-supply) or VS = ±0.85 V to ±2.75 V (dual-supply), RL = 10 kΩ connected to VS / 2,
VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
(V–) + 50 mV < VOUT <
(V+) – 50 mV
115
132
(V–) + 100 mV < VO <
(V+) – 100 mV, RL = 2 kΩ
110
128
(V–) + 100 mV < VOUT <
(V+) – 100 mV, RL = 2 kΩ,
TA = –40°C to +125°C(1)
100
(V–) + 50 mV < VOUT <
(V+) – 50 mV,
VCM = (V+) – 1.15 V
106
124
(V–) + 100 mV < VOUT <
(V+) – 100 mV, RL = 2 kΩ,
VCM = (V+) – 1.15 V
106
124
(V–) + 100 mV < VOUT <
(V+) – 100 mV, RL = 2 kΩ,
VCM = (V+) – 1.15 V,
TA = –40°C to +125°C(1)
100
MAX
UNIT
OPEN-LOOP GAIN
VS = 5.5 V
AOL
Open-loop voltage gain
VS = 1.7 V
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
tS
Slew rate
4-V step, gain = +1
Phase margin
CL = 100 pF
Settling time
Overload recovery time
THD+N
AV = 1000 V/V
Total harmonic distortion +
noise
13
falling
4.5
rising
3.5
MHz
V/μs
45
To 0.1%, 2-V step, gain = +1
°
0.75
To 0.01%, 2-V step, gain = +1
μs
1
VIN × gain > VS
0.45
μs
VOUT = 1 VRMS, gain = +1, f = 1 kHz,
VCM = (V–) + 1.5 V
–112
dB
0.00025
%
OUTPUT
Voltage output swing from
both rails
20
VS = 1.7 V
RL = 2 kΩ
20
VS = 5.5 V
ISC
Short-circuit current
RO
Open-loop output
impedance
30
RL = 2 kΩ
mV
35
Sinking, VS = 5.5 V
–55
Sourcing, VS = 5.5 V
mA
65
f = 1 MHz
120
Ω
POWER SUPPLY
IQ
Quiescent current per
amplifier
1.22
IO = 0 mA
TA = –40°C to +125°C(1)
1.4
1.5
mA
SHUTDOWN (OPA392YBJ, OPA2392YBJ and OPA4392RTE Only)
IQSD
Quiescent current per
amplifier
All amplifiers disabled, EN = V–
VIH
High-level input voltage
Amplifier enabled
VIL
Low-level input voltage
Amplifier disabled
tON
Amplifier enable time
G = 1, VOUT = 0.9 × VS/2, two amplifiers enabled
tOFF
Amplifier disable time
G = 1, VOUT = 0.1 × VS/2, two amplifiers disabled
EN pin input leakage
current
VIH = V+
0.02
VIL = V–
1
(1)
6
µA
(V+) – 0.5
V
(V–) + 0.5
V
9.5
µs
7.8
µs
µA
Specification established from device population bench system measurements across multiple lots.
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6.7 Typical Characteristics
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
VS = 5.0 V
VS = 5.0 V, VCM = 4.8 V
Figure 6-1. Offset Voltage Distribution
Figure 6-2. Offset Voltage Distribution
VS = 5.0 V
TA = –40°C
Figure 6-3. Offset Voltage Distribution
Figure 6-4. Offset Voltage vs Common-Mode Voltage
TA = +125°C
Figure 6-5. Offset Voltage vs Common-Mode Voltage
10
Figure 6-6. Offset Voltage vs Common-Mode Voltage
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6.7 Typical Characteristics (continued)
30
30
25
25
20
20
Amplifiers (%)
Amplifiers (%)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
15
10
5
0
15
10
5
1
1.04 1.08 1.12 1.16
1.2
1.24 1.28 1.32 1.36
0
0.9
1.4
Quiescent Current (mA)
0.95
1
1.05
1.1
1.15
1.2
1.25
Quiescent Current (mA)
C004
1.3
C002
VS = 1.7 V
Figure 6-7. Quiescent Current Distribution
150
180
Gain
Phase
120
150
90
120
60
90
30
60
0
30
-30
10m 100m
Phase ()
Gain (dB)
Figure 6-8. Quiescent Current Distribution
0
1
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
Figure 6-9. Open-Loop Gain and Phase vs Frequency
Figure 6-10. Closed-Loop Gain vs Frequency
VS = 1.7 V
VS = 3.3 V
Figure 6-11. Input Bias Current vs Common-Mode Voltage
Figure 6-12. Input Bias Current vs Common-Mode Voltage
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Figure 6-13. Input Bias Current vs Common-Mode Voltage
Figure 6-14. Input Bias Current vs Temperature
Figure 6-15. Output Voltage Swing vs Output Current (Sourcing)
Figure 6-16. Output Voltage Swing vs Output Current (Sinking)
VS = ±0.85 V
VS = ±0.85 V
Figure 6-17. Output Voltage Swing vs Output Current (Sourcing)
12
Figure 6-18. Output Voltage Swing vs Output Current (Sinking)
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
5 Units
Figure 6-19. CMRR and PSRR vs Frequency
Figure 6-20. CMRR vs Temperature
5 Units
Figure 6-21. PSRR vs Temperature
Figure 6-22. Voltage Noise vs Frequency
f = 1 kHz
VOUT = 1 VRMS
Figure 6-23. THD+N Ratio vs Frequency
Figure 6-24. THD+N vs Output Amplitude
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
5 Units
Figure 6-25. 0.1-Hz to 10-Hz Noise
Figure 6-26. Quiescent Current vs Supply Voltage
5 Units
5 Units
Figure 6-27. Quiescent Current vs Temperature
Figure 6-28. Open-Loop Gain vs Temperature
G = –1
Figure 6-29. Open-Loop Output Impedance vs Frequency
14
Figure 6-30. Small-Signal Overshoot vs Capacitive Load
(10‑mV Step)
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
G=1
Figure 6-31. Small-Signal Overshoot vs Capacitive Load
(10‑mV Step)
Figure 6-32. No Phase Reversal
Figure 6-33. Positive Overload Recovery
Figure 6-34. Negative Overload Recovery
G=1
G = –1
Figure 6-35. Small-Signal Step Response (10-mV Step)
Figure 6-36. Small-Signal Step Response (10-mV Step)
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
G=1
G = –1
Figure 6-37. Large-Signal Step Response (4-V Step)
Figure 6-38. Large-Signal Step Response (4-V Step)
PRF = –10 dBm
Figure 6-39. Settling Time
16
Figure 6-40. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx392 is a family of low offset, low-noise e-trim operational amplifiers (op amps) that uses a proprietary
offset trim technique. These op amps offer ultra-low input offset voltage and drift and achieve excellent input and
output dynamic linearity. The OPAx392 operate from 1.7 V to 5.5 V, are unity-gain stable, and are designed for a
wide range of general-purpose and precision applications.
The amplifiers feature state-of-the-art CMOS technology and advanced design features that help achieve
extremely low input bias current, wide input and output voltage ranges, high loop gain, and low, flat output
impedance in small package options. The OPAx392 strengths also include 13‑MHz bandwidth, 4.4‑nV/√Hz noise
spectral density, and low 1/f noise. These features make the OPAx392 an exceptional choice for interfacing with
sensors, photodiodes, and high-performance analog-to-digital converters (ADCs).
7.2 Functional Block Diagram
V+
Reference
Current
+IN
±IN
VBIAS1
Class AB
Control
Circuitry
OUT
VBIAS2
Ví
(Ground)
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7.3 Feature Description
7.3.1 Low Operating Voltage
The OPAx392 family can be used with single or dual supplies from an operating range of VS = 1.7 V (±0.85 V) up
to 5.5 V (±2.75 V). The offset voltage is trimmed at 5.0 V, however, the device maintains ultra-low offset voltages
down to VS = 1.7 V.
Key parameters that vary over the supply voltage or temperature range are shown in the Typical Characteristics.
7.3.2 Low Input Bias Current
The typical input bias current of the OPAx392 is extremely low (typically 10 fA). Input bias current is dominated
by leakage current from the ESD protection diodes, which is proportional to the area of the diode. The
OPAx392 is able to achieve ultra-low input bias current as a result of modern process technology and advanced
electrostatic discharge (ESD) protection design that minimizes the area of the diode.
In overdriven conditions, the bias current can increase significantly. The most common cause of an overdriven
condition occurs when the operational amplifier is outside of the linear range of operation. When the output of
the operational amplifier is driven to one of the supply rails, the feedback loop requirements cannot be satisfied
and a differential input voltage develops across the input pins. This differential input voltage results in the
forward-biasing of the ESD cells. Figure 7-1 shows the equivalent circuit.
V+
10
±
+IN
10
±IN
CORE
+
V±
Figure 7-1. Equivalent Input Circuit
7.4 Device Functional Modes
The OPAx392 family is operational when the power-supply voltage is greater than 1.7 V (±0.85 V). For devices
that use the EN function (see Section 5), the devices are disabled when the EN pin is low. In this state, quiescent
current is significantly reduced, and the output is high impedance. The maximum specified power-supply voltage
for the OPAx392 is 5.5 V (±2.75 V).
18
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx392 is a unity-gain stable, precision operational amplifier family free from unexpected output and
phase reversal. The use of proprietary e-trim operational amplifier technology gives the benefit of low input
offset voltage over time and temperature, along with ultra-low input bias current. The OPAx392 are optimized
for full rail-to-rail input, allowing for low-voltage, single-supply operation or split-supply use. These miniature,
high-precision, low-noise amplifiers offer high-impedance inputs that have a common-mode range to the supply
rail, with low offset across the supply range, and a rail-to-rail output that swings within 5 mV of the supplies
under normal test conditions. The OPAx392 precision amplifiers are designed for upstream analog signal chain
applications in low or high gains, as well as downstream signal chain functions such as DAC buffering.
8.2 Typical Application
This single-supply, low-side, bidirectional current-sensing design example detects load currents from –1 A to
+1 A. The single-ended output spans from 110 mV to 3.19 V. This design uses the OPA392 because of the low
offset voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier and
the other amplifier provides the reference voltage.
Figure 8-1 shows the schematic.
VCC
VREF
VCC
R5
+
U1B
ILOAD
R6
R2
VBUS
+
±
R1
+
VSHUNT
±
+
RSHUNT
VOUT
R3
U1A
RL
VCC
R4
Figure 8-1. Bidirectional Current-Sensing Schematic
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8.2.1 Design Requirements
This design example has the following requirements:
•
•
•
Supply voltage: 3.3 V
Input: –1 A to +1 A
Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
8.2.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor, RSHUNT, to develop the shunt voltage, VSHUNT. The
shunt voltage is then amplified by the difference amplifier consisting of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by Equation 1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
(1)
where
•
•
•
VSHUNT = ILOAD ´ RSHUNT
R
GainDiff_Amp = 4
R3
VREF = VCC ´
R6
R5 + R6
There are two types of errors in this design: offset and gain. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4 / R3 matches R2 / R1. The latter value affects the CMRR of
the difference amplifier, ultimately translating to an offset error.
The value of VSHUNT is the ground potential for the system load because VSHUNT is a low-side measurement.
Therefore, a maximum value must be placed on VSHUNT. In this design, the maximum value for VSHUNT is set
to 100 mV. Equation 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of
100 mV and maximum load current of 1 A.
RSHUNT(Max) =
VSHUNT(Max) 100 mV
= 100 mW
=
ILOAD(Max)
1A
(2)
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
is selected. If greater accuracy is required, select a 0.1% resistor or better.
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to +100 mV. This voltage is
divided down by R1 and R2 before reaching the operational amplifier, U1A. Make sure that the voltage present
at the noninverting node of U1A is within the common-mode range of the device. Therefore, use an operational
amplifier, such as the OPA392, that has a common-mode range that extends below the negative supply voltage.
Finally, to minimize offset error, the OPA392 has a typical offset voltage of merely ±0.25 µV (±5 µV maximum).
Given a symmetric load current of –1 A to +1 A, the voltage divider resistors (R5 and R6) must be equal. To
be consistent with the shunt resistor, a tolerance of 0.5% is selected. To minimize power consumption, 10‑kΩ
resistors are used.
20
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To set the gain of the difference amplifier, the common-mode range and output swing of the OPA392 must be
considered. Equation 3 and Equation 4 depict the typical common-mode range and maximum output swing,
respectively, of the OPA392 given a 3.3‑V supply.
–100 mV < VCM < 3.4 V
(3)
100 mV < VOUT < 3.2 V
(4)
The gain of the difference amplifier can now be calculated as shown in Equation 5:
GainDiff_Amp =
VOUT_Max - VOUT_Min
3.2 V - 100 mV
V
= 15.5
=
V
100
mW ´ [1 A - (- 1A)]
RSHUNT ´ (IMAX - IMIN)
(5)
The resistor value selected for R1 and R3 is 1 kΩ. 15.4 kΩ is selected for R2 and R4 because this number is the
nearest standard value. Therefore, the calculated gain of the difference amplifier is 15.4 V/V.
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors
are selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.
8.2.3 Application Curve
Output Voltage (V)
3.30
1.65
0
-1.0
-0.5
0
Input Current (A)
0.5
1.0
Figure 8-2. Bidirectional Current-Sensing Circuit Performance: Output Voltage vs Input Current
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8.3 Power Supply Recommendations
The OPAx392 are specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V).
CAUTION
Exceeding supply voltages listed in the Absolute Maximum Ratings table can permanently damage
the device.
8.4 Layout
8.4.1 Layout Guidelines
Pay attention to good layout practice. Keep traces short, and when possible, use a printed-circuit board
(PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place
a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied throughout the analog
circuit to improve performance and provide benefits such as reducing the electromagnetic interference (EMI)
susceptibility.
For lowest offset voltage and precision performance, circuit layout and mechanical conditions must be optimized.
Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed
from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by making
sure these potentials are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Use guard traces to minimize leakage current when ultra-low bias current is required.
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or higher, depending on materials used.
8.4.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 8-3. OPA392 Layout Schematic
VS
CBYPASS
VOUT
OUT
V+
Minimize
parasitic
inductance by
placing bypass
capacitor close
to V+.
V±
+IN
Keep high
impedance
input signal
away from
noisy traces.
±IN
RG
VIN
RF
Route trace under package for output to
feedback resistor connection.
Figure 8-4. OPA392 Layout Example
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
9.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers
extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments
offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, Amplifier Input Common-Mode and Output-Swing Limitations application note
Texas Instruments, Offset Correction Methods: Laser Trim, e-Trim™, and Chopper application brief
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
e-trim™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
All trademarks are the property of their respective owners.
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9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2023) to Revision F (December 2023)
Page
• Changed OPA392 YBJ (DSBGA, 6) package status from advanced information (preview with samples) to
production data (active) and added associated content..................................................................................... 1
• Changed OPA2392 D (SOIC, 8) package status from preview to production data (active) and added
associated content..............................................................................................................................................1
• Changed OPA2392 DGK (VSSOP, 8) package status from preview to advanced information (preview with
samples) and added associated content............................................................................................................ 1
Changes from Revision D (December 2022) to Revision E (September 2023)
Page
• Changed OPA392 in YBJ package (DSBGA, 6) status from preview to advanced information (preview with
samples) and added associated content............................................................................................................ 1
• Changed OPA2392 in D package (SOIC, 8) status from preview to advanced information (preview with
samples) and added associated content............................................................................................................ 1
• Added OPA2392 in DSG (WSON, 8) preview package and associated pin configuration................................. 1
• Changed ESD Ratings to bidirectional values....................................................................................................6
Changes from Revision C (July 2022) to Revision D (December 2022)
Page
• Changed OPA2392 in YBJ (DSBGA, 9) from advanced information (preview) to production data (active) and
added associated content...................................................................................................................................1
Changes from Revision B (October 2021) to Revision C (July 2022)
Page
• Changed OPA2392 device to advanced information (preview).......................................................................... 1
• Changed Figure 6-9 Y-axis scales for clarity.................................................................................................... 10
Changes from Revision A (August 2021) to Revision B (October 2021)
Page
• Added footnote to input bias current and input offset current room temperature specification.......................... 8
• Added Figures 6-4, 6-5, and 6-6, Offset Voltage vs Common-Mode Voltage ................................................. 10
• Changed Figure 6-9, Open-Loop Gain and Phase vs Frequency, to correct data .......................................... 10
• Changed Figure 6-10, Closed-Loop Gain and Phase vs Frequency, to correct data.......................................10
• Added Figure 6-14, Input Bias Current vs Temperature ..................................................................................10
• Changed Figure 6-23, THD+N Ratio vs Frequency to correct data................................................................. 10
Changes from Revision * (January 2021) to Revision A (August 2021)
Page
• Changed OPA392 device in DBV (SOT-23-5) package from advanced information (preview) to production
data (active)........................................................................................................................................................1
24
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA2392DR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O2392D
Samples
OPA2392YBJR
ACTIVE
DSBGA
YBJ
9
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
O23
Samples
OPA2392YBJT
ACTIVE
DSBGA
YBJ
9
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
O23
Samples
OPA392DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
23GT
Samples
OPA392DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
23GT
Samples
OPA392YBJR
ACTIVE
DSBGA
YBJ
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
PL
Samples
XOPA392YBJR
ACTIVE
DSBGA
YBJ
6
3000
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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