0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
OPA4140AIPW

OPA4140AIPW

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP14_5X4.4MM

  • 描述:

    IC OPAMP JFET 11MHZ RRO 14TSSOP

  • 数据手册
  • 价格&库存
OPA4140AIPW 数据手册
OPA140, OPA2140, OPA4140 SBOS498E – JULY 2010 – REVISED JULY 2021 OPAx140 High-Precision, Low-Noise, Rail-to-Rail Output, 11-MHz, JFET Op Amp 1 Features 3 Description • • • • • • • • • • • • The OPA140, OPA2140, and OPA4140 (OPAx140) operational amplifier (op amp) family is a series of low-power JFET input amplifiers that features good drift and low input bias current. The rail-torail output swing and input range that includes V– allow designers to take advantage of the lownoise characteristics of JFET amplifiers while also interfacing to modern, single-supply, precision analogto-digital converters (ADCs) and digital-to-analog converters (DACs). Very-low offset drift: 1 μV/°C maximum Very-low offset: 120 μV Low input bias current: 10 pA maximum Very-low 1/f noise: 250 nVPP, 0.1 Hz to 10 Hz Low noise: 5.1 nV/√Hz Slew rate: 20 V/μs Low supply current: 2 mA maximum Input voltage range includes V– supply Single-supply operation: 4.5 V to 36 V Dual-supply operation: ±2.25 V to ±18 V No phase reversal Packages: – Industry-standard SOIC, SON (Preview), SOT-23, TSSOP, and VSSOP 2 Applications Intra-dc interconnect (metro) Semiconductor test Chemistry and gas analyzer DC power supply, ac source, electronic load Data acquisition (DAQ) Lab and field instrumentation VSUPPLY = ±18V All versions are fully specified from –40°C to +125°C for use in the most challenging environments. The OPA140 (single) is available in the 5‑pin SOT-23 8‑pin VSSOP and 8‑pin SOIC packages. The OPA2140 (dual) is available in 8‑pin SON, 8‑pin VSSOP, and 8‑pin SOIC packages. The OPA4140 (quad) is available in the 14‑pin SOIC and 14‑pin TSSOP packages. Competitor’s Device Device Information OPAx140 PART NUMBER 200nV/div • • • • • • The OPA140 achieves 11-MHz unity-gain bandwidth and 20-V/μs slew rate while consuming only 1.8 mA (typical) of quiescent current. This device runs on a single 4.5-V to 36-V supply or dual ±2.25-V to ±18-V supplies. OPA140 OPA2140 Time (1s/div) OPA4140 0.1-Hz to 10-Hz Noise (1) PACKAGE(1) BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.90 mm SOT23 (5) 2.90 mm × 1.60 mm VSSOP (8) 3.00 mm × 3.00 mm SOIC (8) 4.90 mm × 3.90 mm SON (8) - Preview 3.00 mm x 3.00 mm VSSOP (8) 3.00 mm × 3.00 mm SOIC (14) 8.65 mm × 3.90 mm TSSOP (14) 5.00 mm × 4.40 mm For all available packages, see the package option addendum at the end of the data sheet. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information: OPA140.................................... 6 6.5 Thermal Information: OPA2140.................................. 6 6.6 Thermal Information: OPA4140.................................. 6 6.7 Electrical Characteristics: VS = 4.5 V to 36 V; ±2.25 V to ±18 V............................................................7 6.8 Typical Characteristics................................................ 8 7 Detailed Description......................................................15 7.1 Overview................................................................... 15 7.2 Functional Block Diagram......................................... 15 7.3 Feature Description...................................................15 7.4 Device Functional Modes..........................................22 8 Application and Implementation.................................. 23 8.1 Application Information............................................. 23 8.2 Typical Application.................................................... 23 9 Power Supply Recommendations................................24 10 Layout...........................................................................25 10.1 Layout Guidelines................................................... 25 10.2 Layout Example...................................................... 25 11 Device and Documentation Support..........................26 11.1 Device Support........................................................26 11.2 Documentation Support.......................................... 26 11.3 Receiving Notification of Documentation Updates.. 26 11.4 Support Resources................................................. 27 11.5 Trademarks............................................................. 27 11.6 Electrostatic Discharge Caution.............................. 27 11.7 Glossary.................................................................. 27 12 Mechanical, Packaging, and Orderable Information.................................................................... 27 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (January 2019) to Revision E (July 2021) Page • Added OPA2140 DRG preview package and associated content to data sheet................................................ 1 Changes from Revision C (August 2016) to Revision D (January 2019) Page • Changed Figure 12 x-axis title From: Frequency (Hz) To: Output Amplitude (VRMS)......................................... 8 Changes from Revision B (November 2015) to Revision C (August 2016) Page • Changed units for En Input voltage noise From: µV To: nV in Section 6.7 ........................................................ 7 Changes from Revision A (August 2010) to Revision B (November 2015) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1 • Changed title of Table 6-1 From: Characteristic Performance Measurements To: Table of Graphs ..................8 • Changed section 7.37 title From: Power Dissipation and Thermal Protection To: Thermal Protection ........... 18 Changes from Revision * (July 2010) to Revision A (August 2010) Page • Changed device and data sheet status to production data status...................................................................... 1 • Added SOIC (8) (MSOP) packages....................................................................................................................3 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 5 Pin Configuration and Functions NC 1 ±IN 2 +IN 3 V± 4 8 NC ± 7 V+ + 6 OUT 5 NC Figure 5-1. OPA140: D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View OUT 1 V- 2 +IN 3 5 V+ 4 -IN Figure 5-2. OPA140: DBV (5-Pin SOT-23) Package, Top View Table 5-1. Pin Functions: OPA140 PIN OPA140 NAME +IN I/O D (SOIC), DGK (VSSOP) DBV (SOT) 3 3 DESCRIPTION I Noninverting input Inverting input –IN 2 4 I NC 1, 5, 8 — — No internal connection (can be left floating) OUT 6 1 O Output V+ 7 5 — Positive (highest) power supply V– 4 2 — Negative (lowest) power supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 3 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 A 2 – V– 3 + +IN A B – –IN A 1 + OUT A 8 V+ 7 OUT B –IN A 2 6 –IN B +IN A 3 8 V+ OUT A 1 7 OUT B A 6 –IN B B 4 5 +IN B 5 +IN B V– 4 Figure 5-3. OPA2140: D (8-Pin SOIC) and DGK (8Pin VSSOP) Packages, Top View OUT A 1 ±IN A 2 A Figure 5-4. OPA2140: DRG (8-Pin SON) Package, Top View (Preview) 14 OUT D 13 ±IN D D +IN A 3 12 +IN D V+ 4 11 V± + IN B 5 10 + IN C B C ±IN B 6 9 ±IN C OUT B 7 8 OUT C Figure 5-5. OPA4140: D (14-Pin SOIC) and PW (14-Pin TSSOP) Packages, Top View Table 5-2. Pin Functions: OPA2140 and OPA4140 PIN OPA2140 OPA4140 D (SOIC), DGK (VSSOP) DRG (SON) D (SOIC), PW (TSSOP) +IN A 3 3 I Noninverting input, channel A +IN B 5 5 I Noninverting input, channel B +IN C — 10 I Noninverting input, channel C +IN D — 12 I Noninverting input, channel D –IN A 2 2 I Inverting input, channel A –IN B 6 6 I Inverting input, channel B –IN C — 9 I Inverting input, channel C –IN D — 13 I Inverting input, channel D OUT A 1 1 O Output, channel A OUT B 7 7 O Output, channel B OUT C — 8 O Output, channel C OUT D — 14 O Output, channel D V+ 8 4 — Positive (highest) power supply V– 4 11 — Negative (lowest) power supply NAME 4 I/O DESCRIPTION Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN Supply voltage, VS = (V+) – (V–) Signal input pins (V–) – 0.5 (V+) + 0.5 Current(2) –10 10 –55 (3) 150 Junction 150 Storage, Tstg (2) V mA Continuous Operating (1) UNIT V Voltage(2) Output short circuit(3) Temperature MAX 40 –65 °C 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should be current-limited to 10 mA or less. Short-circuit to VS/2 (ground in symmetrical dual-supply setups), one amplifier per package. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Charged-device model (CDM), per JEDEC specification JESD22-C101(2) VALUE UNIT ±2000 V ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltage Specified temperature NOM MAX UNIT ±2.25 ±18 V –40 125 °C Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 5 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 6.4 Thermal Information: OPA140 OPA140 THERMAL METRIC(1) D (SOIC) DBV (SOT) DGK (VSSOP) 8 PINS 5 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 160 210 180 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75 200 55 °C/W RθJB Junction-to-board thermal resistance 60 110 130 °C/W ψJT Junction-to-top characterization parameter 9 40 N/A °C/W ψJB Junction-to-board characterization parameter 50 105 120 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Thermal Information: OPA2140 OPA2140 THERMAL METRIC(1) D (SOIC) DGK (VSSOP) DRG (SON) 8 PINS 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 160 180 50.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75 55 50.6 °C/W RθJB Junction-to-board thermal resistance 60 130 23.3 °C/W ψJT Junction-to-top characterization parameter 9 N/A 0.9 °C/W ψJB Junction-to-board characterization parameter 50 120 23.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 7.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.6 Thermal Information: OPA4140 OPA4140 THERMAL METRIC(1) PW (TSSOP) UNIT 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 97 135 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56 45 °C/W RθJB Junction-to-board thermal resistance 53 66 °C/W ψJT Junction-to-top characterization parameter 19 N/A °C/W ψJB Junction-to-board characterization parameter 46 60 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) 6 D (SOIC) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 6.7 Electrical Characteristics: VS = 4.5 V to 36 V; ±2.25 V to ±18 V at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 30 120 UNIT OFFSET VOLTAGE VOS Input offset voltage VS = ±18 V, TA = –40°C to 125°C dVOS/dT Input offset voltage drift VS = ±18 V, TA = –40°C to 125°C PSRR Power-supply rejection ratio VS = ±2.25 V to ±18 V, TA = –40°C to 125°C 220 VS = ±2.25 V to ±18 V, TA = –40°C to 125°C µV ±4 µV/V ±0.35 1 µV/°C ±0.1 ±0.5 µV/V ±0.5 ±10 pA ±3 nA ±0.5 ±10 pA ±1 nA INPUT BIAS CURRENT IB IOS Input bias current Input offset current TA = –40°C to 125°C TA = –40°C to 125°C NOISE En Input voltage noise f = 0.1 Hz to 10 Hz 250 nVPP f = 0.1 Hz to 10 Hz 42 nVRMS f = 10 Hz en in Input voltage noise density Input current noise density 8 f = 100 Hz 5.8 f = 1 kHz 5.1 f = 1 kHz 0.8 nV/√ Hz fA/√ Hz INPUT VOLTAGE VCM CMRR Common-mode voltage TA = –40°C to 125°C Common-mode rejection VS = ±18 V, VCM = (V–) – 0.1 V ratio to (V+) – 3.5 V (V–) – 0.1 126 TA = –40°C to 125°C (V+) – 3.5 140 V dB 120 INPUT IMPEDANCE ZID Differential ZIC Common-mode VCM = (V–) – 0.1 V to (V+) – 3.5 V 1013 || 10 Ω || pF 1013 || 7 Ω || pF OPEN-LOOP GAIN AOL Open-loop voltage gain VO = (V–) + 0.35 V to (V+) – 0.35 V, RL = 10 kΩ VO = (V–) + 0.35 V to (V+) – 0.35 V, RL = 2 kΩ TA = –40°C to 125°C 120 126 114 126 dB 108 FREQUENCY RESPONSE BW Gain bandwidth product 11 MHz SR Slew rate 20 V/µs 880 ns 1.6 µs 600 ns 12-bit ts Settling time tOR Overload recovery time THD+N Total harmonic distortion 1 kHz, G = 1, VO = 3.5 VRMS + noise 16-bit 0.00005% OUTPUT VO Voltage output ISC Short-circuit current CLOAD Capacitive load drive ZO Open-loop output impedance RLOAD = 10 kΩ, AOL ≥ 108 dB (V–) + 0.2 (V+) – 0.2 RLOAD = 2 kΩ, AOL ≥ 108 dB (V–) + 0.35 (V+) – 0.35 Source 36 Sink –30 V mA See Figure 6-19 and Figure 6-20 f = 1 MHz, IO = 0 A (See Figure 6-18) 16 Ω Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 7 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 6.7 Electrical Characteristics: VS = 4.5 V to 36 V; ±2.25 V to ±18 V (continued) at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VS IQ Power-supply voltage Quiescent current per amplifier 4.5 (±2.25) 9 (±18) IO = 0 A 1.8 TA = –40°C to 125°C 2 2.7 V mA CHANNEL SEPARATION Channel separation At dc 0.02 At 100 kHz 10 μV/V 6.8 Typical Characteristics at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) Table 6-1. Table of Graphs DESCRIPTION FIGURE Offset Voltage Production Distribution Offset Voltage Production Distribution Offset Voltage Drift Distribution Offset Voltage Drift Distribution Offset Voltage vs Common-Mode Voltage (Maximum Supply) IB vs Common-Mode Voltage Offset Voltage vs Common-Mode Voltage IB vs Common-Mode Voltage Input Offset Voltage vs Temperature Input Offset Voltage vs Temperature (144 Amplifiers) Output Voltage Swing vs Output Current Output Voltage Swing vs Output Current (Maximum Supply) CMRR and PSRR vs Frequency (RTI) CMRR and PSRR vs Frequency (Referred to Input) Common-Mode Rejection Ratio vs Temperature 0.1-Hz to 10-Hz Noise Common-Mode Rejection Ratio vs Temperature 0.1-Hz to 10-Hz Noise Input Voltage Noise Density vs Frequency Input Voltage Noise Density vs Frequency THD+N Ratio vs Frequency (80-kHz AP Bandwidth) THD+N Ratio vs Output Amplitude THD+N Ratio vs Frequency THD+N Ratio vs Output Amplitude Quiescent Current vs Temperature Quiescent Current vs Temperature Quiescent Current vs Supply Voltage Quiescent Current vs Supply Voltage Gain and Phase vs Frequency Gain and Phase vs Frequency Closed-Loop Gain vs Frequency Closed-Loop Gain vs Frequency Open-Loop Gain vs Temperature Open-Loop Gain vs Temperature Open-Loop Output Impedance vs Frequency Open-Loop Output Impedance vs Frequency Small-Signal Overshoot vs Capacitive Load (G = 1) Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Small-Signal Overshoot vs Capacitive Load (G = –1) Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) No Phase Reversal No Phase Reversal Positive Overload Recovery Positive Overload Recovery Negative Overload Recovery Negative Overload Recovery Large-Signal Positive and Negative Settling Time Small-Signal Step Response (G = 1) Small-Signal Step Response (100 mV) Small-Signal Step Response (G = –1) Small-Signal Step Response (100 mV) Large-Signal Step Response (G = 1) Large-Signal Step Response Large-Signal Step Response (G = –1) Large-Signal Step Response Short-Circuit Current vs Temperature Short Circuit Current vs Temperature Maximum Output Voltage vs Frequency Channel Separation vs Frequency 8 Large-Signal Positive Settling Time (10-V Step), Large-Signal Negative Settling Time (10-V Step) Maximum Output Voltage vs Frequency Channel Separation vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 6.8 Typical Characteristics (continued) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 Population Population at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) Offset Voltage (mV) Offset Voltage Drift (mV/°C) Figure 6-1. Offset Voltage Production Distribution 160 18 Typical Units Shown 120 80 60 40 20 0 -20 -40 -60 -80 -100 -120 Input Offset Voltage (mV) VOS (mV) 120 100 Figure 6-2. Offset Voltage Drift Distribution 80 40 0 -40 -80 -120 -160 -18 -12 0 -6 6 12 -40 -25 -10 18 5 20 35 50 65 80 95 110 125 Temperature (?C) VCM (V) Figure 6-3. Offset Voltage vs Common-Mode Voltage Figure 6-4. Input Offset Voltage vs Temperature (144 Amplifiers) 18.0 10 17.5 +14.5V Output Voltage (V) -0.1V IB (pA) 17.0 Specified Common-Mode Voltage Range 8 6 4 +IB 2 16.5 16.0 -40°C +25°C +85°C +125°C -16.0 -16.5 -17.0 -17.5 0 -IB -18 -15 -12 -9 -18.0 -6 -3 0 3 6 9 12 15 18 0 10 20 30 40 50 60 70 Output Current (mA) VCM (V) Figure 6-5. IB vs Common-Mode Voltage Figure 6-6. Output Voltage Swing vs Output Current (Maximum Supply) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 9 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) Common-Mode Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 180 0.12 CMRR 160 0.10 140 CMRR (mV/V) 120 100 -PSRR 80 +PSRR 60 40 0.08 0.06 0.04 0.02 20 0 0 1 10 100 1k 10k 100k 1M 10M -75 100M -50 0 -25 25 75 50 100 125 150 Temperature (°C) Frequency (Hz) Figure 6-7. CMRR and PSRR vs Frequency (Referred to Input) Figure 6-8. Common-Mode Rejection Ratio vs Temperature 100nV/div Voltage Noise Density (nV/ÖHz) 100 10 1 Time (1s/div) 0.1 1 10 100 1k 10k 100k Frequency (Hz) Figure 6-9. 0.1-Hz to 10-Hz Noise 0.0001 -120 G = +1 0.00001 -140 10 100 1k 10k 20k Total Harmonic Distortion + Noise (%) Total Harmonic Distortion + Noise (%) G = -1 0.01 BW = 80kHz 1kHz Signal RL = 2kW -80 0.001 -100 0.0001 -120 NOTE: Increase at low signal levels is a result of increased % contribution of noise. 0.00001 0.1 Frequency (Hz) 1 10 -140 100 Output Amplitude (VRMS) Figure 6-11. THD+N Ratio vs Frequency 10 G = -1 G = +1 Total Harmonic Distortion + Noise (dB) -100 VOUT = 3VRMS BW = 80kHz RL = 2kW Total Harmonic Distortion + Noise (dB) 0.001 Figure 6-10. Input Voltage Noise Density vs Frequency Figure 6-12. THD+N Ratio vs Output Amplitude Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 2.5 2.00 OPA140 1.75 1.50 1.25 1.5 IQ (mA) IQ (mA) 2.0 1.0 1.00 0.75 0.50 0.5 0.25 0 Specified Supply-Voltage Range 0 -75 -50 -25 0 25 75 50 100 125 150 4 0 8 12 Temperature (°C) Figure 6-13. Quiescent Current vs Temperature 140 20 24 28 32 36 Figure 6-14. Quiescent Current vs Supply Voltage 180 40 120 CL = 30pF 30 G = +10 Gain 135 90 60 40 Phase Phase (degrees) 80 20 Gain (dB) 100 Gain (dB) 16 Supply Voltage (V) 45 20 10 G = +1 0 -10 -20 0 G = -1 -30 -20 10 100 1k 10k 100k 1M 10M 0 100M -40 100k Frequency (Hz) 1M 10M 100M Frequency (Hz) Figure 6-15. Gain and Phase vs Frequency Figure 6-16. Closed-Loop Gain vs Frequency 1k 0 10kW Load -0.2 100 -0.6 ZO (W) AOL (mV/V) -0.4 2kW Load -0.8 10 -1.0 -1.2 -1.4 1 -75 -50 -25 0 25 75 50 100 125 150 10 100 Temperature (°C) Figure 6-17. Open-Loop Gain vs Temperature 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 6-18. Open-Loop Output Impedance vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 11 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 40 50 ROUT = 0W G = +1 +15V 35 45 ROUT OPA140 25 ROUT = 0W 40 RL -15V ROUT = 24W CL Overshoot (%) Overshoot (%) 30 ROUT = 24W 20 15 35 30 25 20 ROUT = 51W 15 10 RI = 2kW RF = 2kW G = -1 +15V 10 ROUT = 51W 5 ROUT OPA140 CL 5 0 -15V 0 0 200 400 600 800 1000 1200 1400 1600 0 500 1000 Capacitive Load (pF) 1500 2000 Capacitive Load (pF) Figure 6-19. Small-Signal Overshoot vs Capacitive Load (100mV Output Step) Figure 6-20. Small-Signal Overshoot vs Capacitive Load (100mV Output Step) 35 Output Voltage (VPP) 5V/div Output +18V OPA140 Output -18V 37VPP Sine Wave (±18.5V) Maximum Output Voltage Range Without Slew-Rate Induced Distortion VS = ±15 V 30 25 20 15 VS = ±5 V 10 VS = ±2.25 V 5 0 Time (0.4ms/div) 10k 100k 1M 10M Frequency (Hz) Figure 6-22. Maximum Output Voltage vs Frequency Figure 6-21. No Phase Reversal VOUT 5V/div 5V/div VIN 20kW 20kW 2kW VIN 2kW VOUT OPA140 OPA140 VIN G = -10 G = -10 Time (0.4ms/div) Time (0.4ms/div) Figure 6-23. Positive Overload Recovery 12 VOUT VIN VOUT Figure 6-24. Negative Overload Recovery Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 6.8 Typical Characteristics (continued) 1000 1000 800 800 600 400 16-bit Settling 200 0 -200 (±1/2LSB = ±0.00075%) -400 -600 Delta from Final Value (mV) Delta from Final Value (mV) at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 600 400 0 -200 -600 -800 -1000 -1000 0.5 1 1.5 2 2.5 3 3.5 (±1/2LSB = ±0.00075%) -400 -800 0 16-bit Settling 200 4 0 0.5 1 1.5 2 2.5 Figure 6-25. Large-Signal Positive Settling Time (10-V Step) RL 4 CL = 100pF 10mV/div 10mV/div G = +1 OPA140 -15V 3.5 Figure 6-26. Large-Signal Negative Settling Time (10-V Step) CL = 100pF +15V 3 Time (ms) Time (ms) RI = 2kW RF = 2kW +15V OPA140 CL CL -15V G = -1 Time (100ns/div) Time (100ns/div) Figure 6-28. Small-Signal Step Response (100 mV) 2 V/div 2 V/div Figure 6-27. Small-Signal Step Response (100 mV) Time (400 ns/div) Time (400 ns/div) Figure 6-29. Large-Signal Step Response Figure 6-30. Large-Signal Step Response Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 13 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 60 -90 ISC, Source ISC, Sink Channel Separation (dB) 50 ISC (mA) 40 30 20 10 -100 VOUT = 3VRMS G = +1 -110 RL = 2kW -120 -130 -140 Short-circuiting causes thermal shutdown; see Applications Information section. RL = 5kW -150 0 -75 -50 -25 0 25 75 50 100 125 150 10 100 Figure 6-31. Short Circuit Current vs Temperature 14 1k 10k 100k Frequency (Hz) Temperature (°C) Figure 6-32. Channel Separation vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 7 Detailed Description 7.1 Overview The OPAx140 family of operational amplifiers is a series of low-power JFET input amplifiers that feature superior drift performance and low input bias current. The rail-to-rail output swing and input range that includes V– allow designers to use the low-noise characteristics of JFET amplifiers while also interfacing to modern, single-supply, precision analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). The OPAx140 series achieves 11-MHz unity-gain bandwidth and 20-V/μs slew rate, and consumes only 1.8 mA (typical) of quiescent current. These devices operate on a single 4.5-V to 36-V supply or dual ±2.25-V to ±18-V supplies. Section 7.2 shows the simplified diagram of the OPAx140. 7.2 Functional Block Diagram V+ Pre-Output Driver IN– OUT IN+ V– 7.3 Feature Description 7.3.1 Operating Voltage The OPA140, OPA2140, and OPA4140 series of op amps can be used with single or dual supplies from an operating range of VS = 4.5 V (±2.25 V) and up to VS = 36 V (±18 V). These devices do not require symmetrical supplies; they only require a minimum supply voltage of 4.5 V (±2.25 V). For VS less than ±3.5 V, the common-mode input range does not include midsupply. Supply voltages higher than 40 V can permanently damage the device; see Section 6.1. Key parameters are specified over the operating temperature range, TA = –40°C to 125°C. Key parameters that vary over the supply voltage or temperature range are shown in Section 6.8 of this data sheet. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 15 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 7.3.2 Capacitive Load and Stability The dynamic characteristics of the OPAx140 have been optimized for commonly encountered gains, loads, and operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (ROUT equal to 50 Ω, for example) in series with the output. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) and Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) illustrate graphs of Small-Signal Overshoot vs Capacitive Load for several values of ROUT. Also, see the Feedback Plots Define Op Amp AC Performance Application Bulletin, available for download from www.ti.com, for details of analysis techniques and application circuits. 7.3.3 Output Current Limit The output current of the OPAx140 series is limited by internal circuitry to 36 mA/–30 mA (sourcing/sinking), to protect the device if the output is accidentally shorted. This short circuit current depends on temperature, as shown in Short Circuit Current vs Temperature. 7.3.4 Noise Performance Figure 7-1 shows the total circuit noise for varying source impedances with the operational amplifier in a unity-gain configuration (with no feedback resistor network and therefore no additional noise contributions). The OPA140 and OPA211 are shown with total circuit noise calculated. The op amp itself contributes both a voltage noise component and a current noise component. The voltage noise is commonly modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying component of the input bias current and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest noise op amp for a given application depends on the source impedance. For low source impedance, current noise is negligible, and voltage noise generally dominates. The OPA140, OPA2140, and OPA4140 family has both low voltage noise and extremely low current noise because of the FET input of the op amp. As a result, the current noise contribution of the OPAx140 series is negligible for any practical source impedance, which makes it the better choice for applications with high source impedance. The equation in Figure 7-1 shows the calculation of the total circuit noise, with these parameters: • en = voltage noise • In = current noise • RS = source impedance • k = Boltzmann's constant = 1.38 × 10–23 J/K • T = temperature in degrees Kelvin (K) For more details on calculating noise, see Section 7.3.5. Votlage Noise Spectral Density, EO 10k EO 1k OPA211 RS 100 OPA140 Resistor Noise 10 2 2 2 EO = en + (in RS) + 4kTRS 1 100 1k 10k 100k 1M Source Resistance, RS (W) Figure 7-1. Noise Performance of the OPA140 and OPA211 in Unity-Gain Buffer Configuration 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 7.3.5 Basic Noise Calculations Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the circuit is the root-sum-square combination of all noise components. The resistive portion of the source impedance produces thermal noise proportional to the square root of the resistance. This function is plotted in Figure 7-1. The source impedance is usually fixed; consequently, select the op amp and the feedback resistors to minimize the respective contributions to the total noise. Noise Calculation in Gain Configurations illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the op amp reacts with the feedback resistors to create additional noise components. However, the extremely low current noise of the OPAx140 means that its current noise contribution can be neglected. The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance feedback resistors load the output of the amplifier. The equations for total noise are shown for both configurations. A) Noise in Noninverting Gain Configuration Noise at the output: R2 2 2 O E R1 R2 = 1+ R1 2 R2 2 n e + 2 2 R1 2 e1 + e2 + 1 + R2 R1 es2 EO RS Where eS = 4kTRS = thermal noise of RS e1 = 4kTR1 = thermal noise of R1 e2 = 4kTR2 = thermal noise of R2 VS B) Noise in Inverting Gain Configuration Noise at the output: R2 2 2 EO R1 = 1+ R2 R1 + RS 2 R2 2 en + R 1 + RS 2 2 1 2 e + e2 + R2 R 1 + RS e s2 EO RS VS Where eS = 4kTRS = thermal noise of RS e1 = 4kTR1 = thermal noise of R1 e2 = 4kTR2 = thermal noise of R2 For the OPAx140 series of operational amplifiers at 1 kHz, en = 5.1 nV/√ Hz. Figure 7-2. Noise Calculation in Gain Configurations 7.3.6 Phase-Reversal Protection The OPA140, OPA2140, and OPA4140 family has internal phase-reversal protection. Many FET- and bipolarinput op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input circuitry of the OPA140, OPA2140, and OPA4140 prevents phase reversal with excessive common-mode voltage; instead, the output limits into the appropriate rail (see No Phase Reversal). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 17 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 7.3.7 Thermal Protection The OPAx140 series of op amps are capable of driving 2-kΩ loads with power-supply voltages of up to ±18 V over the specified temperature range. In a single-supply configuration, where the load is connected to the negative supply voltage, the minimum load resistance is 2.8 kΩ at a supply voltage of 36 V. For lower supply voltages (either single-supply or symmetrical supplies), a lower load resistance may be used, as long as the output current does not exceed 13 mA; otherwise, the device short circuit current protection circuit may activate. Internal power dissipation increases when operating at high supply voltages. Copper leadframe construction used in the OPA140, OPA2140, and OPA4140 series devices improves heat dissipation compared to conventional materials. Printed-circuit-board (PCB) layout can also help reduce a possible increase in junction temperature. Wide copper traces help dissipate the heat by acting as an additional heatsink. Temperature rise can be further minimized by soldering the devices directly to the PCB rather than using a socket. Although the output current is limited by internal protection circuitry, accidental shorting of one or more output channels of a device can result in excessive heating. For instance, when an output is shorted to mid-supply, the typical short-circuit current of 36 mA leads to an internal power dissipation of over 600 mW at a supply of ±18 V. In the case of a dual OPA2140 in an 8-pin VSSOP package (thermal resistance θJA = 180°C/W), such power dissipation would lead the die temperature to be 220°C above ambient temperature, when both channels are shorted. This temperature increase significantly decreases the operating life of the device. To prevent excessive heating, the OPAx140 series has an internal thermal shutdown circuit that shuts down the device if the die temperature exceeds approximately 180°C. When this thermal shutdown circuit activates, a built-in hysteresis of 15°C makes sure that the die temperature must drop to approximately 165°C before the device switches on again. Additional consideration should be given to the combination of maximum operating voltage, maximum operating temperature, load, and package type. Figure 7-3 and Figure 7-4 show several practical considerations when evaluating the OPA2140 (dual version) and the OPA4140 (quad version). 20 20 18 18 Maximum Supply Voltage (V) Maximum Supply Voltage (V) As an example, the OPA4140 has a maximum total quiescent current of 10.8 mA (2.7 mA/channel) over temperature. The 14-pin TSSOP package has a typical thermal resistance of 135°C/W. This parameter means that because the junction temperature should not exceed 150°C to provide reliable operation, either the supply voltage must be reduced, or the ambient temperature should remain low enough so that the junction temperature does not exceed 150°C. This condition is illustrated in Figure 7-3 for various package types. Moreover, resistive loading of the output causes additional power dissipation and thus self-heating, which also must be considered when establishing the maximum supply voltage or operating temperature. To this end, Figure 7-4 shows the maximum supply voltage versus temperature for a worst-case dc load resistance of 2 kΩ. 16 14 12 10 8 6 TSSOP Quad SOIC Quad MSOP Dual SOIC Dual 4 2 0 80 90 100 110 16 14 12 10 8 6 TSSOP Quad SOIC Quad MSOP Dual SOIC Dual 4 2 0 120 130 140 150 160 80 90 100 Ambient Temperature (°C) Figure 7-3. Maximum Supply Voltage vs Temperature (OPA2140 and OPA4140), Quiescent Condition 18 110 120 130 140 150 160 Ambient Temperature (°C) Figure 7-4. Maximum Supply Voltage vs Temperature (OPA2140 and OPA4140), Maximum DC Load Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 7.3.8 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application shows an illustration of the ESD circuits contained in the OPAx140 series (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where they meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. (2) TVS RF +V +VS OPA140 RI ESD CurrentSteering Diodes -In (3) RS +In Op Amp Core Edge-Triggered ESD Absorption Circuit ID VIN Out RL (1) -V -VS (2) TVS (1) VIN = +VS + 500 mV. (2) TVS: +VS(max) > VTVSBR (Min) > +VS (3) Suggested value approximately 1 kΩ. Figure 7-5. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat. When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or more of the steering diodes. Depending on the path that the current takes, the absorption device may activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx140 but below the device breakdown voltage level. Once this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level. When the operational amplifier connects into a circuit such as the one Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application shows, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 19 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption device. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA. If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings. Another common question involves what happens to the amplifier if an input signal is applied to the input while the power supplies +VS or –VS are at 0 V. Again, it depends on the supply characteristic while at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be supplied by the input source through the current steering diodes. This state is not a normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path. If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be added to the supply pins as shown in Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application. The Zener voltage must be selected such that the diode does not turn on during normal operation. However, its Zener voltage should be low enough so that the Zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 7.3.9 EMI Rejection The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this section provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for the following three reasons: • Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the supply or output pins. • The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching EMIRR performance • EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input terminal with no complex interactions from other components or connecting PCB traces. Figure 7-6 120 EMIRR IN+ (db) PRF = -10 dbm VS = r12 V 100 VCM = 0 V 80 60 40 20 0 10 100 1k Frequency (MHz) 10k Figure 7-6. OPA2140 EMIRR The EMIRR IN+ of the OPA2140 is plotted versus frequency as shown in .If available, any dual and quad op amp device versions have nearly similar EMIRR IN+ performance. The OPA2140 unity-gain bandwidth is 11 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the op amp bandwidth. For more information, see the EMI Rejection Ratio of Operational Amplifiers Application Report, available for download from www.ti.com. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 21 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 Table 7-1 lists the EMIRR IN+ values for the OPA2140 at particular frequencies commonly encountered in realworld applications. Applications listed in Table 7-1 may be centered on or operated near the particular frequency shown. This information may be of special interest to designers working with these types of applications, or working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific, and medical (ISM) radio band. Table 7-1. OPA2140 EMIRR IN+ for Frequencies of Interest FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 53.1 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 72.2 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 80.7 dB 2.4 GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 86.8 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 91.7 dB 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 96.6 dB 5 GHz 7.3.10 EMIRR +IN Test Configuration Figure 7-7 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the op amp noninverting input terminal using a transmission line. The op amp is configured in a unity gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch at the op amp input causes a voltage reflection; however, this effect is characterized and accounted for when determining the EMIRR IN+. The resulting DC offset voltage is sampled and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that may interfere with multimeter accuracy. Ambient temperature: 25Û& +VS ± 50 Low-Pass Filter + RF source DC Bias: 0 V Modulation: None (CW) Frequency Sweep: 201 pt. Log -VS Not shown: 0.1 µF and 10 µF supply decoupling Sample / Averaging Digital Multimeter Figure 7-7. EMIRR +IN Test Configuration 7.4 Device Functional Modes The OPAx140 has a single functional mode and is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power supply voltage for the OPAx140 is 36 V (±18 V). 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The OPA140, OPA2140, and OPA4140 are unity-gain stable, operational amplifiers with very low noise, input bias current, and input offset voltage. Applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1-μF capacitors are adequate. Designers can easily use the rail-to-rail output swing and input range that includes V– to take advantage of the low-noise characteristics of JFET amplifiers while also interfacing to modern, single-supply, precision data converters. 8.2 Typical Application R4 2.94 k C5 1 nF R1 590 R3 499 Input C2 39 nF ± Output + OPA140 Copyright © 2016, Texas Instruments Incorporated Figure 8-1. 25-kHz Low-pass Filter 8.2.1 Design Requirements Lowpass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing. The OPAx140 are an excellent choice to construct high-speed, high-precision active filters. Figure 8-1 shows a second-order, low-pass filter commonly encountered in signal processing applications. Use the following parameters for this design example: • Gain = 5 V/V (inverting gain) • Low-pass cutoff frequency = 25 kHz • Second-order Chebyshev filter response with 3-dB gain peaking in the passband 8.2.2 Detailed Design Procedure The infinite-gain multiple-feedback circuit for a low-pass network function is shown in. Use Equation 1 to calculate the voltage transfer function. Output s Input 1 R1R3C2C5 s 2 s C2 1 R1 1 R3 1 R4 1 R3R4C2C5 (1) This circuit produces a signal inversion. For this circuit, the gain at DC and the lowpass cutoff frequency are calculated by Equation 2: Gain fC 1 2S R4 R1 1 R3R 4 C2C5 (2) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 23 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 Software tools are readily available to simplify filter design. The WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH® Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web based tool from the WEBENCH Design Center, the WEBENCH Filter Designer allows you to design, optimize, and simulate complete multistage active filter solutions within minutes. 8.2.3 Application Curve 20 Gain (db) 0 -20 -40 -60 100 1k 10k Frequency (Hz) 100k 1M Figure 8-2. OPAx140 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter 9 Power Supply Recommendations The OPAx140 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in Section 6.8. CAUTION Supply voltages larger than 40 V can permanently damage the device; see Section 6.1. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 10. 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: • • • • • • • • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information, see Circuit Board Layout Techniques. To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. Place the external components as close to the device as possible. As illustrated in Figure 10-1, keeping RF and RG close to the inverting input minimizes parasitic capacitance. Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. For best performance, TI recommends cleaning the PCB following board assembly. Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. 10.2 Layout Example Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF NC NC GND ±IN V+ VIN +IN OUTPUT V± NC Use a low-ESR, ceramic bypass capacitor RG GND VS± GND VOUT Ground (GND) plane on another layer Use low-ESR, ceramic bypass capacitor Figure 10-1. Operational Amplifier Board Layout for Noninverting Configuration Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 25 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ SImulation Software (Free Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ simulation software is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI simulation softwate provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. Note These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 11.1.1.2 WEBENCH Filter Designer Tool WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. 11.1.1.3 TI Precision Designs TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • Texas Instruments, Circuit Board Layout Techniques • Texas Instruments, Op Amps for Everyone design reference • Texas Instruments, OPA140, OPA2140, OPA4140 EMI Immunity Performance technical brief • Texas Instruments, Compensate Transimpedance Amplifiers Intuitively application report • Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis • Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis • Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters • Texas Instruments, Op Amp Performance Analysis application bulletin • Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin • Texas Instruments, Tuning in Amplifiers application bulletin • Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application report • Texas Instruments, Feedback Plots Define Op Amp AC Performance application bulletin • Texas Instruments, EMI Rejection Ratio of Operational Amplifiers Application Report application report 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 OPA140, OPA2140, OPA4140 www.ti.com SBOS498E – JULY 2010 – REVISED JULY 2021 11.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.5 Trademarks TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc. TINA-TI™ is a trademark of Texas Instruments, Inc and DesignSoft, Inc. TI E2E™ is a trademark of Texas Instruments. Bluetooth® is a registered trademark of Bluetooth SIG, Inc. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA140 OPA2140 OPA4140 27 PACKAGE OPTION ADDENDUM www.ti.com 12-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) OPA140AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA140 Samples OPA140AIDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O140 Samples OPA140AIDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O140 Samples OPA140AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 (140, O140) Samples OPA140AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 140 Samples OPA140AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA140 Samples OPA2140AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O2140A Samples OPA2140AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 2140 Samples OPA2140AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 2140 Samples OPA2140AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O2140A Samples OPA4140AID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 O4140A Samples OPA4140AIDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 O4140A Samples OPA4140AIPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O4140A Samples OPA4140AIPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O4140A Samples POPA2140AIDRGR ACTIVE SON DRG 8 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-Sep-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
OPA4140AIPW 价格&库存

很抱歉,暂时无法提供与“OPA4140AIPW”相匹配的价格&库存,您可以联系我们找货

免费人工找货
OPA4140AIPW
    •  国内价格
    • 1000+53.90000

    库存:55817