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OPA4209AIPW

OPA4209AIPW

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP14_5X4.4MM

  • 描述:

    General Purpose Amplifier 4 Circuit Rail-to-Rail 14-TSSOP

  • 数据手册
  • 价格&库存
OPA4209AIPW 数据手册
Sample & Buy Product Folder Technical Documents Support & Community Tools & Software Reference Design OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 OPAx209 2.2-nV/√Hz, Low-Power, 36-V Operational Amplifier 1 Features 3 Description • • • • • • • The OPA209 series of precision operational amplifiers achieve very low voltage noise density (2.2 nV/√Hz) with a supply current of only 2.5 mA (maximum). This series also offers rail-to-rail output swing, which helps to maximize dynamic range. 1 • • • Low Voltage Noise: 2.2 nV/√Hz at 1 kHz 0.1-Hz to 10-Hz Noise: 130 nVPP Low Quiescent Current: 2.5 mA/Ch (Maximum) Low Offset Voltage: 150 µV (Maximum) Gain Bandwidth Product: 18 MHz Slew Rate: 6.4 V/µs Wide Supply Range: ±2.25 V to ±18 V, 4.5 V to 36 V Rail-to-Rail Output Short-Circuit Current: ±65 mA Available in 5-Pin SOT-23, 8-Pin MSOP, 8-Pin SOIC, and 14-Pin TSSOP Packages 2 Applications • • • • • • • • • • • PLL Loop Filters Low-Noise, Low-Power Signal Processing Low-Noise Instrumentation Amplifiers High-Performance ADC Drivers High-Performance DAC Output Amplifiers Active Filters Ultrasound Amplifiers Professional Audio Preamplifiers Low-Noise Frequency Synthesizers Infrared Detector Amplifiers Hydrophone Amplifiers In precision data acquisition applications, the OPA209 provides fast settling time to 16-bit accuracy, even for 10-V output swings. This excellent ac performance, combined with only 150 µV (maximum) of offset and low drift over temperature, makes the OPA209 very suitable for fast, high-precision applications. The OPA209 is specified over a wide dual powersupply range of ±2.25 V to ±18 V, or single-supply operation from 4.5 V to 36 V. The OPA209 is available in the 5-pin SOT-23, 8-pin VSSOP, and the standard 8-pin SOIC packages. The dual OPA2209 comes in both 8-pin VSSOP and 8-pin SOIC packages. The quad OPA4209 is available in the 14-pin TSSOP package. The OPA209 series is specified from –40°C to 125°C. Device Information(1) PART NUMBER OPA209 OPA2209 OPA4209 PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm × 1.60 mm VSSOP (8) 3.00 mm × 3.00 mm SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm SOIC (8) 4.90 mm × 3.91 mm TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 50nV/div 0.1-Hz to 10-Hz Noise Time (1s/div) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 5 5 5 5 6 6 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information: OPA209 .................................. Thermal Information: OPA2209 ................................ Thermal Information: OPA4209 ................................ Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 13 7.1 Overview ................................................................. 13 7.2 Functional Block Diagram ....................................... 13 7.3 Feature Description................................................. 13 7.4 Device Functional Modes ....................................... 17 8 Application and Implementation ........................ 18 8.1 Application Information .......................................... 18 8.2 Typical Application ................................................. 18 9 Power Supply Recommendations...................... 19 10 Layout................................................................... 19 10.1 Layout Guidelines ................................................ 19 10.2 Layout Example .................................................... 20 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 22 22 22 22 22 22 23 12 Mechanical, Packaging, and Orderable Information ........................................................... 23 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (October 2013) to Revision D Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1 • Moved specified voltage, specified temperature, and operating temperature from Electrical Characteristics to Recommended Operating Conditions .................................................................................................................................... 5 • Updated values in the Thermal Information tables to align with JEDEC standards............................................................... 5 Changes from Revision B (August 2010) to Revision C Page • Deleted device graphic ........................................................................................................................................................... 1 • Changed y-axis units label in Figure 2 ................................................................................................................................... 8 2 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 5 Pin Configuration and Functions OPA209: DBV Package 5-Pin SOT-23 Top View OUT 1 V- 2 5 OPA209: D or DGK Packages 8-Pin SOIC or VSSOP Top View V+ NC (1) -IN 1 2 8 NC 7 V+ (1) OPA209 +IN 3 4 -IN (1) +IN 3 6 OUT V- 4 5 NC (1) NC = no internal connection Pin Functions: OPA209 PIN NAME I/O DESCRIPTION SOT-23 SOIC, VSSOP –IN 4 2 I Inverting input +IN 3 3 I Noninverting input NC — 1, 5, 8 — No internal connection OUT 1 6 O Output V– 2 4 — Negative (lowest) power supply V+ 5 7 — Positive (highest) power supply OPA2209: D or DGK Packages 8-Pin SOIC or VSSOP Top View OUT A -IN A 1 2 +IN A 3 V- 4 A B 8 V+ 7 OUT B 6 -IN B 5 +IN B Pin Functions: OPA2209 PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Noninverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Noninverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V– 4 — Negative (lowest) power supply V+ 8 — Positive (highest) power supply Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 3 OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com OPA4209: PW Package 14-Pin TSSOP Top View 14 OUT D OUT A 1 -IN A 2 +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 -IN B 6 OUT B 7 A D 13 -IN D 10 +IN C B C 9 -IN C 8 OUT C Pin Functions: OPA4209 PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Noninverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Noninverting input, channel B –IN C 9 I Inverting input, channel C +IN C 10 I Noninverting input, channel C –IN D 13 I Inverting input, channel D +IN D 12 I Noninverting input, channel D OUT A 1 O Output, channel A OUT B 7 O Output, channel B OUT C 8 O Output, channel C OUT D 14 O Output, channel D V– 11 — Negative (lowest) power supply V+ 4 — Positive (highest) power supply 4 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Supply voltage, VS = (V+) – (V–) Voltage Signal input pins (2) Signal input pins (2) Current (V+) + 0.5 V –10 10 mA 150 °C 200 °C 150 °C –55 Junction, TJ Storage, Tstg (2) (3) V Continuous Operating, TA (1) UNIT 40 (V–) – 0.5 Output short circuit (3) Temperature MAX –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For input voltages beyond the power-supply rails, voltage or current must be limited. Short-circuit to ground, one amplifier per package. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±3000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VS MIN MAX UNIT ±2.25 ±18 V Specified temperature –40 125 °C Operating temperature –55 150 °C Specified voltage TA 6.4 Thermal Information: OPA209 OPA209 THERMAL METRIC (1) DBV (SOT-23) D (SOIC) DGK (VSSOP) 5 PINS 8 PINS 8 PINS UNIT 204.9 135.5 142.6 °C/W RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 200 73.7 46.9 °C/W RθJB Junction-to-board thermal resistance 113.1 61.9 63.5 °C/W ψJT Junction-to-top characterization parameter 38.2 19.7 5.3 °C/W ψJB Junction-to-board characterization parameter 104.9 54.8 62.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 5 OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 6.5 Thermal Information: OPA2209 OPA2209 THERMAL METRIC (1) D (SOIC) DGK (VSSOP) 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 134.3 132.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 72.1 38.5 °C/W RθJB Junction-to-board thermal resistance 60.7 52.1 °C/W ψJT Junction-to-top characterization parameter 18.2 2.4 °C/W ψJB Junction-to-board characterization parameter 53.8 52.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.6 Thermal Information: OPA4209 OPA4209 THERMAL METRIC (1) PW (TSSOP) UNIT 14 PINS RθJA Junction-to-ambient thermal resistance 112.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26.1 °C/W RθJB Junction-to-board thermal resistance 61 °C/W ψJT Junction-to-top characterization parameter 0.7 °C/W ψJB Junction-to-board characterization parameter 59.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.7 Electrical Characteristics at VS = ±2.25 V to ±18 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX ±35 ±150 1 3 0.05 0.5 UNIT OFFSET VOLTAGE VOS Input offset voltage VS = ±15 V, VCM = 0 V dVOS/dT Input offset voltage drift TA = –40°C to 125°C PSRR vs power supply VS = ±2.25 V to ±18 V Channel separation DC (dual and quad versions) TA = 25°C TA = –40°C to 125°C 1 1 µV µV/°C µV/V µV/V INPUT BIAS CURRENT TA = 25°C IB Input bias current VCM = 0 V ±1 ±8 TA = –40°C to 125°C ±15 TA = 25°C IOS Input offset current VCM = 0 V ±4.5 TA = –40°C to 85°C ±0.7 nA ±4.5 TA = –40°C to 85°C ±8 TA = –40°C to 125°C ±15 nA NOISE en Input voltage noise Noise density In Input current noise density f = 0.1 Hz to 10 Hz 0.13 f = 10 Hz 3.3 f = 100 Hz 2.25 f = 1 kHz 2.2 f = 1 kHz 500 µVPP nV/√Hz fA/√Hz INPUT VOLTAGE RANGE VCM Common-mode voltage range CMRR Common-mode rejection ratio 6 (V–) + 1.5 (V–) + 1.5 V < VCM < (V+) – 1.5 V, TA = –40°C to 125°C Submit Documentation Feedback 120 (V+) – 1.5 130 V dB Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 Electrical Characteristics (continued) at VS = ±2.25 V to ±18 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT IMPEDANCE Differential 200 || 4 kΩ || pF Common-mode 109 || 2 Ω || pF OPEN-LOOP GAIN AOL (V–) + 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ TA = 25°C 126 TA = –40°C to 125°C 120 (V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 600 Ω (1) TA = 25°C 114 TA = –40°C to 125°C 110 Open-loop voltage gain 132 dB 120 FREQUENCY RESPONSE GBW Gain bandwidth product 18 MHz SR Slew rate 6.4 V/µs Φm Phase margin RL = 10 kΩ, CL = 25 pF 80 ° 0.1%, G = –1, 10-V step, CL = 100 pF 2.1 0.0015% (16-bit), G = –1, 10-V step, CL = 100 pF 2.6 Overload recovery time G = –1 130 dB (V–) + 0.2 (V+) – 0.2 RL = 600 Ω, AOL > 114 dB (V–) + 0.6 (V+) – 0.6 RL = 10 kΩ, AOL > 120 dB, TA = –40°C to 125°C (V–) + 0.2 (V+) – 0.2 ISC Short-circuit current CLOAD Capacitive load drive (stable operation) VS = ±18 V ±65 See Typical Characteristics ZO Open-loop output impedance See Typical Characteristics V mA POWER SUPPLY IQ (1) Quiescent current (per amplifier) IO = 0 A TA = 25°C TA = –40°C to 125°C 2.2 2.5 3.25 mA See Absolute Maximum Ratings for additional information. Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 7 OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 6.8 Typical Characteristics at TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 10 Input Current Noise Density (pA/ÖHz) Input Voltage Noise Density (nV/ÖHz) 100 10 1 0.1 1 0.1 1 10 100 1k 10k 100k 0.1 10 100 1k 10k Frequency (Hz) Figure 1. Input Voltage Noise Density vs Frequency Figure 2. Input Current Noise Density vs Frequency 0.001 1 VS = ±15V RL = 600W Total Harmonic Distortion+Noise (%) Total Harmonic Distortion+Noise (%) 1 Frequency (Hz) G = +11 VOUT = 3VRMS 0.0001 G = +1 VOUT = 3VRMS 0.00001 10 100 1k 10k 20k 0.1 0.01 0.001 G = +11 0.0001 G = +1 0.00001 0.01 0.1 Frequency (Hz) 1 10 100 Output Voltage Amplitude (VRMS) Figure 3. Total Harmonic Distortion + Noise Ratio vs Frequency Figure 4. Total Harmonic Distortion + Noise Ratio vs Amplitude 160 140 50nV/div PSRR (dB) 120 100 -PSRR 80 +PSRR 60 40 20 0 0.1 1 10 Time (1s/div) Submit Documentation Feedback 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 5. 0.1-Hz to 10-Hz Noise 8 100 Figure 6. Power-Supply Rejection Ratio vs Frequency (Referred to Input) Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 Typical Characteristics (continued) 150 140 130 120 110 100 90 80 70 60 50 40 30 20 100000 Open-Loop Output Impedance (ZO) 1k 10k 100k 1M 10M 10000 1000 100 10 1 0.1 100M 1 10 Frequency (Hz) 140 10k 100k 1M 10M 100M Figure 8. Open-Loop Output Impedance vs Frequency 5 180 4 80 Phase 60 90 40 20 45 Phase (°) 135 Open-Loop Gain (mV/V) Gain 100 0 3 RL = 10kW VS = ±18V 2 1 0 -1 -2 -3 -4 -20 10 100 1k 10k 100k 1M 10M 0 100M -5 -50 -25 0 25 50 75 100 125 150 Temperature (°C) Frequency (Hz) Figure 10. Open-Loop Gain vs Temperature 2.50 2.25 2.00 Drift (mV/°C) Offset Voltage (mV) Figure 11. Offset Voltage Production Distribution 1.75 0.75 0.50 0.25 0 -75.00 -67.50 -60.00 -52.50 -45.00 -37.50 -30.00 -22.50 -15.00 -7.50 0 7.50 15.00 22.50 30.00 37.50 45.00 52.50 60.00 67.50 75.00 Population Population Figure 9. Open-Loop Gain and Phase vs Frequency 1.50 1 1.25 Gain (dB) 1k Frequency (Hz) Figure 7. Common-Mode Rejection Ratio vs Frequency 120 100 1.00 CMRR (dB) at TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) Figure 12. Offset Voltage Drift Production Distribution Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 9 OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 5 100 4 80 IOS 2 1 0 IB+ -1 IB- -2 60 Input Offset Voltage (mV) -3 40 20 0 -20 -40 -60 -4 -80 -5 -50 (V+)-1.0.V (V+)-0.5V 150 (V+)-1.5V 125 (V+)-2.0V 100 (V+)-2.5V 75 (V-)+2.5V 50 Temperature (°C) (V-)+2.0V 25 (V-)+0.5V 0 -25 (V-)+1.5V -100 (V-)+1.0V IB and IOS (nA) 3 VS = 36V 32 36 Input Common-Mode Voltage (V) Figure 13. Input Bias and Input Offset Currents vs Temperature Figure 14. Input Offset Voltage vs Common-Mode Voltage 20 4.5 18 3.5 16 2.5 1.5 12 IOS (nA) VOS Shift (mV) 14 Average of 36 Typical Units 10 8 0.5 -0.5 6 -1.5 4 -2.5 2 -3.5 0 -4.5 0 20 40 60 80 100 120 4 8 12 16 Time (s) Figure 15. Input Offset Voltage vs Time 24 28 Figure 16. Input Offset Current vs Supply Voltage 2.0 4 VS = 36V 10 Typical Units Shown 1.5 3 2 1.0 IB- IB+ 0.5 IB (nA) 1 0 IB-1 0 -0.5 IOS IB+ IOS (V+)-0.5V (V+)-1.0.V (V+)-1.5V (V+)-2.0V (V+)-2.5V (V+)-3.0V (V-)+3.0V -2.0 (V-)+2.5V -1.5 -4 (V-)+2.0V -3 (V-)+1.5V -1.0 (V-)+1.0V -2 (V-)+0.5V IB and IOS (nA) 20 VS (V) 4 8 12 16 20 24 28 32 36 Supply Voltage (V) Common-Mode Voltage (V) Figure 17. Input Bias and Input Offset Currents vs Common-Mode Voltage 10 Submit Documentation Feedback Figure 18. Input Bias Current vs Supply Voltage Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 3.5 2.5 3.0 2.0 2.0 IQ (mA) IQ (mA) 2.5 1.5 1.5 1.0 1.0 0.5 0.5 0 -50 0 -25 0 25 50 75 100 125 150 0 4 8 12 16 Temperature (°C) Figure 19. Quiescent Current vs Temperature 100 0 Sinking VS = ±2.25V -40 -60 Sinking VS = ±18V -80 -100 -50 -25 0 25 50 75 100 125 +85°C 15 Output Voltage (V) ISC (mA) Sourcing VS = ±2.25V -20 36 VS = ±18V 0°C 05 +150°C 0 -50°C +125°C -40°C +85°C -05 0°C -10 -50°C -15 -40°C -20 150 20 30 40 50 60 70 Output Current (mA) Figure 21. Short-Circuit Current vs Temperature Figure 22. Output Voltage vs Output Current G = -1 CL = 100pF G = +1 RL = 604W CL = 100pF RF 604W Device CL 20mV/div +18V 20mV/div 32 10 Temperature (°C) RL 28 Figure 20. Quiescent Current vs Supply Voltage 60 20 24 20 Sourcing VS = ±18V 80 40 20 VS (V) RI 604W +18V Device -18V CL -18V Time (0.1ms/div) Time (0.2ms/div) Figure 23. Small-Signal Step Response Figure 24. Small-Signal Step Response Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 11 OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) G = -1 CL = 100pF G = +1 RL = 604W CL = 100pF 2V/div 2V/div +18V Device RL RF 604W RI 604W CL -18V +18V Device CL -18V Time (1ms/div) Time (1ms/div) Figure 25. Large-Signal Step Response Figure 26. Large-Signal Step Response G = -10 Output VIN 5V/div 5V/div 0V +18V 10kW 1kW Device Output VOUT Device VOUT VIN -18V 37VPP Sine Wave (±18.5V) Time (0.5ms/div) 0.25ms/div Figure 28. Negative Overload Recovery Figure 27. No Phase Reversal 60 10kW 1kW 50 VOUT Device VOUT VIN 5V/div Overshoot (%) G = +1 0V VIN 40 G = -1 30 20 10 G = -10 0 0 200 400 Figure 29. Positive Overvoltage Recovery 12 Submit Documentation Feedback 600 800 1000 1200 1400 1600 Capacitive Load (pF) Time (0.5ms/div) Figure 30. Small-Signal Overshoot vs Capacitive Load Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 7 Detailed Description 7.1 Overview The OPA209 series of precision operational amplifiers are unity-gain stable, and free from unexpected output and phase reversal. Applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. The Functional Block Diagram shows a simplified schematic of the OPA209. This die uses a SiGe bipolar process and contains 180 transistors. 7.2 Functional Block Diagram V+ Pre-Output Driver OUT IN- IN+ V- Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Operating Voltage The OPA209 series of op amps can be used with single or dual supplies within an operating range of VS = 4.5 V (±2.25 V) up to 36 V (±18 V). Supply voltages higher than 40 V total can permanently damage the device (see Absolute Maximum Ratings). In addition, key parameters are assured over the specified temperature range, TA = –40°C to 125°C. Parameters that vary significantly with operating voltage or temperature are shown in the Typical Characteristics. 7.3.2 Input Protection The input terminals of the OPA209 are protected from excessive differential voltage with back-to-back diodes, as shown in Figure 31. In most circuit applications, the input protection circuitry has no consequence. However, in low-gain or G = 1 circuits, fast ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly enough to the input ramp. This effect is illustrated in Figure 25 and Figure 26 in Typical Characteristics. If the input signal is fast enough to create this forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be used to limit the signal input current. This input series resistor degrades the low-noise performance of the OPA209. See Noise Performance for further information on noise performance. Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 13 OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Feature Description (continued) Figure 31 shows an example configuration that implements a current-limiting feedback resistor. RF - OPA209 RI Input Output + Copyright © 2016, Texas Instruments Incorporated Figure 31. Pulsed Operation 7.3.3 Noise Performance Figure 32 shows the total circuit noise for varying source impedances with the op amp in a unity-gain configuration (no feedback resistor network, and therefore no additional noise contributions). Two different op amps are shown with the total circuit noise calculated. The OPA209 has very low voltage noise, making it ideal for low source impedances (less than 2 kΩ). As a comparable precision FET-input op amp (very low current noise), the OPA827 has somewhat higher voltage noise, but lower current noise. It provides excellent noise performance at moderate to high source impedance (10 kΩ and up). For source impedance lower than 300 Ω, the OPA211 may provide lower noise. The equation in Figure 32 shows the calculation of the total circuit noise, with these parameters: • en = voltage noise, • in = current noise, • RS = source impedance, • k = Boltzmann's constant = 1.38 × 10–23 J/K, and • T = temperature in Kelvins For more details on calculating noise, see Basic Noise Calculations. VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE Votlage Noise Spectral Density, EO 10k EO 1k RS OPA209 100 OPA827 Resistor Noise 10 2 2 2 EO = en + (in RS) + 4kTRS 1 100 1k 10k 100k 1M Source Resistance, RS (W) Figure 32. Noise Performance of the OPA209 and OPA827 in Unity-Gain Buffer Configuration 14 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 Feature Description (continued) 7.3.4 Basic Noise Calculations Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the circuit is the root-sum-square combinations of all noise components. The resistive portion of the source impedance produces thermal noise proportional to the square root of the resistance. This function is illustrated in Figure 32. The source impedance is usually fixed; consequently, select the appropriate op amp and the feedback resistors to minimize the respective contributions to the total noise. Figure 33 illustrates both noninverting (Figure 33a) and inverting (Figure 33b) op amp circuit configurations with gain. In circuit configurations with gain, the feedback network resistors also contribute noise. The current noise of the op amp reacts with the feedback resistors to create additional noise components. The feedback resistor values can generally be chosen to make these noise sources negligible. Note that lowimpedance feedback resistors load the output of the amplifier. The equations for total noise are shown for both configurations. A) Noise in Noninverting Gain Configuration Noise at the output: R2 2 2 R1 EO = 1 + R2 R1 2 2 2 2 2 2 en + e1 + e2 + (inR2) + eS + (inRS) EO R2 Where eS = Ö4kTRS ´ 1 + R1 2 1+ R2 R1 = thermal noise of RS RS R2 e1 = Ö4kTR1 ´ R1 VS = thermal noise of R1 e2 = Ö4kTR2 = thermal noise of R2 B) Noise in Inverting Gain Configuration Noise at the output: R2 2 2 EO R1 = 1+ R2 R1 + RS EO RS 2 2 2 2 2 en + e1 + e2 + (inR2) + eS Where eS = Ö4kTRS ´ R2 R1 + RS = thermal noise of RS VS e1 = Ö4kTR1 ´ R2 R1 + RS = thermal noise of R1 e2 = Ö4kTR2 = thermal noise of R2 For the OPA209 series op amps at 1 kHz, en = 2.2 nV/√Hz and In = 530 fA/√Hz. Figure 33. Noise Calculation in Gain Configurations Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 15 OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Feature Description (continued) 7.3.5 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event. See Figure 34 for an illustration of the ESD circuits contained in the OPA209 series (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where they meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat. When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or more of the steering diodes. Depending on the path that the current takes, the absorption device may activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA209 but below the device breakdown voltage level. Once this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level. When the operational amplifier connects into a circuit such as the one Figure 34 shows, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption device. Figure 34 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly higher VIN. As a result, the datasheet specifications recommend that applications limit the input current to 10 mA. If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings. Another common question involves what happens to the amplifier if an input signal is applied to the input while the power supplies +VS and/or –VS are at 0 V. Again, it depends on the supply characteristic while at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be supplied by the input source through the current steering diodes. This state is not a normal bias condition; the amplifier will not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path. If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be added to the supply pins as shown in Figure 34. The Zener voltage must be selected such that the diode does not turn on during normal operation. However, its Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level. 16 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 Feature Description (continued) TVS(2) RF +VS +V OPA209 RI ESD CurrentSteering Diodes -In RS(3) Op Amp Core +In Out Edge-Triggered ESD Absorption Circuit ID VIN(1) RL -V -VS TVS(2) Copyright © 2016, Texas Instruments Incorporated (1) VIN = +VS + 500 mV (2) TVS: +VS(max) > VTVSBR (Min) > +VS (3) Suggested value approximately 1 kΩ Figure 34. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application 7.4 Device Functional Modes The OPAx209 is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power-supply voltage for the OPAx209 is 36 V (±18 V). Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 17 OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The OPAx209 are unity-gain stable, precision operational amplifiers with very low noise. Applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate. 8.2 Typical Application Figure 35. Low-Pass Filter 8.2.1 Design Requirements Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing. The OPAx209 are ideally suited to construct high-speed, high-precision active filters. Figure 35 shows a secondorder, low-pass filter commonly encountered in signal processing applications. Use the following parameters for this design example: • Gain = 5 V/V (inverting gain) • Low-pass cutoff frequency = 25 kHz • Second-order Chebyshev filter response with 3-dB gain peaking in the passband 8.2.2 Detailed Design Procedure The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 35. Use Equation 1 to calculate the voltage transfer function. -1/ R1R3C2C5 Output (s) = 2 Input s + (s / C2 )(1/ R1 + 1/ R3 + 1/ R 4 ) + 1/ R3R 4C2C5 (1) This circuit produces a signal inversion. For this circuit, the gain at DC and the low-pass cutoff frequency are calculated by Equation 2: R Gain = 4 R1 fc = 18 1 (1/ R3R 4C2C5 ) 2p Submit Documentation Feedback (2) Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 Typical Application (continued) 8.2.3 Application Curve Figure 36. OPAx209 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter 9 Power Supply Recommendations The OPAx209 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good printed circuit board (PCB) layout practices, including the following guidelines: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. • Place the external components as close to the device as possible. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. • Cleaning the PCB following board assembly is recommended for best performance. • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, postcleaning bake at 85°C for 30 minutes is sufficient for most circumstances. Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 19 OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 10.2 Layout Example Figure 37. OPAx209 Layout Example 20 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 11.1.1.2 DIP Adapter EVM The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT23-6, SOT23-5 and SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with terminal strips or may be wired directly to existing circuits. 11.1.1.3 Universal Operational Amplifier EVM The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits for a variety of IC package types. The evaluation module board design allows many different circuits to be constructed easily and quickly. Five models are offered, with each model intended for a specific package type. PDIP, SOIC, VSSOP, TSSOP, and SOT-23 packages are all supported. NOTE These boards are unpopulated, so users must provide their own ICs. TI recommends requesting several op amp device samples when ordering the Universal Op Amp EVM. 11.1.1.4 TI Precision Designs TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. 11.1.1.5 WEBENCH® Filter Designer WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to design, optimize, and simulate complete multistage active filter solutions within minutes. Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 21 OPA209, OPA2209, OPA4209 SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 11.2 Documentation Support 11.2.1 Related Documentation The following documents are relevant to using the OPAx209 and recommended for reference. All are available for download at www.ti.com (unless otherwise noted): • OPA827 Low-Noise, High-Precision, JFET-Input Operational Amplifier (SBOS376) • OPA2x11 1.1-nv/√Hz Noise, Low Power, Precision Operational Amplifier (SBOS377) • OPA209, OPA2209, OPA4209 EMI Immunity Performance (SBOZ020) • Microcontroller PWM to 12-bit Analog Out (TIDU027) • Capacitive Load Drive Solution Using an Isolation Resistor (TIDU032) • Noise Measurement Post Amp (TIDU016) • Diagnostic Patient Monitoring and Therapy Guide (SLYB147) 11.3 Related Links Table 1 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA209 Click here Click here Click here Click here Click here OPA2209 Click here Click here Click here Click here Click here OPA4209 Click here Click here Click here Click here Click here 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.6 Trademarks TINA-TI, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. TINA, DesignSoft are trademarks of DesignSoft, Inc. All other trademarks are the property of their respective owners. 11.7 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 22 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 OPA209, OPA2209, OPA4209 www.ti.com SBOS426D – NOVEMBER 2008 – REVISED OCTOBER 2016 11.8 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: OPA209 OPA2209 OPA4209 Submit Documentation Feedback 23 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) OPA209AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 209A Samples OPA209AIDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OOBQ Samples OPA209AIDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OOBQ Samples OPA209AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OOAQ Samples OPA209AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI | NIPDAUAG | NIPDAU Level-2-260C-1 YEAR -40 to 125 OOAQ Samples OPA209AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 209A Samples OPA2209AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O2209 Samples OPA2209AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 OOJI Samples OPA2209AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 OOJI Samples OPA2209AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O2209 Samples OPA4209AIPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (OP4209A, OPA) 4209 Samples OPA4209AIPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (OP4209A, OPA) 4209 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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OPA4209AIPW
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  • 1+73.361871+9.10051
  • 10+54.9939210+6.82197
  • 90+45.6521190+5.66313
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  • 270+42.74297270+5.30225
  • 540+41.31884540+5.12559
  • 1080+40.146261080+4.98013

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