OPA552PA

® OPA 551 OPA OPA 551 551 OPA551 OPA552 For most current data sheet and other product information, visit www.burr-brown.com High-Voltage, High-Current OPERATIONAL AMPLIFIERS FEATURES q q q q WIDE SUPPLY RANGE: ±4V to ±30V HIGH OUTPUT CURRENT: 200mA Continuous LOW NOISE: 14nV/√Hz FULLY PROTECTED: Thermal Shutdown Output Current-Limited THERMAL SHUTDOWN INDICATOR WIDE OUTPUT SWING: 2V From Rail FAST SLEW RATE: OPA551: 15V/µs OPA552: 24V/µs WIDE BANDWIDTH: OPA551: 3MHz OPA552: 12MHz PACKAGES: DIP-8, SO-8, or DDPAK-7 DESCRIPTION The OPA551 and OPA552 are low cost op amps with high-voltage (60V) and high-current (200mA) capability. The OPA551 is unity-gain stable and features high slew rate (15Vµs) and wide bandwidth (3MHz). The OPA552 is optimized for gains of 5 or greater, and offers higher speed with a slew rate of 24V/µs and a bandwidth of 12MHz. Both are suitable for telephony, audio, servo, and test applications. These laser-trimmed, monolithic integrated circuits provide excellent low-level accuracy along with high output swing. High performance is maintained as the amplifier swings to its specified limits. The OPA551 and OPA552 are internally protected against over-temperature conditions and current overloads. The thermal shutdown indicator “flag” provides a current output to alert the user when thermal shutdown has occurred. The OPA551 and OPA552 are available in DIP-8 and SO-8 packages, as well as a DDPAK-7 surfacemount plastic power package. They are specified for operation over the extended industrial temperature range, –40°C to +125°C. q q q q q APPLICATIONS q q q q q TELEPHONY TEST EQUIPMENT AUDIO AMPLIFIER TRANSDUCER EXCITATION SERVO DRIVER OPA551, OPA552 OPA551, OPA552 NC OPA551, OPA552 V– 1 2 3 4 SO-8 (U) 8 7 6 5 Flag V– V+ Out V– DIP-8 (P) 4 5 –In +In 1 2 3 8 7 6 Flag V+ Out NC 1234567 NOTE: Tab is connected to V– supply. –In +In +In NC V+ Flag –In V– Out DDPAK-7 Surface-Mount (F) V– International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® ©1999 Burr-Brown Corporation PDS-1472A 1 Printed in U.S.A. OPA551, OPA552 July, 1999 SPECIFICATIONS: VS = ±30V OPA551 At TJ = +25°C(1), RL = 3kΩ connected to ground and VOUT = 0V, unless otherwise noted. Boldface limits apply over the specified junction temperature range, TJ = –40°C to +125°C. OPA551UA, PA, FA PARAMETER OFFSET VOLTAGE Input Offset Voltage TJ = –40°C to +125°C vs Temperature vs Power Supply INPUT BIAS CURRENT Input Bias Current Input Offset Current NOISE Input Voltage Noise Density, f = 1kHz Current Noise Density, f = 1kHz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain TJ = –40°C to +125°C FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time: 0.1% 0.01% Total Harmonic Distortion + Noise, f = 1kHz Overload Recovery Time OUTPUT Voltage Output TJ = –40°C to +125°C VOUT AOL RL = 3kΩ, –28V < VO < +28V RL = 3kΩ, –28V < VO < +28V RL = 300Ω, –27V < VO < +27V 110 100 IB IOS en in VCM CMRR (V–) + 2.5 92 ±20 ±3 14 3.5 (V+) – 2.5 102 1013 || 2 1013 || 6 126 120 3 ±15 1.3 2 0.0005 0.0005 1 (V–) + 3.0 (V–) + 3.5 (V–) + 2.0 (V–) + 2.5 ±200 (V+) (V+) (V+) (V+) ±380 See Typical Curve – – – – 3.0 3.5 2.0 2.7 ±100 ±100 pA pA nV/√Hz fA/√Hz V dB Ω || pF Ω || pF dB dB dB MHz V/µs µs µs % % µs V V V V mA mA VOS dVOS /dT PSRR CONDITION VCM = 0V, IO = 0 VS = ±4V to ±30V, VCM = 0V MIN TYP ±1 MAX ±3 UNITS mV mV µV/°C µV/V ±7 10 ±5 30 –27.5V < VCM < +27.5V GBW SR THD+N G=1 G = 1, CL = 100pF, 10V Step G = 1, CL = 100pF, 10V Step VO = 15Vrms, RL = 3kΩ, G = 3 VO = 15Vrms, RL = 300Ω, G = 3 VIN • Gain = VS IO = 200mA IO = 200mA IO = 10mA IO = 10mA Package Dependent—See Text Stable Operation TJ = –40°C to +125°C Maximum Continuous Current Output: dc IO Short-Circuit Current ISC Capacitive Load Drive CLOAD SHUTDOWN FLAG Thermal Shutdown Status Output Normal Operation Thermally Shutdown Voltage Compliance Range Junction Temperature Shutdown Reset from Shutdown POWER SUPPLY Specified Voltage Operating Voltage Range Quiescent Current TJ = –40°C to +125°C TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance SO-8 Surface Mount DIP-8 DDPak-7 DDPak-7 VS IQ Sourcing Sourcing 80 V– 0.05 120 1 160 (V+) – 1.5 µA µA V °C °C V V mA mA °C °C °C °C/W °C/W °C/W °C/W 160 140 ±30 ±7 ±4 IO = 0 ±30 ±8.5 ±10 +125 +125 +150 TJ TJ TA –40 –55 –65 90 100 65 3 θJA θJA θJA θJC NOTES: (1) All tests are high-speed tested at +25°C ambient temperature. Effective junction temperature is +25°C unless otherwise noted. ® OPA551, OPA552 2 SPECIFICATIONS: VS = ±30V OPA552 At TJ = +25°C(1), RL = 3kΩ connected to Ground and VOUT = 0V, unless otherwise noted. Boldface limits apply over the specified junciton temperature range, TJ = –40°C to +125°C. OPA552UA, PA, FA PARAMETER OFFSET VOLTAGE Input Offset Voltage TJ = –40°C to +125°C vs Temperature vs Power Supply INPUT BIAS CURRENT Input Bias Current Input Offset Current NOISE Input Voltage Noise Density, f = 1kHz Current Noise Density, f = 1kHz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain TJ = –40°C to +125°C FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time: 0.1% 0.01% Total Harmonic Distortion + Noise, f = 1kHz Overload Recovery Time OUTPUT Voltage Output TJ = –40°C to +125°C VOUT AOL RL = 3kΩ, –28V < VO < +28V RL = 3kΩ, –28V < VO < +28V RL = 300Ω, –27V < VO < +27V 110 100 IB IOS en in VCM CMRR (V–) + 2.5 92 ±20 ±3 14 3.5 (V+) – 2.5 102 1013 || 2 1013 || 6 126 120 12 ±24 2.2 3 0.0005 0.0005 1 (V–) + 3.0 (V–) + 3.5 (V–) + 2.0 (V–) + 2.5 ±200 (V+) (V+) (V+) (V+) ±380 See Typical Curve – – – – 3.0 3.5 2.0 2.7 ±100 ±100 pA pA nV/√Hz fA/√Hz V dB Ω || pF Ω || pF dB dB dB MHz V/µs µs µs % % µs V V V V mA mA VOS dVOS /dT PSRR CONDITION VCM = 0V, IO = 0 VS = ±4V to ±30V, VCM = 0V MIN TYP ±1 MAX ±3 UNITS mV mV µV/°C µV/V ±7 10 ±5 30 –27.5V < VCM < +27.5V GBW SR THD+N G=5 G = 5, CL = 100pF, 10V Step G = 5, CL = 100pF, 10V Step VO = 15Vrms, RL = 3kΩ, G = 5 VO = 15Vrms, RL = 300Ω, G = 5 VIN • Gain = VS IO = 200mA IO = 200mA IO = 10mA IO = 10mA Package Dependent—See Text Stable Operation TJ = –40°C to +125°C Maximum Continuous Current Output: dc IO Short-Circuit Current ISC Capacitive Load Drive CLOAD SHUTDOWN FLAG Thermal Shutdown Status Output Normal Operation Thermally Shutdown Voltage Compliance Range Junction Temperature Shutdown Reset from Shutdown POWER SUPPLY Specified Voltage Operating Voltage Range Quiescent Current TJ = –40°C to +125°C TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance SO-8 Surface Mount DIP-8 DDPak-7 DDPak-7 VS IQ Sourcing Sourcing 80 V– 0.05 120 1 160 (V+) – 1.5 µA µA V °C °C V V mA mA °C °C °C °C/W °C/W °C/W °C/W 160 140 ±30 ±7 ±4 IO = 0 ±30 ±8.5 ±10 +125 +125 +150 TJ TJ TA –40 –55 –65 90 100 65 3 θJA θJA θJA θJC NOTES: (1) All tests are high-speed tested at +25°C ambient temperature. Effective junction temperature is +25°C unless otherwise noted. ® 3 OPA551, OPA552 ABSOLUTE MAXIMUM RATINGS(1) Output Current ................................................................. See SOA Curve Supply Voltage, V+ to V– ................................................................... 60V Input Voltage Range ....................................... (V–) – 0.5V to (V+) + 0.5V Operating Temperature .................................................. –55°C to +125°C Storage Temperature ..................................................... –65°C to +150°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering 10s, DIP-8) ...................................... 300°C (soldering 3s, SO-8 and DDPAK) .................... 240°C ESD Capability (Human Body Model) ............................................. 3000V NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE /ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 182 SPECIFIED TEMPERATURE RANGE –40°C to +125°C PACKAGE MARKING OPA551UA ORDERING NUMBER(2) OPA551UA OPA551UA/2K5 OPA551PA OPA551FA OPA551FA/500 OPA552UA OPA552UA/2K5 OPA552PA OPA552FA OPA552FA/500 TRANSPORT MEDIA Rails Tape and Reel Rails Rails Tape and Reel Rails Tape and Reel Rails Rails Tape and Reel PRODUCT OPA551UA PACKAGE SO-8 " OPA551PA OPA551FA " DIP-8 DDPAK-7 " 006 328 " –40°C to +125°C –40°C to +125°C " OPA551PA OPA551FA " OPA552UA " OPA552PA OPA552FA " SO-8 " 182 " –40°C to +125°C " OPA552UA " DIP-8 DDPAK-7 " 006 328 " –40°C to +125°C –40°C to +125°C " OPA552PA OPA552FA " " " " " NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Products followed by a slash (/) are only available in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA551UA/2K5” will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA551, OPA552 4 TYPICAL PERFORMANCE CURVES At TJ = +25°C, VS = ±30V and RL = 3kΩ, unless otherwise noted. All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. OPEN-LOOP GAIN AND PHASE vs FREQUENCY OPA551 140 OPA551 120 100 80 Gain –20 –40 –60 Gain (dB) OPEN-LOOP GAIN AND PHASE vs FREQUENCY OPA552 0 140 OPA552 120 100 80 Gain –20 –40 –60 Phase –80 –100 –120 –140 –160 1 10 100 1k 10k 100k 1M –180 10M Phase (°) 0 Gain (dB) Phase (°) Phase 60 40 20 0 –20 –40 1 10 100 1k 10k 100k 1M Frequency (Hz) –80 –100 –120 –140 –160 –180 10M 60 40 20 0 –20 –40 Frequency (Hz) COMMON-MODE REJECTION RATIO vs FREQUENCY 120 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 120 100 POWER SUPPLY REJECTION RATIO vs FREQUENCY –PSRR CMRR (dB) PSRR (dB) 80 60 +PSRR 40 20 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY 10k TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 0.1 VO = 15Vrms RL = 3kΩ, 300Ω G = 3 (OPA551) G = 5 (OPA552) in Voltage Noise (nV/√Hz) Current Noise (fA/√Hz) 1k 100 THD+N (%) 1M 0.01 0.001 10 en 1 10 100 1k 10k 100k Frequency (Hz) 0.0001 1 100 1k Frequency (Hz) 10k 100k ® 5 OPA551, OPA552 TYPICAL PERFORMANCE CURVES At TJ = +25°C, VS = ±30V and RL = 3kΩ, unless otherwise noted. (Cont.) All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY ±30 (V+) (V+)–1 Output Voltage Swing (V) OUTPUT VOLTAGE SWING vs OUTPUT CURRENT Maximum Output Voltage (V) ±25 ±20 OPA552 ±15 ±10 ±5 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) Without Slew-Induced Distortion OPA551 +85°C +25°C (V+)–2 (V+)–3 (V–)+3 (V–)+2 (V–)+1 (V–) 0 50 100 150 200 250 300 350 400 Output Current (mA) +85°C –55°C –55°C +25°C OPEN-LOOP GAIN, POWER SUPPLY REJECTION RATIO, AND COMMON-MODE REJECTION RATIO vs TEMPERATURE 130 125 120 115 AOL INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs TEMPERATURE 100k 10k Current (pA) Gain (dB) 110 105 100 95 90 85 80 –75 –25 25 1k +IB 100 –IB –IOS PSRR CMRR 10 75 125 1 –75 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE 9 8 7 6 IQ (mA) GAIN BANDWIDTH PRODUCT vs TEMPERATURE 450 Gain Bandwidth Product (MHz) 100 430 IQ –ISC +ISC 410 390 ISC (mA) 5 4 3 2 1 0 –75 –50 –25 0 25 370 350 330 310 290 270 OPA552 10 OPA551 50 75 100 125 150 1 –80 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) ® OPA551, OPA552 6 TYPICAL PERFORMANCE CURVES At TJ = +25°C, VS = ±30V and RL = 3kΩ, unless otherwise noted. (Cont.) All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. SLEW RATE vs TEMPERATURE 35 30 Slew Rate (V/µs) 25 20 OPA551 15 10 5 0 –60 –40 –20 Current (pA) INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs COMMON-MODE VOLTAGE 30 25 20 –IB +IB OPA552 15 10 5 0 –5 –30 IOS 0 20 40 60 80 100 120 140 –20 –10 0 10 20 30 Junction Temperature (°C) Common-Mode Voltage (V) QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs SUPPLY VOLTAGE 7.6 405 18 15 OFFSET VOLTAGE PRODUCTION DISTRIBUTION Typical production distribution of packaged units. Short-Circuit Current (mA) Quiescent Current (mA) 7.2 –ISC IQ 395 Percent of Amplifiers (%) 12 9 6 3 0 6.8 385 6.4 +ISC 375 6.0 0 5 10 15 20 25 30 35 Supply Voltage (V) 365 < –3.0 < –2.4 < –1.8 < –1.2 < –0.6 < 0.0 < 0.6 < 1.2 < 1.8 < 2.4 Offset Voltage (mV) OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION 18 16 Typical production distribution of packaged units. SETTLING TIME vs CLOSED-LOOP GAIN 100 OPA551 0.01% Settling Time (µs) Percent of Amplifiers (%) 14 12 10 8 6 4 2 0 OPA551 0.1% 10 OPA552 0.01% OPA552 0.1% 1 < 0.0 < 1.5 < 3.0 < 4.50 < 6.0 < 7.5 < 9.0 < 10.5 < 12.0 < 13.5 < 15.0 1 10 Gain (V/V) < 3.0 100 Offset Drift µV/°C ® 7 OPA551, OPA552 TYPICAL PERFORMANCE CURVES At TJ = +25°C, VS = ±30V and RL = 3Ω, unless otherwise noted. (Cont.) All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient temperatures for a specific configuration. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 60 50 Overshoot (%) LARGE-SIGNAL STEP RESPONSE OPA551, G = 1, CL = 100pF OPA551 OPA552 G = –4 OPA551, G = 1 40 30 20 10 OPA552, G = –8 0 0.01 0.1 1 OPA552 G = –6 OPA551 G = –1 5V/div OPA551 G = –2 10 Time (1µs/div) Load Capacitance (nF) LARGE-SIGNAL STEP RESPONSE OPA552, G = 5, CL = 100pF OPA552 SMALL-SIGNAL STEP RESPONSE OPA551, G = 1, CL = 100pF OPA551 Time (1µs/div) 25mV/div 5V/div Time (1µs/div) SMALL-SIGNAL STEP RESPONSE OPA552, G = 5, CL = 100pF OPA552 SMALL-SIGNAL STEP RESPONSE OPA551, G = –1, CL = 1000pF OPA551 100mV/div Time (1µs/div) 5V/div Time (1µs/div) ® OPA551, OPA552 8 APPLICATIONS INFORMATION Figure 1 shows the OPA551 connected as a basic noninverting amplifier. The OPA551 can be used in virtually any op amp configuration. OPA552 is designed for use in configurations with gains of 5 or greater. Power supply terminals should be bypassed with 0.1µF capacitors, or greater, near the power supply pins. Be sure that the capacitors are appropriately rated for the power supply voltage used. The OPA551 and OPA552 can supply output currents up to 200mA with excellent performance. CURRENT LIMIT The OPA551 and OPA552 are designed with internal current-limiting circuitry that limits the output current to approximately 380mA. The current limit varies with increasing junction temperature as shown in the typical curve “Current Limit vs Temperature.” This, in combination with the thermal protection circuitry, provides protection from many types of overload conditions including short circuit to ground. THERMAL PROTECTION The OPA551 and OPA552 have thermal shutdown circuitry that protects the amplifier from damage caused by overload conditions. The thermal protection circuitry disables the output when the junction temperature reaches approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is automatically re-enabled. The thermal shutdown function is not intended to replace proper heat sinking. Activation of the thermal shutdown circuitry is an indication of excessive power dissipation or an inadequate heat sink. Continuously running the amplifier into thermal shutdown can degrade reliability. The Thermal Shutdown Indicator (“flag”) pin can be monitored to determine if shutdown is occurring. During normal operation, the current output from the flag pin is typically 50nA. During shutdown, the current output from the flag pin increases to 120µA (typical). This current output allows for easy interfacing to external logic. See Figure 2 for two examples implementing this function. V+ 10µF + 0.1µF R1 R2 G = 1+ R2 R1 OPA551 VIN Flag (optional) ZL VO 0.1µF 10µF + V– FIGURE 1. Basic Circuit Connections. OPA551 Flag 80µA to 160µA HCT logic has relatively wellcontrolled logic level. A properly chosen resistor value can guarantee proper logic high level throughout the full range of flag output current. VOUT OPA551 VOUT VLOGIC +5V Interface to virtually any CMOS logic gate by choosing resistor value that provides a guaranteed logic high voltage with the minimum (80µA) flag current. A diode clamp to the logic supply voltage assures that the CMOS is not damaged by overdrive. HP5082-2835 HCT 27kΩ CMOS 47kΩ Logic Ground Logic Ground Interfacing with HCT Logic Interfacing with CMOS Logic FIGURE 2. Thermal Shutdown Indicator. ® 9 OPA551, OPA552 POWER SUPPLIES The OPA551 and OPA552 may be operated from power supplies of ±4V to ±30V, or a total of 60V with excellent performance. Most behavior remains unchanged throughout the full operating voltage range. Parameters that vary significantly with operating voltage are shown in the Typical Performance Curves. For applications that do not require symmetrical output voltage swing, power supply voltages do not need to be equal. The OPA551 and OPA552 can operate with as little as 8V between the supplies or with up to 60V between the supplies. For example, the positive supply could be set to 50V with the negative supply at –10V or vice-versa. The SO-8 package outline shows three negative supply (V–) pins. These pins are internally connected for improved thermal performance. Pin 4 is to be used as the primary current carrier for the negative supply. It is recommended that pins 1 and 5 not be directly connected to V– but, instead be connected to a thermal mass. DO NOT lay out the PC board to use pins 1 and 5 as feedthroughs to the negative supply. Doing so can result in a reduction of performance. The tab of the DDPAK-7 package is electrically connected to the negative supply (V–), however, this connection should not be used to carry current. For best thermal performance, the tab should be soldered directly to the circuit board copper area (see heat sink text). POWER DISSIPATION Internal power dissipation of these op amps can be quite large. Many of the specifications for the OPA551 and OPA552 are for a specified junction temperature. If the device is not subjected to internal self-heating, the junction temperature will be the same as the ambient. However, in practical applications, the device will self-heat and the junction temperature will be significantly higher than ambient. After junction temperature has been established, performance parameters that vary with junction temperature can be determined from the performance curves. The following calculation can be performed to establish junction temperature as a function of ambient temperature and the conditions of the application. Consider the OPA551 in a circuit configuration where the load is 600Ω and the output voltage is 15V. The supplies are at ±30V and the ambient temperature (TA) is 40°C. The θJA for the 8-pin DIP package is 100°C/W. First, the internal heating of the op amp is as follows: PD(internal) = IQ • VS = 7.2mA • 60V = 432mW The output current (IO) can be calculated: IO = VOUT /RL = 15V/600Ω = 25mA The power being dissipated (PD) in the output transistor of the amplifier can be calculated: PD(output stage) = IO • (VS – VO) = 25mA • (30 – 15) = 375mW PD(total) = PD(internal) + PD(output stage) = 432mW + 375mW = 807mW The resulting junction temperature can be calculated: TJ = TA + PD θJA TJ = 40°C + 807mW • 100°C/W = 120.7°C Where, TJ = junction temperature (°C) TA = ambient temperature (°C) θJA = junction-to-air thermal resistance (°C/W) For the DDPAK package, the θJA is 65°C/W with no heat sinking, resulting in a junction temperature of 92.5°C. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is activated. Use worst-case load and signal conditions. For good reliability, the thermal protection should trigger more than +35°C above the maximum expected ambient condition of your application. This ensures a maximum junction temperature of +125°C at the maximum expected ambient condition. If the OPA551 or OPA552 is to be used in an application requiring more than 0.5W continuous power dissipation, it is recommended that the DDPAK package option be used. The DDPAK has superior thermal dissipation characteristics and is more easily adapted to a heat sink. Operation from a single power supply (or unbalanced power supplies) can produce even larger power dissipation since a larger voltage can be impressed across the conducting output transistor. Consult Application Bulletin AB-039 for further information on how to calculate or measure power dissipation. Power dissipation can be minimized by using the lowest possible supply voltage. For example, with a 200mA load, the output will swing to within 3.5V of the power supply rails. Power supplies set to no more than 3.5V above the maximum output voltage swing required by the application will minimize the power dissipation. SAFE OPERATING AREA The Safe Operating Area (SOA curves, Figures 3, 4, and 5) shows the permissible range of voltage and current. The curves shown represent devices soldered to a circuit board with no heat sink. The safe output current decreases as the voltage across the output transistor (VS – VO) increases. For further insight on SOA, consult Application Bulletin AB-039. Output short circuits are a very demanding case for SOA. A short circuit to ground forces the full power supply voltage (V+ or V–) across the conducting transistor and produces a typical output current of 380mA. With ±30V ® OPA551, OPA552 10 power supplies, this creates an internal dissipation of 11.4W. This far exceeds the maximum rating and is not recommended. If operation in this region is unavoidable, use the DDPAK with a heat sink. HEAT SINKING Power dissipated in the OPA551 or OPA552 will cause the junction temperature to rise. For reliable operation, the junction temperature should be limited to +125°C. Many applications will require a heat sink to assure that the maximum operating junction temperature is not exceeded. The heat sink required depends on the power dissipated and on ambient conditions. For heat sinking purposes, the tab of the DDPAK is typically soldered directly to a circuit board copper area. Increasing the copper area improves heat dissipation. Figure 6 shows typical thermal resistance from junction-to-ambient as a function of copper area. Depending on conditions, additional heat sinking may be required. Aavid Thermal Products Inc. manufactures surface-mountable heat sinks designed specifically for use with DDPAK packages. Further information is available on Aavid’s web site, www.aavid.com. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is activated. Use worst-case load and signal conditions. For good reliability, the thermal protection should trigger more than +25°C above the maximum expected ambient condition of your application. This produces a junction temperature of +125°C at the maximum expected ambient condition. SAFE OPERATING AREA—8-PIN DIP 1000 25°C 100 IO (mA) 125°C 10 85°C 1 0.1 1 10 | VS | – | VO | (V) 100 FIGURE 3. DIP-8 Safe Operating Area. SAFE OPERATING AREA—SO-8 1000 25°C 100 IO (mA) 125°C 10 85°C Thermal Resistance, θJA (°C/W) 50 THERMAL RESISTANCE vs CIRCUIT BOARD COPPER AREA 1 40 OPA551, OPA552 Surface-Mount Package 1oz. copper 30 0.1 1 10 | VS | – | VO | (V) 100 20 FIGURE 4. SO-8 Safe Operating Area. 10 0 0 1 2 3 4 5 SAFE OPERATING AREA—DDPAK 1000 25°C 100 IO (mA) Copper Area (inches2) 25°C 1" Copper Circuit Board Copper Area 125°C 10 125°C 1" Copper 85°C 1 0.1 1 10 | VS | – | VO | (V) 100 OPA551, OPA552 Surface-Mount Package FIGURE 5. DDPAK-7 Safe Operating Area. 11 FIGURE 6. DDPAK Thermal Resistance vs Circuit Board Copper Area. ® OPA551, OPA552 CAPACITIVE LOADS The dynamic characteristics of the OPA551 and OPA552 have been optimized for commonly encountered gains, loads, and operating conditions. The combination of low closedloop gain and capacitive load will decrease the phase margin and may lead to gain peaking or oscillations. Figure 7 shows a circuit that preserves phase margin with capacitive load. Figure 8 shows the small-signal step response for the circuit in Figure 7. Consult Application Bulletin AB-028 for more information. can be used to boost output current. The circuit in Figure 10 is capable of supplying output currents up to 1A. Alternatively, the OPA547, OPA548, and OPA549 series power op amps should be considered for high output current drive, along with programmable current limit and output disable capability. R1 R2 RS(1) 10Ω +30V VIN “MASTER” OPA551 OPA551 RG 4kΩ VI CS 1.8nF –30V NOTE: (1) RS resistors minimize the circulating current that can flow between the two devices due to VOS errors. CF 220pF RF 4kΩ 10nF OPA551 “SLAVE” RL RS(1) 10Ω FIGURE 7. Driving Large Capacitive Loads. SMALL-SIGNAL STEP RESPONSE OPA551, G = –1, CL = 10nF OPA551 FIGURE 9. Parallel Amplifers Increase Output Current Capability. R1 R2 +30V 20mV/div TIP29C CF R3(1) 100Ω OPA551 VIN R4 0.2Ω VO R4 0.2Ω LOAD TIP30C Time (2.5µs/div) FIGURE 8. Small-Signal Step Response for Figure 7. INCREASING OUTPUT CURRENT In those applications where the 200mA of output current is not sufficient to drive the desired load, output current can be increased by connecting two or more OPA551s or OPA552s in parallel as shown in Figure 9. Amplifier A1 is the “master” amplifier and may be configured in virtually an op amp circuit. Amplifier A2, the “slave”, is configured as a unity gain buffer. Alternatively, external output transistors –30V NOTE: (1) R3 provides current limit and allows the amplifier to drive the load when the output is between 0.7V and –0.7V. FIGURE 10. External Output Transistors Boost Output Current Up to 1 Amp. ® OPA551, OPA552 12 INPUT PROTECTION The OPA551 and OPA552 feature internal clamp diodes to protect the inputs when voltages beyond the supply rails are encountered. However, input current should be limited to 5mA. In some cases, an external series resistor may be required. Many input signals are inherently current-limtied, therefore, a limiting resistor may not be required. Please consider that a “large” series resistor, in conjunction with the input capacitance, can affect stability. USING THE OPA552 IN LOW GAINS The OPA552 family is intended for applications with signal gains of 5 or greater, but it is possible to take advantage of their high slew rate in lower gains using an external compensation technique in an inverting configuration. This technique maintains low noise characteristics of the OPA552 architecture at low frequencies. Depending on the application, a small increase in high frequency noise may result. This technique shapes the loop gain for good stability while giving an easily controlled secondorder low-pass frequency response. Considering only the noise gain (non-inverting signal gain) for the circuit of Figure 11, the low frequency noise gain (NG1) will be set by the resistor ratios, while the high frequency noise gain (NG2) will be set by the capacitor ratios. The capacitor values set both the transition frequencies and the high frequency noise gain. If this noise gain, determined by NG2 = 1 + CS/CF, is set to a value greater than the recommended minimum stable gain for the op amp and the noise gain pole, set by 1/RFCF, is placed correctly, a very well controlled, 2nd-order lowpass frequency response will result. To choose the values for both CS and CF, two parameters and only three equations need to be solved. First, the target for the high frequency noise gain (NG2) should be greater than the minimum stable gain for the OPA552. In the circuit in Figure 11, a target NG2 of 10 is used. Second, the signal gain of –1 shown in Figure 11 sets the low frequency noise gain to NG1 = 1 + RF/RG (=2 in this example). Using these two gains, knowing the Gain Bandwidth Product (GBP) for the OPA552 (12MHz), and targeting a maximally flat 2nd-order, low-pass Butterworth frequency response (Q = 0.707), the key frequency in the compensation can be found. For the values shown in Figure 11, the f–3dB will be approximately 956kHz. This is less than that predicted by simply dividing the GBP by NG1. The compensation network controls the bandwidth to a lower value while providing the full slew rate at the output and an exceptional distortion performance due to increased loop gain at frequencies below NG1 • Z0. The capacitor values shown in Figure 11 are calculated for NG1 = 2 and NG2 = 10 with no adjustment for parasitics. Actual circuit values can be optimized by check the small-signal step response with actual load conditions. Figure 12 shows the small-signal step response of this OPA552, G = –1 circuit with a 500pF load. It is wellbehaved with no tendency to oscillate. If CS and CF were removed, the circuit would be unstable. +30V OPA552 RG 1kΩ VIN CS 1.88nF –30V NG1 = 1 + RF/RG = 2 NG2 = 1 + CS/CF = 10 CF 208pF RF 1kΩ VOUT FIGURE 11. Compensation of the OPA552 for G = 1. SMALL-SIGNAL STEP RESPONSE OPA552, G = –1, CL = 500pF OPA552 20mV/div Time (1µs/div) FIGURE 12. Small-Signal Step Response for Figure 11. ® 13 OPA551, OPA552 OFFSET VOLTAGE ERROR CALCULATION The offset voltage (VOS) of the OPA51 and OPA552 is specified with a ±30V power supply and the commonmode voltage centered between the supplies (VS/2 = 0V). Additional specifications for power supply rejection and common-mode rejection are provided to allow the user to easily calculate worst-case excepted offset under the conditions of a given application. Power Supply Rejection Ratio (PSRR) is specified in µV/V. For the OPA551 and OPA552, worst-case PSRR is 30µV/V, which means for each volt of change in total power supply voltage, the offset may shift by up to 30µV/V. Common-Mode Rejection Ratio (CMRR) is specified in dB, which can be converted to µV/V using the following equation: CMRR in (V/V) = 10[(CMRR in dB)/–20] (1) calculate excursions from the specified offset voltage under different applications conditions. For example, a common application might configure the amplifier with a –48 single supply with –6V common-mode. This configuration represents a 12V variation in power supply: ±30V or 60V in the offset specification versus 48V in the application. In addition, this configuration has an 18V variation in common-mode voltage: VS/2 = –24V is the specification for these power supplies, but the common-mode voltage is –6V in the application. Calculation of the worst-case expected offset would be as follows: Worst-case VOS = (2) maximum specified VOS + (power supply variation • PSRR + (common-mode variation • CMRR) VOSwc = 5mV + (12V • 30µV/V) + (18V • 15.8µV/V) = ±5.64mV For the OPA551 and OPA552, the worst-case CMRR at ±30mV supply over the full common-mode range is 96dB, or approxmately 15.8µV/V. This means that for every volt of change in common-mode, the offset may shift up to 15.8µV. These numbers can be used to ® OPA551, OPA552 14