OPA602BP

OPA602 OPA OPA 602 602 SBOS155A – AUGUST 1987 – REVISED OCTOBER 2002 High-Speed Precision Difet ® OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● ● ● WIDE BANDWIDTH: 6.5MHz HIGH SLEW RATE: 35V/µs LOW OFFSET: ±250µV max LOW BIAS CURRENT: ±1pA max FAST SETTLING TIME: 1µs to 0.01% UNITY-GAIN STABLE PRECISION INSTRUMENTATION OPTOELECTRONICS SONAR, ULTRASOUND PROFESSIONAL AUDIO EQUIPMENT MEDICAL EQUIPMENT DATA CONVERSION DESCRIPTION +VS The OPA602 is a precision, wide bandwidth FET operational amplifier. Monolithic Difet (dielectrically isolated FET) construction provides an unusual combination of high-speed and accuracy. Its wide-bandwidth design minimizes dynamic errors. High slew rate and fast settling time allow accurate signal processing in pulse and data conversion applications. Wide bandwidth and low distortion minimize AC errors. All specifications are rated with a 1kΩ resistor in parallel with 500pF load. The OPA602 is unity-gain stable and easily drives capacitive loads up to 1500pF. (7) –In (2) +In (3) Cascode Output (6) Laser-trimmed input circuitry provides offset voltage and drift performance normally associated with precision bipolar op amps. Difet construction achieves extremely low input bias currents (1pA max) without compromising input voltage noise. The OPA602’s unique input cascode circuitry maintains low input bias current and precise input characteristics over its full input common-mode voltage range. –VS (4) (1) Difet® Burr-Brown Corp. (5) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1987, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage ............................................................................... ±18VDC Internal Power Dissipation (TJ ≤ +175°C) .................................... 1000mW Differential Input Voltage .............................................................. Total VS Input Voltage Range ............................................................................ ±VS Storage Temperature Range P and U Packages ....................................................... –40°C to +125°C Operating Temperature Range P and U Packages ........................................................ –25°C to + 85°C Lead Temperature U Package, SO (3s) .................................................................... +260°C Output Short-Circuit to Ground (+25°C) ................................... Continuous Junction Temperature .................................................................... +175°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT OFFSET VOLTAGE MAX (µV) AT 25°C PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE OPA602AP OPA602BP ±2000 DIP-8 P –25°C to +85°C 602AP 602AP Tubes, 50 ±1000 " " " 602BP 602BP Tubes, 50 OPA602AU ±3000 SO-8 D –25°C to +85°C 602AU 602AU Tubes, 100 PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATIONS Top View DIP, SO Offset Trim 1 8 NC –In 2 7 +VS +In 3 6 Output –VS 4 5 Offset Trim Offset Trim 1 8 NC –In 2 7 +VS +In 3 6 Output –VS 4 5 Offset Trim SO-8 DIP-8 2 NC = No Connection OPA602 www.ti.com SBOS155A ELECTRICAL CHARACTERISTICS At VS = ±15VDC and TA = +25°C, unless otherwise noted. OPA602BP PARAMETER CONDITIONS MIN INPUT NOISE Voltage: fO = 10Hz fO = 100Hz fO = 1kHz fO = 10kHz fB = 10Hz to 10kHz fB = 0.1Hz to 10Hz Current: fB = 0.1Hz to 10Hz fO = 0.1Hz to 20kHz OFFSET VOLTAGE Input Offset Voltage: P Package U Package Over Specified Temperature P, U Packages Average Drift(1) Supply Rejection TA = TMIN to TMAX ±VS = 12V to 18V 80 TYP OPA602AP, AU MAX MIN TYP MAX UNITS 23 19 13 12 1.4 0.95 ✻ ✻ ✻ ✻ ✻ ✻ nV/ √Hz nV/ √Hz nV/ √Hz nV/ √Hz µVrms µVp-p 12 0.6 ✻ ✻ fAp-p fA/ √Hz 0.5 1 1 1 2 3 mV mV ±0.75 ±3 100 ±1.5 ±5 ±1.5 ✻ ✻ ±15 mV µV/°C dB 70 BIAS CURRENT Input Bias Current Over Specified Temperature VCM = 0VDC ±1 ±20 ±2 ±200 ±2 ±20 ±10 ±500 pA pA OFFSET CURRENT Input Offset Current Over Specified Temperature VCM = 0VDC 0.5 20 2 200 1 20 10 500 pA pA INPUT IMPEDANCE Differential Common-Mode 1013 || 1 1014 || 3 INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection VIN = ±10VDC OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Gain Bandwidth Full-Power Response Slew Rate Settling Time: 0.1% 0.01% RATED OUTPUT Voltage Output Current Output Output Resistance Load Capacitance Stability Short-Circuit Current POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent Over Specified Temperature TEMPERATURE RANGE Specification Operating: P, U Packages Storage: P, U Packages θJA ✻ ✻ Ω || pF Ω || pF ±10.2 88 +13, –11 100 ✻ 75 ✻ ✻ V dB RL ≥ 1kΩ 88 100 75 ✻ dB Gain = 100 20Vp-p, RL = 1kΩ VO = ±10V, RL = 1kΩ 4 6.5 570 35 3.5 ✻ ✻ ✻ MHz kHz V/µs ✻ µs µs ±11 ✻ V ✻ ✻ ✻ ✻ ✻ mA Ω pF mA 24 Gain = –1, RL = 1kΩ CL = 500pF, 10V Step 20 0.6 1.0 RL = 1kΩ ±11.5 VO = ±10VDC 1MHz, Open Loop Gain = +1 ±15 ±30 ±5 +12.9, –13.8 ±20 80 1500 ±50 ±15 ✻ ✻ ✻ ✻ VDC VDC mA mA ✻ ✻ °C +85 ✻ ✻ °C +125 ✻ ✻ ✻ °C/W °C ±18 4 4.5 ✻ –25 +85 –25 –40 200 IO = 0mADC 3 3.5 Ambient Temperature ±25 ✻ ✻ ✻ Same specifications as OPA602BP. NOTE: (1) OPA602AP, AU ensured by design with a 99% confidence level. OPA602 SBOS155A www.ti.com 3 TYPICAL CHARACTERISTICS At TA = +25°C and VS = ±15VDC, unless otherwise noted. INPUT VOLTAGE NOISE SPECTRAL DENSITY INPUT CURRENT NOISE SPECTRAL DENSITY 1k Voltage Noise (nV/√Hz) Current Noise (fA/√Hz) 100 10 1 100 10 1 0.1 1 10 100 1k 10k 100k 1 1M 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) POWER-SUPPLY REJECTION AND COMMON-MODE REJECTION vs TEMPERATURE TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY AT 1kHz vs SOURCE RESISTANCE 110 1k Voltage Noise, EO (nV/√Hz) CMR and PSR (dB) EO 105 CMR 100 PSR 95 RS 100 OPA602 + Resistor 10 Resistor Noise Only 1 90 –75 –50 –25 0 25 50 75 100 100 125 1k Temperature (°C) 10k 100k 1M 10M 100M Source Resistance (Ω) COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE OPEN-LOOP FREQUENCY RESPONSE 140 120 90 –45 100 80 φ –90 60 40 –135 AOL 80 20 0 –15 –10 –5 0 +5 +10 +15 –180 1 Common-Mode Voltage (V) 10 100 1k 10k 100k 1M 10M Frequency (Hz) OPA602 www.ti.com SBOS155A Phase Shift (degrees) 100 70 4 CL = 100pF 110 Voltage Gain (dB) Common-Mode Rejection (dB) RL = 1kΩ 120 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C and VS = ±15VDC, unless otherwise noted. GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE GAIN BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE 10 37 38 8 6 33 Slew Rate 4 31 2 29 –75 –50 –25 0 25 50 75 100 36 GBW 6 34 Slew Rate 5 125 5 0 32 10 15 Ambient Temperature (°C) Supply Voltage (±VCC) OPEN-LOOP GAIN vs TEMPERATURE MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY 20 30 120 Output Voltage (Vp-p) 110 Voltage Gain (dB) 7 100 90 20 10 RL = 1kΩ 0 80 –75 –50 –25 0 25 50 75 100 10k 125 100k 1M 10M Frequency (Hz) Ambient Temperature (°C) LARGE-SIGNAL TRANSIENT RESPONSE SMALL-SIGNAL TRANSIENT RESPONSE 10 Output Voltage (mV) Output Voltage (V) 150 0 –10 100 50 0 –50 –100 –150 0 1 2 3 4 5 0 Time (µs) OPA602 SBOS155A 2 5 Time (µs) www.ti.com 5 Slew Rate (V/µs) 35 GBW Gain Bandwidth (MHz) 8 Slew Rate (V/µs) Gain Bandwidth (MHz) AV = –1 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C and VS = ±15VDC, unless otherwise noted. SETTLING TIME vs CLOSED-LOOP GAIN SUPPLY CURRENT vs TEMPERATURE 5 3.5 3 0.01% 2 3.25 Supply Current (mA) Settling Time (µs) 4 0.1% 1 3.0 2.75 RL = 1kΩ CL = 100pF 0 –1 –10 –100 2.5 –75 –1k –50 –25 0 25 50 75 Closed-Loop Gain (V/V) Ambient Temperature (°C) OPEN-LOOP GAIN vs SUPPLY VOLTAGE TOTAL HARMONIC DISTORTION vs FREQUENCY 1 104 100 125 40.2kΩ THD + Noise (%rms) Voltage Gain 402Ω 100 96 6.5Vrms 1kΩ 0.1 AV = +101V/V AV = +101V/V 0.01 AV = +1V/V 92 0.001 15 20 10 100 1k 10k Frequency (Hz) BIAS AND OFFSET CURRENT vs TEMPERATURE BIAS AND OFFSET CURRENT vs INPUT COMMON MODE VOLTAGE 10nA 1nA 1nA 100 100 10 10 100k 10 Bias Current (pA) 10nA 1 10 Bias Current 1 Offset Current 0.1 0.1 1 1 0.1 –50 –25 0 25 50 75 100 0.1 125 0.01 0.01 –15 –10 –5 0 5 10 15 Common-Mode Voltage (V) Ambient Temperature (°C) 6 1 0.1 Supply Voltage (±VCC) Offset Current (pA) Bias Current (pA) 10 OPA602 www.ti.com SBOS155A Offset Current (pA) 5 0 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C and VS = ±15VDC, unless otherwise noted. COMMON-MODE REJECTION vs FREQUENCY 140 120 120 Common-Mode Rejection (dB) Power-Supply Rejection (dB) POWER-SUPPLY REJECTION vs FREQUENCY 140 100 80 – + 60 40 20 0 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 1 10M 10 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) APPLICATIONS INFORMATION INPUT BIAS CURRENT GUARDING Unity-gain stability with good phase margin and excellent output drive characteristics bring freedom from the subtle problems associated with other high-speed amplifiers. However, as with any high-speed, wide bandwidth circuitry, careful circuit layout will ensure best performance. Make short, direct interconnections and avoid stray wiring capacitance— especially at the inverting input pin. Leakage currents across printed circuit boards can easily exceed the input bias current of the OPA602. A circuit board “guard” pattern, as shown in Figure 1, is an effective solution to difficult leakage problems. This guard pattern must be repeated on all layers of a multilayer board. By surrounding critical high impedance input circuitry with a low impedance circuit connection at the same potential, leakage currents will flow harmlessly to the low-impedance node. Power supplies should be bypassed with good high-frequency capacitors positioned close to the op amp pins. In most cases 0.1µF ceramic capacitors are adequate. Applications with heavier loads and fast transient waveforms may benefit from use of additional 1.0µF tantalum bypass capacitors. Input bias current may also be degraded by improper handling or cleaning. Contamination from handling parts and circuit boards may be cleaned with appropriate solvents and deionized water. Each rinsing operation should be followed by a 30-minute bake at +85°C. Noninverting Buffer 2 2 OPA602 In 6 Out 3 OPA602 6 Out 3 In Inverting In 2 Board Layout for Input Guarding: Guard top and bottom of board. Alternate—use Teflon® standoff for sensitive input pins. OPA602 6 Out 3 Teflon® E.I. Du Pont de Nemours & Co. FIGURE 1. Connection of Input Guard. OPA602 SBOS155A www.ti.com 7 APPLICATION CIRCUITS MSB B1 • 16 +VS 17 7 • • • • • • • • • B12 4 5 6 7 8 9 10 11 12 13 14 15 +15V DAC7541A VOUT Out 2 OPA602 OPA602 2 3 2 3 1 Out 1 VREFERENCE C1 15pF 18 RF 6 1 5 4 100kΩ ±10mV Typical Trim Range Single-Point Ground (1) –VCC B B B  B V OUT = − VREF  1 + 2 + 3 + L + 12   2 4 8 4096  –VS −10V ≤ VREF ≤ +10V 0 ≤ V OUT ≤ − NOTE: (1) 10kΩ to 1MΩ trim potentiometer (100kΩ recommended). 4095 VREF 4096 Where: BN = 1 if the BN digital input is high. BN = 0 if the BN digital input is low. FIGURE 2. Offset Voltage Trim. FIGURE 3. Voltage Output Digital-to-Analog Converter. (2) HP 5082-2835 2kΩ 2kΩ 50Ω +15V 47pF 1µF High-Quality Pulse Generator + 2kΩ 510Ω +15V 1µF 1µF Tantalum Pulse In ±5V + 2kΩ + 1/2 2N5564 51Ω Output OPA602 Error Out ±0.5mV (0.01%) 1µF Tantalum + CL 500pF –15V 1/2 2N5564 1µF + 510Ω 1µF + –15V FIGURE 4. Settling Time and Slew Rate Test Circuit. 8 OPA602 www.ti.com SBOS155A PACKAGE DRAWINGS P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 OPA602 SBOS155A www.ti.com 9 PACKAGE DRAWINGS (Cont) D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. 10 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 OPA602 www.ti.com SBOS155A PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) OPA602AU ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 OPA 602AU Samples OPA602AU/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 OPA 602AU Samples OPA602AU/2K5E4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 OPA 602AU Samples OPA602AUE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 OPA 602AU Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of