OPA
631
OPA631
OPA632
www.ti.com
Low-Power, Single-Supply
OPERATIONAL AMPLIFIERS
TM
FEATURES
DESCRIPTION
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The OPA631 and OPA632 are low-power, high-speed,
voltage-feedback amplifiers designed to operate on a
single +3V or +5V supply. Operation on ±5V or +10V
supplies is also supported. The input range extends
below ground and to within 1V of the positive supply.
Using complementary common-emitter outputs provides an output swing to within 30mV of ground and
130mV of the positive supply. The high output drive
current and low differential gain and phase errors also
make them ideal for single-supply consumer video
products.
Low distortion operation is ensured by the high gain
bandwidth product (68MHz) and slew rate (100V/µs),
making the OPA631 and OPA632 ideal input buffer
stages to 3V and 5V CMOS converters. Unlike other
low-power, single-supply amplifiers, distortion performance improves as the signal swing is decreased. A
low 6nV input voltage noise supports wide dynamic
range operation. Channel multiplexing or system power
reduction can be achieved using the high-speed disable
line on the OPA632. Power dissipation can be reduced
to zero by taking the disable line HIGH.
The OPA631 and OPA632 are available in an industrystandard SO-8 package. The OPA631 is also available
in an ultra-small SOT23-5 package, while the OPA632
is available in the SOT23-6. Where higher full-power
bandwidth and lower distortion are required in a singlesupply operational amplifier, consider the OPA634
and OPA635.
HIGH BANDWIDTH: 75MHz (G = +2)
LOW SUPPLY CURRENT: 6mA
ZERO POWER DISABLE (OPA632)
+3V TO +10V OPERATION
INPUT RANGE INCLUDES GROUND
4.8V OUTPUT SWING ON +5V SUPPLY
HIGH SLEW RATE: 100V/µs
LOW INPUT VOLTAGE NOISE: 6nV/√Hz
AVAILABLE IN SOT23 PACKAGE
APPLICATIONS
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SINGLE-SUPPLY ADC INPUT BUFFERS
SINGLE-SUPPLY VIDEO LINE DRIVERS
CCD IMAGING CHANNELS
LOW-POWER ULTRASOUND
PLL INTEGRATORS
PORTABLE CONSUMER ELECTRONICS
+3V
Disable
2.26kΩ
374Ω
DIS
VIN
100Ω
+3V
Pwrdn
ADS901
10-Bit
20Msps
OPA632
22pF
RELATED PRODUCTS
562Ω
750Ω
DESCRIPTION
Copyright © 1999, Texas Instruments Incorporated
SBOS066A
SINGLES
DUALS
Medium Speed, No Disable
With Disable
OPA631
OPA632
OPA2631
—
High Speed, No Disable
With Disable
OPA634
OPA635
OPA2634
—
Printed in U.S.A. February, 2001
SPECIFICATIONS: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
OPA631U, N
OPA632U, N
TYP
GUARANTEED
CONDITIONS
+25°C
+25°C
0°C to
70°C
–40°C to
+85°C
UNITS
MIN/
MAX
TEST
LEVEL(1)
G = +2, VO ≤ 0.5Vp-p
G = +5, VO ≤ 0.5Vp-p
G = +10, VO ≤ 0.5Vp-p
G ≥ +10
VO ≤ 0.5Vp-p
G = +2, 2V Step
0.5V Step
0.5V Step
G = +2, 1V Step
VO = 2Vp-p, f = 5MHz
f > 1MHz
f > 1MHz
75
16
7.6
68
5
100
5.3
5.4
17
42
6.0
1.9
0.5
1.2
50
12
5.6
51
—
64
8.0
7.5
28
40
6.8
2.6
—
—
40
10
4.2
40
—
52
11
10
38
38
7.6
2.9
—
—
32
8.5
3.7
36
—
47
12.8
11.6
42
35
7.9
3.6
—
—
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dBc
nV/√Hz
pA/√Hz
%
degrees
min
min
min
min
typ
min
max
max
max
min
max
max
typ
typ
B
B
B
B
C
B
B
B
B
B
B
B
C
C
62
2.5
—
11
0.3
—
56
6
—
25
1.5
—
50
8
—
31
1.8
—
46
11
50
48
2.8
7
dB
mV
µV/°C
µA
µA
nA/°C
min
max
max
max
max
max
A
A
B
A
A
B
–0.5
4.0
74
–0.1
3.7
70
–0.1
3.7
68
–0.1
3.5
60
V
V
dB
max
min
min
B
A
A
10 || 2.1
400 || 1.2
—
—
—
—
—
—
kΩ || pF
kΩ || pF
typ
typ
C
C
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current (output shorted to either supply)
Closed-Loop Output Impedance
G = +2, f ≤ 100kHz
0.03
0.16
4.87
4.60
80
90
100
0.2
0.07
0.17
4.8
4.4
25
35
—
—
0.10
0.20
4.7
4.4
20
22
—
—
0.13
1.7
4.6
3.1
5
9
—
—
V
V
V
V
mA
mA
mA
Ω
max
max
min
min
min
min
typ
typ
A
A
A
A
A
A
C
C
DISABLE (OPA632 only)
On Voltage (device enabled Low)
Off Voltage (device disabled High)
On Disable Current (DIS pin)
Off Disable Current (DIS pin)
Disabled Quiescent Current
Disable Time
Enable Time
Off Isolation
f = 5MHz, Input to Output
1.0
3.7
70
0
0
100
60
70
1.0
3.8
110
—
20
—
—
—
1.0
4.0
120
—
25
—
—
—
1.0
4.2
120
—
30
—
—
—
V
V
µA
µA
µA
ns
ns
dB
max
min
max
typ
max
typ
typ
typ
A
A
A
C
A
C
C
C
VS = +5V
VS = +5V
Input Referred
—
—
6
6
59
2.7
10.5
6.6
5.8
52
2.7
10.5
6.9
5.5
49
2.7
10.5
7.1
4.8
48
V
V
mA
mA
dB
min
max
max
min
min
B
A
A
A
A
–40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
PARAMETER
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth
Gain Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Spurious Free Dynamic Range
Input Voltage Noise
Input Current Noise
NTSC Differential Gain
NTSC Differential Phase
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Offset Current Drift
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: U, N
Thermal Resistance
U
SO-8
N
SOT23-5, SOT23-6
VCM = 2.0V
VCM = 2.0V
Input Referred
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
2
OPA631, OPA632
SBOS066A
SPECIFICATIONS: VS = +3V
At TA = 25°C, G = +2 and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
OPA631U, N
OPA632U, N
TYP
PARAMETER
AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth
Gain Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Spurious Free Dynamic Range
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Offset Current Drift
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Short Circuit Current (output shorted to either supply)
Closed-Loop Output Impedance
DISABLE (OPA632 only)
On Voltage (device enabled Low)
Off Voltage (device disabled High)
On Disable Current (DIS pin)
Off Disable Current (DIS pin)
Disabled Quiescent Current
Disable Time
Enable Time
Off Isolation
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: U, N
Thermal Resistance
U
SO-8
N
SOT23-5, SOT23-6
GUARANTEED
CONDITIONS
+25°C
+25°C
0°C to
70°C
UNITS
G = +2, VO ≤ 0.5Vp-p
G = +5, VO ≤ 0.5Vp-p
G = +10, VO ≤ 0.5Vp-p
G ≥ +10
VO ≤ 0.5Vp-p
1V Step
0.5V Step
0.5V Step
1V Step
VO = 1Vp-p, f = 5MHz
f > 1MHz
f > 1MHz
61
15
7.7
63
5
95
5.6
5.6
40
44
6.2
2.0
45
11
4.6
47
—
52
9
9
63
37
7.0
2.6
35
9
4.0
34
—
46
11.3
11.3
85
34
7.8
2.9
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dBc
nV/√Hz
pA/√Hz
min
min
min
min
typ
min
max
max
max
min
max
max
B
B
B
B
C
B
B
B
B
B
B
B
60
0.5
—
12
0.3
—
54
3.8
—
25
1
—
50
4.3
45
30
1.3
2
dB
mV
µV/°C
µA
µA
nA/°C
min
max
max
max
max
max
A
A
B
A
A
B
–0.5
2
72
–0.3
1.75
66
–0.1
1.3
65
V
V
dB
max
min
min
B
A
A
10 || 2.1
400 || 1.2
—
—
—
—
kΩ || p
kΩ || p
typ
typ
C
C
Figure 2, f < 100kHz
0.03
0.05
2.95
2.85
55
55
80
0.2
0.05
0.15
2.85
2.66
21
20
—
—
0.05
0.16
2.84
2.60
14
13
—
—
V
V
V
V
mA
mA
mA
Ω
max
max
min
min
min
min
typ
typ
A
A
A
A
A
A
C
C
f = 5MHz, Input to Output
1.0
1.7
66
0
0
100
60
70
1.0
1.8
100
—
20
—
—
—
1.0
1.8
110
—
25
—
—
—
V
V
µA
µA
µA
ns
ns
dB
max
min
max
typ
max
typ
typ
typ
A
A
A
C
A
C
C
C
VS = +3V
VS = +3V
Input Referred
—
—
5.3
5.3
57
2.7
10.5
5.9
5.0
50
2.7
10.5
6.4
4.8
48
V
V
mA
mA
dB
min
max
max
min
min
B
A
A
A
A
–40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
VCM = 1.0V
VCM = 1.0V
Input Referred
RL = 1kΩ to 1.5V
RL = 150Ω to 1.5V
RL = 1kΩ to 1.5V
RL = 150Ω to 1.5V
MIN/ TEST
MAX LEVEL(1)
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
OPA631, OPA632
SBOS066A
3
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Power Supply ................................................................................ +11VDC
Internal Power Dissipation .................................... See Thermal Analysis
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range .................................................... –0.5 to +VS + 0.3V
Storage Temperature Range: P, U, N ........................... –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
PIN CONFIGURATIONS
Top View—OPA631, OPA632
NC
1
8
DIS (OPA632 only)
Inverting Input
2
7
+VS
Non-Inverting Input
3
6
Output
GND
4
5
NC
SO-8
Top View—OPA632
Top View—OPA631
Non-Inverting Input
3
4
Inverting Input
Output
1
6
+VS
GND
2
5
DIS
Non-Inverting Input
3
4
Inverting Input
SOT23-6
6
4
6
SOT23-5
A32
1
3
2
1
A31
4
2
+VS
Pin Orientation/Package Marking
3
GND
6
5
1
2
Output
Pin Orientation/Package Marking
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
OPA631U
SO-8 Surface-Mount
182
–40°C to +85°C
OPA631U
"
"
"
"
SOT23-5
331
–40°C to +85°C
A31
"
"
"
"
SO-8 Surface-Mount
182
–40°C to +85°C
OPA632U
"
"
"
"
SOT23-6
332
–40°C to +85°C
A32
"
"
"
"
"
OPA631N
"
OPA632U
"
OPA632N
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
OPA631U
OPA631U/2K5
OPA631N/250
OPA631N/3K
Rails
Tape and Reel
Tape and Reel
Tape and Reel
OPA632U
OPA632U/2K5
OPA632N/250
OPA632N/3K
Rails
Tape and Reel
Tape and Reel
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /3K indicates 3000 devices per reel). Ordering 3000 pieces
of “OPA632N/3K” will get a single 3000-piece Tape and Reel.
4
OPA631, OPA632
SBOS066A
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
LARGE-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
12
6
VO = 200mVp-p
0
9
G = +2
VO = 0.2Vp-p
6
3
–3
Gain (dB)
Normalized Gain (dB)
3
–6
–9
G = +5
–12
–15
0
–3
VO = 1Vp-p
–6
VO = 2Vp-p
–9
G = +10
–18
–12
–21
–15
VO = 4Vp-p
–18
–24
1
10
100
1
300
10
SMALL-SIGNAL PULSE RESPONSE
VO = 4Vp-p
Input and Output Voltage (500mV/div)
Input and Output Voltage (50mV/div)
300
LARGE-SIGNAL PULSE RESPONSE
VO = 200mVp-p
VO
VIN
VO
VIN
Time (10ns/div)
Time (10ns/div)
DISABLE FEEDTHROUGH vs FREQUENCY
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
Disable Voltage (1V/div)
100
Frequency (MHz)
Frequency (MHz)
–35
VDIS
OPA632 Only
VDIS = +5V
–40
VIN = 0.5V
OPA632 Only
Time (50ns/div)
VO
Feedthrough (dB)
Output Voltage (250mV/div)
–45
–50
–55
–60
–65
–70
–75
–80
–85
1
10
100
1000
Frequency (MHz)
OPA631, OPA632
SBOS066A
5
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
1MHz 2nd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
1MHz 3rd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–30
3rd-Harmonic Distortion (dBc)
2nd-Harmonic Distortion (dBc)
–30
–40
–50
–60
RL = 250Ω
–70
RL = 150Ω
–80
–90
RL = 250Ω
–50
RL = 150Ω
–60
–70
–80
–90
0.1
1
4
0.1
1
4
Output Voltage (Vp-p)
Output Voltage (Vp-p)
5MHz 2nd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
5MHz 3rd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–30
–30
RL = 500Ω
3rd-Harmonic Distortion (dBc)
2nd-Harmonic Distortion (dBc)
RL = 500Ω
–40
–40
RL = 250Ω
–50
RL = 150Ω
–60
–70
–80
RL = 250Ω
–40
–50
RL = 150Ω
–60
–70
–80
RL = 500Ω
–90
–90
0.1
1
0.1
4
4
Output Voltage (Vp-p)
10MHz 2nd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
10MHz 3rd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–30
–30
RL = 500Ω
3rd-Harmonic Distortion (dBc)
2nd-Harmonic Distortion (dBc)
1
Output Voltage (Vp-p)
–40
RL = 250Ω
–50
RL = 150Ω
–60
–70
–80
–40
–50
–60
RL = 500Ω
–70
RL = 250Ω
–80
RL = 150Ω
–90
–90
0.1
1
Output Voltage (Vp-p)
6
4
0.1
1
4
Output Voltage (Vp-p)
OPA631, OPA632
SBOS066A
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
2nd-HARMONIC DISTORTION vs FREQUENCY
3rd-HARMONIC DISTORTION vs FREQUENCY
–30
VO = 2Vp-p
RL = 150Ω
–40
3rd-Harmonic Distortion (dBc)
2nd-Harmonic Distortion (dBc)
–30
G = +2
–50
G = +5
–60
G = +10
–70
–80
–90
–50
–60
G = +2
–70
1
10
0.1
1
10
Frequency (MHz)
Frequency (MHz)
HARMONIC DISTORTION vs LOAD RESISTANCE
TWO-TONE, 3rd-ORDER
INTERMODULATION SPURIOUS
–30
–30
–40
3rd-Order Spurious Level (dBc)
VO = 2Vp-p
fO = 5MHz
–50
3rd-Harmonic Distortion
–60
–70
2nd-Harmonic Distortion
–80
–90
fO = 10MHz
–40
–50
–60
–70
fO = 5MHz
–80
fO = 1MHz
Load Power at
Matched 50Ω Load
–90
100
200
300
400
500
–16
–14
–12
RL (Ω)
–10
–8
–6
–4
–2
0
Single-Tone Load Power (dBm)
CMRR AND PSRR vs FREQUENCY
INPUT NOISE DENSITY vs FREQUENCY
80
100
CMRR
75
70
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
Rejection Ratio, Input Referred (dB)
G = +5
G = +10
–80
–90
0.1
Harmonic Distortion (dBc)
–40
VO = 2Vp-p
RL = 150Ω
65
PSRR
60
55
50
45
40
10
Voltage Noise, eni = 6.0nV/√Hz
Current Noise, ini = 1.9pA/√Hz
35
30
1
100
1k
10k
100k
Frequency (Hz)
OPA631, OPA632
SBOS066A
1M
10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
7
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
RS vs CAPACITIVE LOAD
1000
FREQUENCY RESPONSE vs CAPACITIVE LOAD
2
CL = 1000pF
1
CL = 10pF
Normalized Gain (dB)
0
RS (Ω)
100
10
–1
CL = 100pF
–2
–3
–4
RS
–5
OPA63x
VO
CL
–6
–7
1
1000
CLOSED-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
100k
1M
10M
100M
300
100
Output Impedance (Ω)
G = +1
RF = 25Ω
Open-Loop Phase (°)
0
–30
–60
–90
–120
–150
–180
–210
–240
–270
–300
–330
–360
10
1
0.1
1G
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
INPUT DC ERRORS vs TEMPERATURE
POWER SUPPLY AND OUTPUT CURRENT
vs TEMPERATURE
20
4.5
18
4.0
16
3.5
14
Input Offset Voltage
3.0
12
2.5
10
2.0
8
Input Bias Current
1.5
6
10X Input Offset Current
4
0.5
2
0.0
0
–20
0
20
40
Temperature (°C)
60
80
100
12
Quiescent-Supply Current (mA)
5.0
–40
100
OPEN-LOOP GAIN AND PHASE
Open-Loop Gain
1.0
10
Frequency (MHz)
Open-Loop Phase
10k
1
120
Sinking Output Current
10
100
Sourcing Output Current
8
6
80
60
Quiescent Supply Current
4
40
2
20
0
0
–40
–20
0
20
40
60
80
100
Temperature (°C)
OPA631, OPA632
SBOS066A
Output Current (mA)
100
Capacitive Load (pF)
Input Bias Current (µA)
10x Input Offset Current (µA)
Open-Loop Gain (dB)
100
90
80
70
60
50
40
30
20
10
0
–10
–20
10
1k
Input Offset Voltage (mV)
+VS/2
–8
1
8
1kΩ
TYPICAL PERFORMANCE CURVES: VS = +3V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
LARGE-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
12
6
VO = 200mVp-p
0
9
G = +2
VO = 200mVp-p
6
–3
3
G = +5
Gain (dB)
Normalized Gain (dB)
3
–6
–9
–12
–15
0
–3
VO = 1Vp-p
–6
–9
G = +10
–18
–12
–21
–15
VO = 2Vp-p
–18
–24
1
10
100
300
1
10
–30
VO = 1Vp-p
RL = 150Ω
3rd-Harmonic Distortion (dBc)
2nd-Harmonic Distortion (dBc)
–40
G = +2
–50
–60
G = +5
–70
G = +10
–80
VO = 1Vp-p
RL = 150Ω
–40
–50
–60
G = +2
–70
G = +5
G = +10
–80
–90
–90
0.1
1
0.1
10
1
10
Frequency (MHz)
Frequency (MHz)
HARMONIC DISTORTION vs LOAD RESISTANCE
TWO-TONE, 3rd-ORDER
INTERMODULATION SPURIOUS
–30
–30
VO = 1Vp-p
fO = 5MHz
–40
3rd-Order Spurious Level (dBc)
Harmonic Distortion (dBc)
300
3rd-HARMONIC DISTORTION vs FREQUENCY
2nd-HARMONIC DISTORTION vs FREQUENCY
–30
100
Frequency (MHz)
Frequency (MHz)
3rd-Harmonic Distortion
–50
–60
–70
2nd-Harmonic Distortion
–80
–90
fO = 10MHz
–40
–50
–60
fO = 5MHz
–70
fO = 1MHz
–80
Load Power at
Matched 50Ω Load
–90
100
200
300
RL (Ω)
OPA631, OPA632
SBOS066A
400
500
–16
–14
–12
–10
–8
–6
–4
Single-Tone Load Power (dBm)
9
TYPICAL PERFORMANCE CURVES: VS = +3V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
RS vs CAPACITIVE LOAD
1000
FREQUENCY RESPONSE vs CAPACITIVE LOAD
6
3
Normalized Gain (dB)
RS (Ω)
100
10
CL = 1000pF
VO = 0.2Vp-p
0
–3
–6
CL = 100pF
–9
–12
RS
–15
OPA63x
VO
CL
–18
–21
1
1kΩ
+VS/2
–24
10
100
1000
1
10
100
Capacitive Load (pF)
Frequency (MHz)
OUTPUT SWING vs LOAD RESISTANCE
SUPPLY AND OUTPUT CURRENTS
vs SUPPLY VOLTAGE
300
1.0
10
200
2.9
0.9
9
180
0.8
2.7
0.7
2.6
0.6
2.5
0.5
2.4
0.4
2.3
0.3
2.2
0.2
Minimum VO
2.1
0.1
2.0
50
Minimum Output Voltage (V)
Maximum VO
2.8
Quiescent-Supply Current (mA)
3.0
0.0
1000
100
8
160
Quiescent-Supply Current
7
140
6
120
5
100
4
80
Output Current, Sinking
3
2
60
40
Output Current, Sourcing
1
20
0
0
3
4
5
RL (Ω)
6
7
8
9
10
Supply Voltage (V)
SLEW RATE AND GAIN BANDWIDTH PRODUCT
vs SUPPLY VOLTAGE
120
Slew Rate
Slew Rate (V/µs)
100
100
80
80
Gain Bandwidth Product
60
60
40
40
20
20
0
Gain Bandwidth Product (MHz)
120
0
3
4
5
6
7
8
9
10
Supply Voltage (V)
10
OPA631, OPA632
SBOS066A
Output Current (mA)
1
Maximum Output Voltage (V)
CL = 10pF
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK OPERATION
The OPA631 and OPA632 are unity-gain stable, very highspeed, voltage-feedback op amps designed for single-supply
operation (+3V to +10V). The input stage supports input
voltages below ground, and to within 1.0V of the positive
supply. The complementary common-emitter output stage
provides an output swing to within 30mV of ground and
130mV of the positive supply. They are compensated to
provide stable operation with a wide range of resistive loads.
The OPA632’s internal disable circuitry is intended to minimize system power when disabled.
Figure 1 shows the AC-coupled, gain of +2 configuration
used for the +5V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground. Voltage swings reported in the
Specifications are taken directly at the input and output pins.
For the circuit of Figure 1, the total effective load on the
output at high frequencies is 150Ω || 1500Ω. The disable pin
(OPA632 only) needs to be driven by a low impedance
source, such as a CMOS inverter. The 1.50kΩ resistors at
the non-inverting input provide the common-mode bias
voltage. Their parallel combination equals the DC resistance
at the inverting input, minimizing the output DC offset.
Figure 2 shows the DC-coupled, gain of +2 configuration
used for the +3V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground. Though not strictly a “rail-to-rail”
design, these parts come very close, while maintaining
excellent performance. They will deliver ≈ 2.9Vp-p on a
single +3V supply with 61MHz bandwidth. The 374Ω and
2.26kΩ resistors at the input level-shift VIN so that VOUT is
within the allowed output voltage range when VIN = 0.
See the typical performance curves for information on driving capacitive loads.
+VS = 3V
6.8µF
+
2.26kΩ
0.1µF
374Ω
VIN
DIS (OPA632 only)
57.6Ω
VOUT
OPA63x
RL
150Ω
RG
562Ω
RG
750Ω
+VS
2
+VS = 5V
6.8µF
+
1.50kΩ
FIGURE 2. DC-Coupled Signal—Resistive Load to Supply
Midpoint.
0.1µF
0.1µF
VIN
DIS (OPA632 only)
53.6Ω
1.50kΩ
VOUT
OPA63x
RL
150Ω
0.1µF
RG
750Ω
RF
750Ω
+VS
2
FIGURE 1. AC-Coupled Signal—Resistive Load to Supply
Midpoint.
OPA631, OPA632
SBOS066A
SINGLE-SUPPLY ADC CONVERTER INTERFACE
The front page shows a DC-coupled, single-supply ADC
(Analog-to-Digital Converter) driver circuit. Many systems
are now requiring +3V supply capability of both the ADC
and its driver. The OPA632 provides excellent performance
in this demanding application. Its large input and output
voltage ranges, and low distortion, support converters such
as the ADS901 shown in this figure. The input level-shifting
circuitry was designed so that VIN can be between 0V and
0.5V, while delivering an output voltage of 1V to 2V for the
ADS901. Both the OPA632 and ADS901 have power reduction pins with the same polarity for those systems that need
to conserve power.
11
DC LEVEL SHIFTING
Figure 3 shows a DC-coupled non-inverting amplifier that
level-shifts the input up to accommodate the desired output
voltage range. Given the desired signal gain (G), and the
amount VOUT needs to be shifted up (∆VOUT) when VIN is at
the center of its range, the following equations give the
resistor values that produce the desired performance. Start
by setting R4 between 200Ω and 1.5kΩ.
NG = G + ∆VOUT/VS
R1 = R4/G
NON-INVERTING AMPLIFIER WITH
REDUCED PEAKING
Figure 4 shows a non-inverting amplifier that reduces peaking at low gains. The resistor RC compensates the OPA631
or OPA632 to have higher Noise Gain (NG), which reduces
the AC response peaking (typically 5dB at G = +1 without
RC) without changing the DC gain. VIN needs to be a low
impedance source, such as an op amp. The resistor values
are low to reduce noise. Using both RT and RF helps
minimize the impact of parasitic impedances.
R2 = R4/(NG – G)
R3 = R4/(NG –1)
where:
RT
NG = 1 + R4/R3 (Noise Gain)
VIN
VOUT = (G)VIN + (NG – G)VS
RC
Make sure that VIN and VOUT stay within the specified input
and output voltage ranges.
RG
VOUT
OPA63x
RF
+VS
R2
R1
VIN
FIGURE 4. Compensated Non-Inverting Amplifier.
OPA63x
VOUT
The Noise Gain can be calculated as follows:
R3
R4
FIGURE 3. DC Level-Shifting Circuit.
The front page circuit is a good example of this type of
application. It was designed to take VIN between 0V and
0.5V, and produce VOUT between 1V and 2V, when
using a +3V supply. This means G = 2.00, and
∆VOUT = 1.50V – G • 0.25V = 1.00V. Plugging into the
above equations (with R4 = 750Ω) gives: NG = 2.33,
R1 = 375Ω, R2 = 2.25kΩ, and R3 = 563Ω. The resistors were
changed to the nearest standard values.
12
G1 = 1 +
RF
RG
G2 = 1 +
R T + R F / G1
RC
NG = G1G 2
A unity gain buffer can be designed by selecting
RT = RF = 20.0Ω and RC = 40.2Ω (do not use RG ).
This gives a Noise Gain of 2, so its response will be similar
to the typical performance curves with G = +2, which
typically give a flat frequency response, but with less bandwidth.
OPA631, OPA632
SBOS066A
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA631 and OPA632 in
their three package styles. These are available free as an
unpopulated PC board delivered with descriptive documentation. The summary information for these boards in Table I.
PRODUCT
PACKAGE
OPA63xU
OPA63xN
SO-8
SOT23-5
SOT23-6
BOARD
PART
NUMBER
LITERATURE
REQUEST
NUMBER
DEM-OPA68xU
DEM-OPA6xxN
MKT-351
MKT-348
TABLE I. Demo Board Summary Information.
Contact the Texas Instruments Technical Applications Support Line at 1-972-644-5580 to request any of these boards.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Since the OPA631 and OPA632 are voltage feedback op
amps, a wide range of resistor values may be used for the
feedback and gain setting resistors. The primary limits on
these values are set by dynamic range (noise and distortion)
and parasitic capacitance considerations. For a non-inverting
unity gain follower application, the feedback connection
should be made with a 20Ω resistor, not a direct short (see
Figure 4 with RG = ∞). This will isolate the inverting input
capacitance from the output pin and improve the frequency
response flatness. Usually, for G > 1 application, the feedback resistor value should be between 200Ω and 1.5kΩ.
Below 200Ω, the feedback network will present additional
output loading which can degrade the harmonic distortion
performance. Above 1.5kΩ, the typical parasitic capacitance
(approximately 0.2pF) across the feedback resistor may
cause unintentional band-limiting in the amplifier response.
A good rule of thumb is to target the parallel combination of
RF and RG (Figure 1) to be less than approximately 400Ω.
The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward response.
Assuming a 3pF total parasitic on the inverting node, holding RF || RG
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