OPA687U

® OPA 687 OPA687 For most current data sheet and other product information, visit www.burr-brown.com Wideband, Ultra-Low Noise, Voltage Feedback OPERATIONAL AMPLIFIER With Power Down TM FEATURES q HIGH GAIN BANDWIDTH: 3.8GHz q LOW INPUT VOLTAGE NOISE: 0.95nV/√Hz q VERY LOW DISTORTION: –95dBc (5MHz) q LOW DISABLED POWER: 2mW q VERY HIGH SLEW RATE: 900V/µs q STABLE FOR G ≥ 12 APPLICATIONS q q q q q q LOW DISTORTION ADC DRIVER OC-3 FIBER OPTIC RECEIVER LOW NOISE DIFFERENTIAL AMPLIFIERS EQUALIZING RECEIVERS ULTRASOUND CHANNEL AMPLIFIERS IMPROVED REPLACEMENT FOR THE CLC425 DESCRIPTION The OPA687 combines a very high gain bandwidth and large signal performance with an ultra-low input noise voltage (0.95nV/√Hz) while dissipating only 18mA supply current. Where power savings is paramount, the OPA687 also includes an optional power down pin that, when pulled low, will disable the amplifier and decrease the quiescent current to only 1% of its powered up value. This optional feature may be left disconnected to insure normal amplifier operation when no power-down is required. The combination of low input voltage and current noise, along with a 3.8GHz gain bandwidth product, make the OPA687 an ideal amplifier for wideband transimpedance +5V VCM 100Ω OPA687 20Ω stages. As a voltage gain stage, the OPA687 is optimized for a flat frequency response at a gain of +20 and is guaranteed stable down to gains of +12. New external compensation techniques allows the OPA687 to be used at any inverting gain with excellent frequency response control. Using this compensation can give an extremely high dynamic range ADC driver to support > 40MSPS 12- and 14-bit converters. OPA687 RELATED PRODUCTS SINGLES OPA642 OPA643 OPA686 DUAL INPUT NOISE VOLTAGE (nV/√Hz) 2.7 2.3 1.3 GAIN BANDWIDTH PRODUCT (MHz) 210 800 1600 OPA2686 +5V –60 50Ω Source –5V VIN+ 850Ω 80pF ADS852 14-Bit 65MSPS 3rd-Order Spurious (dBc) 1.7pF 39pF –65 4Vp-p –70 1:2 < 6dB Noise Figure 39pF 850Ω –75 2Vp-p +5V 100Ω OPA687 VCM 1.7pF 20Ω 80pF VIN– –80 –85 0 5 10 15 20 25 30 35 40 45 50 Center Frequency (MHz) –5V Ultra-High Dynamic Range Differential Input ADC Driver Measured 2-Tone, 3rd-Order Distortion for Differential ADC Driver. IInternational Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product In ® © 1998 Burr-Brown Corporation PDS-1372C 1 Printed in U.S.A. OPA687 May, 2000 SPECIFICATIONS: VS = ±5V RL = 100Ω, RF = 750Ω, and RG = 39.2Ω, G = +20 (Figure 1 for AC performance only), unless otherwise noted. OPA687U, N TYP +25°C 600 290 75 3800 35 3 –74 –95 –108 –110 43 0.95 2.5 1.2 900 17 15 8 85 ±0.1 –20 ±0.2 +25°C(2) GUARANTEED 0°C to 70°C(3) –40°C to +85°C(3) MIN/ TEST MAX LEVEL(1) typ min min min min max max max max max min max max max min typ max max min max max max max max max min min typ typ min min min min typ typ max max min min max min max max typ typ typ typ typ typ C B B B B B B B B B B B B B B C B B A A B A B A B A A C C A A A A C C A A A A A A A A C C C C C C PARAMETER AC PERFORMANCE (Figure 1) Closed-Loop Bandwidth CONDITIONS G = +12, RG = 39.2Ω, VO = 200mVp-p G = +20, RG = 39.2Ω, VO = 200mVp-p G = +50, RG = 39.2Ω, VO = 200mVp-p G ≥ +50 G = +20, RL = 100Ω G = +20, f = 5MHz, VO = 2Vp-p RL = 100Ω RL = 500Ω RL = 100Ω RL = 500Ω G = +20, f = 20MHz f > 1MHz f > 1MHz 0.2V Step 2V Step 2V Step 2V Step 2V Step V O = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V UNITS MHz MHz MHz MHz MHz dB dBc dBc dBc dBc dBm nV/√Hz pA/√Hz ns V/µs ns ns ns dB mV µV/°C µA nA/°C µA nA/°C V dB kΩ || pF MΩ || pF Gain Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +12 Harmonic Distortion 2nd Harmonic 3rd Harmonic Two-Tone, 3rd-Order Intercept Input Voltage Noise Density Input Current Noise Density Pulse Response Rise/Fall Time Slew Rate Settling Time to 0.01% 0.1% 1% DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Bias Current Drift (magnitude) Input Offset Current Input Offset Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential Common-Mode OUTPUT Output Voltage Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Quiescent Current, max Quiescent Current, min Power Supply Rejection Ratio +PSRR, –PSRR POWER-DOWN (Disabled Low) Power-Down Quiescent Current (+VS) On Voltage (Enabled High or Floated) Off Voltage (Disabled Asserted Low) Power-Down Pin Input Bias Current Power-Down Time Power-Up Time Off Isolation THERMAL Specification U, N Thermal Resistance, θJA U 8-Pin, SO-8 N 6-Pin, SOT23 180 60 3000 24 8 –70 –90 –95 –105 40 1.1 3.2 2.0 675 18 11 78 160 54 2700 20 10 –68 –88 –90 –100 39 1.15 3.3 2.2 550 20 13 75 ±1.2 5 –36 –50 ±1.5 ±12 ±2.9 83 140 48 2400 18 14 –65 –85 –85 –95 37 1.3 3.5 2.5 450 25 17 70 ±1.6 10 –40 –100 ±1.8 ±15 ±2.8 78 ±1 –33 ±1.0 ±3.0 88 VCM = ±0.5V, Input Referred VCM = 0V VCM = 0V ≥ 400Ω Load 100Ω Load V O = 0V VO = 0V G = +20, f = < 100kHz ±3.2 100 2.5 || 2.5 1.0 || 1.2 ±3.6 ±3.5 80 –80 0.006 ±5 ±6 18.5 18.5 85 –225 3.3 1.8 100 200 60 70 –40 to +85 ±3.3 ±3.2 60 –60 ±3.1 ±2.9 50 –50 ±3.0 ±2.8 40 –40 V V mA mA Ω V V mA mA dB µA V V µA ns ns dB °C VS = ±5V VS = ±5V |VS| = 4.5V to 5.5V, Input Referred (Pin 8 SO-8; Pin 5 on SOT23-6) ±6 19 18 80 –300 3.5 1.7 160 ±6 19.5 17.5 78 –350 3.6 1.6 160 ±6 20.5 16 75 –400 3.7 1.5 160 (VDIS = 0) 5MHz, Input to Output Junction to Ambient 125 150 °C/W °C/W NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for +25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node. VCM is the input common-mode voltage. (5) Tested 100kΩ) will benefit from the low input noise current of a FET-input op amp such as the OPA655. Unity gain stability in the op amp is NOT 8 50Ω Source 50Ω Load VI 50Ω VO 50Ω OPA687 RF 750Ω RG 39.2Ω + –VS –5V 6.8µF 0.1µF FIGURE 1. Non-Inverting G = +20 Specifications and Test Circuit. ® OPA687 required for application as a transimpedance amplifier. Figure 3 shows one possible transimpedance design example that would be particularly suitable for the 155Mbit data rate of an OC-3 receiver. Designs that require high bandwidth from a large area detector with relatively low transimpedance gain will benefit from the low input voltage noise for the OPA687. The amplifier’s input voltage noise is peaked up, at the output, over frequency by the diode source capacitance and can, in many cases, become the dominant output noise contribution. The key elements to the design are the expected diode capacitance (CD) with the reverse bias voltage (–VB) applied, the desired transimpedance gain, RF, and the GBP for the OPA687 (3600MHz). With these three variables set (and including the parasitic input capacitance for the OPA687 added to CD), the feedback capacitor value (CF) may be set to control the frequency response. The example of Figure 3 will give approximately 100MHz flat bandwidth using the 0.16pF feedback compensation capacitor. This bandwidth will easily support an OC-3 receiver with exceptional sensitivity. If the total output noise is bandlimited to a frequency less than the feedback pole frequency, a very simple expression for the equivalent input noise current can be derived as: i EQ = i 2 + N (e N 2 πC D f ) 4 kT  e N  + + 3 RF  RF  2 2 Where: iEQ = Equivalent input noise current if the output noise is bandlimited to f < 1/(2πRFCD) iN = Input current noise for the op amp inverting input eN = Input voltage noise for the op amp CD = Total Inverting Node Capacitance f = Bandlimiting frequency in Hz (usually a post filter prior to further signal processing) +5V Supply Decoupling Not Shown 100pF 0.1µF 12kΩ OPA687 –5V λ 1pF Photodiode –VB RF 12kΩ CF 0.16pF FIGURE 3. Wideband, High Sensitivity, OC-3 Transimpedance Amplifier. To achieve a maximally flat 2nd-order Butterworth frequency response, the feedback pole should be set to: 1/(2πRFCF) = √(GBP/(4πRFCD)) Adding the common-mode and differential-mode input capacitance (1.2 + 2.5)pF to the 1pF diode source capacitance of Figure 3 (CD), and targeting a 12kΩ transimpedance gain using the 3600MHz GBP for the OPA687, will require a feedback pole set to 71MHz to get a maximum bandwidth design. This will require a total feedback capacitance of 0.16pF. Using this maximum bandwidth, maximally flat frequency response target will give an approximate –3dB bandwidth set by: f–3dB = √(GBP/2πRFCD)Hz Evaluating this expression up to the feedback pole frequency at 71MHz for the circuit of Figure 3, gives an equivalent input noise current of 3.0pA/√Hz. This is somewhat higher than the 2.5pA/√Hz for just the op amp itself. This total equivalent input current noise is being slightly increased by the last term in the equivalent input noise expression. It is essential in this case to use a low voltage noise op amp. For example, if a slightly higher input noise voltage, but otherwise identical, op amp were used instead of the OPA687 in this application (say 2.0nV/√Hz), the total input-referred current noise would increase to 4.0pA/√Hz. Low input voltage noise is required for the best sensitivity in these wideband transimpedance applications. This is often unspecified for dedicated transimpedance amplifiers with a total output noise for a specified source capacitance given instead. It is the relatively high input voltage noise for those components that cause higher than expected output noise if the source capacitance is higher than expected. LOW GAIN COMPENSATION FOR IMPROVED SFDR A new external compensation technique may be used at low signal gains to retain the full slew rate and noise benefits of the OPA687, while maintaining the increased loop gain and the associated improvement in distortion offered by the decompensated architecture. This technique shapes the loop gain for good stability while giving an easily controlled second-order low pass frequency response. This technique was used for the circuit on the front page of the data sheet in a differential configuration to achieve extremely high SFDR through high frequencies. That circuit is set up for a differential gain of 8.5V/V from a differential input signal to the output. Using the transformer shown will improve the noise figure and translate from a single to a differential ® 9 OPA687 signal. If the source is differential already, it may be connected through blocking capacitors into the gain setting resistors. To set the compensation capacitors for this circuit (CS and CF), consider the 1/2 circuit of Figure 4 where the 50Ω source is reflected through the 1:2 transformer and then cut in 1/2 and grounded to give a total impedance to AC ground (for the circuit on the front page of this data sheet) equal to the 200Ω. Considering only the noise gain (this is the same as the noninverting signal gain) for the circuit of Figure 4, the low frequency noise gain, (NG1) will be set by the resistor ratios while the high frequency noise gain (NG2) will be set by the capacitor ratios. The capacitor values set both the transition frequencies and the high frequency noise gain. If the high frequency noise gain, determined by NG2 = 1 + CS/CF, is set to a value greater than the recommended minimum stable gain for the op amp, and the noise gain pole, set by 1/RFCF, is placed correctly, a very well-controlled, second-order low pass frequency response will result. Physically, this Z0 (4.1MHz for the values shown above) is set by 1/(2π • RF(CF + CS)) and is the frequency at which the rising portion of the noise gain would intersect unity gain if projected back to 0dB gain. The actual zero in the noise gain occurs at NG1 • Z0 and the pole in the noise gain occurs at NG2 • Z0. Since GBP is expressed in Hz, multiply Z0 by 2π and use this to get CF by solving: CF = 1 (= 1.90pF) 2π • R F Z O NG 2 Finally, since CS and CF set the high frequency noise gain, determine CS by [Using NG2 = 24]: C S = ( NG 2 – 1) C F (= 43.8pF) The resulting closed-loop bandwidth will be approximately equal to: f –3 dB ≅ Z O GBP (= 121MHz) +5V OPA687 RG 200Ω VI CS 44pF –5V CF 1.9pF RF 850Ω VO For the values shown in Figure 4, the f –3dB will be approximately 121MHz. This is less than that predicted by simply dividing the GBP product by NG 1. The compensation network controls the bandwidth to a lower value while providing the full slew rate at the output and an exceptional distortion performance due to increased loop gain at frequencies below NG1 • Z0. The capacitor values shown in Figure 4 are calculated for NG1 = 5.25 and NG 2 = 24 with no adjustment for parasitics. The full circuit on the front page of this datasheet shows the capacitors adjusted for parasitics. The front page of this data sheet shows the measured 2-tone, 3rd-order distortion for just the amplifier portion of the circuit. The upper curve is for a total 2-tone envelope of 4Vp-p, requiring two tones, each at 2Vp-p across the OPA687 outputs. The lower curve is for a 2Vp-p envelope requiring each tone to be 1Vp-p. The basic measurement dynamic range for the two close-in spurious tones is approximately 85dBc. The 4Vp-p test does not show measurable 3rd-order spurious until 25MHz ,while the 2Vp-p is unmeasurable up to 40MHz center frequency. Two-tone, 2nd-order intermodulation distortion was unmeasurable for the circuit on the front page of this data sheet. FIGURE 4. Broadband Low Inverting Gain External Compensation. To choose the values for both CS and CF, two parameters and only three equations need to be solved. The first parameter is the target high frequency noise gain NG2, which should be greater than the minimum stable gain for the OPA687. Here, a target NG2 of 24 will be used. The second parameter is the desired low frequency signal gain, which also sets the low frequency noise gain NG1. To simplify this discussion, we will target a maximally flat second-order low pass Butterworth frequency response (Q = 0.707). The signal gain of –4.25 shown in Figure 4 will set the low frequency noise gain to NG1 = 1 + RF/RG (= 5.25 in this example). Then, using only these two gains and the GBP for the OPA687 (3600MHz), the key frequency in the compensation can be determined as: ZO = GBP NG12  NG1  NG1   1 –   – 1– 2 NG 2  NG 2     ® OPA687 10 LOW NOISE FIGURE, HIGH DYNAMIC RANGE AMPLIFIER The low input noise voltage of the OPA687 and its very high 2-tone intercept can be used to good advantage as a fixedgain IF amplifier. While input noise figures in the 10dB range (for a matched 50Ω input) are easily achieved with just the OPA687, Figure 5 shows a technique to reduce the noise figure even further while providing a broadband, high gain IF amplifier stage using two stages of the OPA687. This circuit uses two stages of forward gain with an overall feedback loop to set the input impedance match. The input transformer provides both a noiseless voltage gain and a signal inversion to retain an overall non-inverting signal path from PI to PO—since the 2nd amplifier stage is inverting to provide the correct feedback polarity through the 6.19kΩ resistor. To achieve a 50Ω input match at the primary of the 1:2 transformer, the secondary must see a 200Ω load impedance. At higher frequencies, the match is provided by the 200Ω resistor in series with 10pF. At lower signal frequencies (f < 80MHz), the input match is set by the feedback through the 6.19kΩ resistor. The low noise figure (5dB) for this circuit is achieved by using the transformer, the low voltage noise OPA687, and the input match set by feedback. The first stage amplifier provides a gain of +15. The very high SFDR is provided by operating the output stage a low signal gain of –2 and using the inverting compensation to hold it stable. Depending on the load that is driven, this circuit can give a 2-tone SFDR that exceeds 90dB through 30MHz. Besides offering a very high dynamic range, this circuit improves on standard IF amplifiers by offering a precisely controlled gain and a very flexible output load driving capability. DESIGN-IN TOOLS DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA687 in its two package styles. Both of these are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in the table below. BOARD PART NUMBER DEM-OPA68xU DEM-OPA6xxN LITERATURE REQUEST NUMBER MKT-351 MKT-348 PRODUCT OPA687U OPA687N PACKAGE 8-Pin SO-8 6-Lead SOT23-6 Contact the Burr-Brown applications support line to request any of these boards. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA687 is available through either the Burr-Brown Internet web page (http://www.burr-brown.com) or as one model on a disk from the Burr-Brown Applications department (1-800-548-6132). The Applications department is also available for design assistance at this number. These models do a good job of predicting smallsignal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. 6.19kΩ Input match set by this feedback path 50Ω Source PI 5dB Noise Figure 750Ω OPA687 200Ω 10pF 420Ω 46pF OPA687 PO 1:2 1.5kΩ 1.6pF 30.1Ω Overall Gain PO PI = 35.6dB FIGURE 5. Very High Dynamic Range High Gain Amplifier. ® 11 OPA687 OPERATING SUGGESTIONS SETTING RESISTOR VALUES TO MINIMIZE NOISE The OPA687 provides a very low input noise voltage while requiring a low 18.5mA of quiescent current. To take full advantage of this low input noise, careful attention to the other possible noise contributors is required. Figure 6 shows the op amp noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. tion 2 for the circuit of Figure 1 will give a total equivalent input noise of 1.4nV/√Hz. This is slightly increased from the 0.95nV/√Hz for the op amp itself due to the contribution of the resistor and bias current noise terms. FREQUENCY RESPONSE CONTROL Voltage feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the specifications. Ideally, dividing GBP by the non-inverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factors), most high-speed amplifiers will exhibit a more complex response with lower phase margin. The OPA687 is compensated to give a maximally flat 2nd-order Butterworth closed-loop response at a non-inverting gain of +20 (Figure 1). This results in a typical gain of +20 bandwidth of 290MHz, far exceeding that predicted by dividing the 3600MHz GBP by 20. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +50, the OPA687 will very nearly match the 72MHz bandwidth predicted using the simple formula and the typical GBP of 3600MHz. Inverting operation offers some interesting opportunities to increase the available gain bandwidth product. When the source impedance is matched by the gain resistor (Figure 2), the signal gain is (1 + RF/RG) while the noise gain for bandwidth purposes is (1 + RF/2RG). This cuts the noise gain almost in half, increasing the minimum stable gain for inverting operation under these condition to –20 and the equivalent gain bandwidth product to 7.2GHz. DRIVING CAPACITIVE LOADS One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter, including additional external capacitance which may be recommended to improve A/D linearity. A high-speed, high open-loop gain amplifier like the OPA687 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. 12 ENI RS OPA687 IBN EO ERS √4kTRS RF √4kTRF 4kT = 1.6E –20J at 290°K 4kT RG RG IBI FIGURE 6. Op Amp Noise Analysis Model. The total output spot-noise voltage can be computed as the square root of the squared contributing terms to the output noise voltage. This computation is adding all the contributing noise powers at the output by superposition, then taking the square root to get back to a spot-noise voltage. Equation 1 shows the general form for this output noise voltage using the terms shown in Figure 6. Equation 1 EO = (E 2 NI + (I BN R S ) + 4 kTR S NG 2 + (I BI R F ) + 4 kTR F NG 2 2 ) Dividing this expression by the noise gain (NG = 1 + RF/RG) will give the equivalent input-referred, spot-noise voltage at the non-inverting input as shown in Equation 2. Equation 2 I R 2 4 kTR F 2 E N = E NI 2 + ( I BN R S ) + 4 kTR S +  BI F  +  NG  NG Putting high resistor values into Equation 2 can quickly dominate the total equivalent input-referred noise. A source impedance on the non-inverting input of 56Ω will add a Johnson voltage noise term equal to just that for the amplifier itself. Holding the gain and source resistors low (as was used in the Typical Performance Curves) will minimize the resistor noise contribution in Equation 2. Evaluating Equa® OPA687 The Typical Performance Curves show the recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA687. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA687 output pin (see Board Layout Guidelines). The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For the OPA687 operating in a gain of +20, the frequency response at the output pin is very flat to begin with, allowing relatively small values of RS to be used for low capacitive loads. As the signal gain is increased, the unloaded phase margin will also increase. Driving capacitive loads at higher gains will require lower RS values than shown for a gain of +20. DISTORTION PERFORMANCE The OPA687 is capable of delivering an exceptionally low distortion signal at high frequencies over a wide range of gains. The distortion plots in the Typical Performance Curves show the typical distortion under a wide variety of conditions. Most of these plots are limited to 110dB dynamic range. The OPA687’s distortion driving a 500Ω load does not rise above –90dBc until either the signal level exceeds 3.0V and/or the fundamental frequency exceeds 5MHz. Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd harmonic will dominate the distortion with negligible 3rd harmonic component. Focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network, in the non-inverting configuration this is sum of RF + RG, while in the inverting configuration this is just RF (Figure 2). Increasing output voltage swing increases harmonic distortion directly. A 6dB increase in output swing will generally increase the 2nd harmonic 12dB and the 3rd harmonic 18dB. Increasing the signal gain will also increase the 2nd harmonic distortion. Again, a 6dB increase in gain will increase the 2nd and 3rd harmonic by about 6dB even with a constant output power and frequency. And finally, the distortion increases as the fundamental frequency increases due to the roll-off in the loop gain with frequency. Conversely, the distortion will improve going to lower frequencies down to the dominant open-loop pole at approximately 200kHz. In most applications, the 2nd harmonic will set the limit to dynamic range. Even order non-linearities arise from slight imbalances between the positive and negative halves of an output sinusoid. These imbalanced non-linearities arise from such mechanisms as voltage dependent base-collector capacitances and imbalanced source impedances looking out of the two amplifier power pins. Once a circuit and board layout has been determined, these imbalances can typically be nulled out by adjusting the DC operating point for the signal. An example DC tune is shown in Figure 7. This circuit has a DC-coupled inverting signal path to the output pin that provides gain for a small DC offsetting signal brought into the non-inverting input pin. The output is ACcoupled to block off this DC operating point from interacting with the next stage. +5V 5kΩ 20Ω 10kΩ 0.1µF 5kΩ +VS Supply Decoupling Not Shown OPA687 VO –5V –VS RG RF VI FIGURE 7. DC Adjustment for 2nd Harmonic Distortion. For a 1Vp-p output swing in the 10MHz to 20MHz region, an output DC voltage in the ±1.5V range will null the 2nd harmonic distortion. Tests into a 200Ω converter input load have shown > 20dB decrease in the 2nd harmonic using this technique. Once the required voltage is found for a particular board, circuit, and signal requirement, that voltage is very repeatable from part to part and may be set permanently on the non-inverting input. Minimal degradation from this improved 2nd harmonic distortion over temperature will be observed. An alternative means to eliminate the 2nd harmonic distortion is to operate two OPA687s differentially as shown on the front page of the data sheet. Both single-tone and 2-tone even order harmonic distortions for this differential configuration are essentially unmeasureable through 30MHz for a good layout. The OPA687 has an extremely low 3rd-order harmonic distortion. This also gives a high 2-tone, 3rd-order intermodulation intercept as shown in the Typical Performance Curves. This intercept curve is defined at the 50Ω load when driven through a 50Ω matching resistor to allow direct comparisons to RF MMIC devices. This network attenuates the voltage swing from the output pin to the load by 6dB. If the OPA687 drives directly into the input of a high impedance device, such as an ADC, this 6dB attenuation is not taken. Under these conditions, the intercept will increase by a minimum 6dBm. The intercept is used to ® 13 OPA687 predict the intermodulation spurious for two closely-spaced frequencies. If the two test frequencies, f1 and f2, are specified in terms of average and delta frequency, fO = (f1 + f2)/2 and ∆f = |f2 – f1|/2, the two, 3-order, close-in spurious tones will appear at fO ±3 • ∆f. The difference between two equal test-tone power levels and these intermodulation spurious power levels is given by (dBc = 2 • (IM3 – PO)) where IM3 is the intercept taken from the Typical Performance Curve and PO is the power level in dBm at the 50Ω load for one of the two, closely-spaced test frequencies. For instance, at 20MHz, the OPA687—at a gain of +20, has an intercept of 43dBm at a matched 50Ω load. If the full envelope of the two frequencies needs to be 2Vp-p, this requires each tone to be 4dBm. The 3rd-order intermodulation spurious tones will then be 2 • (43 – 4)=78dBc below the test-tone power level (–74dBm). If this same 2Vp-p, 2-tone envelope were delivered directly into the input of an ADC without the matching loss or the loading of the 50Ω network, the intercept would increase to at least 49dBm. With the same signal and gain conditions, but now driving directly into a light load, the spurious tones will then be at least 2 • (49 – 4) = 90dBc below the 4dBm test-tone power levels centered on 20MHz. Tests have shown that, in reality, they are much lower due to the lighter loading presented by most ADCs. DC ACCURACY AND OFFSET CONTROL The OPA687 can provide excellent DC signal accuracy due to its high open-loop gain, high common-mode rejection, high power supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of its low ±1.0mV input offset voltage, careful attention to input bias current cancellation is also required. The low noise input stage for the OPA687 has a relatively high input bias current (20µA typ into the pins) but with a very close match between the two input currents—typically ±200nA input offset current. The total output offset voltage may be considerably reduced by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 1 would be to insert a 12.1Ω series resistor into the non-inverting input from the 50Ω terminating resistor. When the 50Ω source resistor is DC-coupled, this will increase the source impedance for the non-inverting input bias current to 37.1Ω. Since this is now equal to the impedance looking out of the inverting input (RF || RG) for Figure 1, the circuit will cancel the gains for the bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using the 750Ω feedback resistor, this output error will now be less than ±1.8µA • 750Ω = ±1.4mV over the full temperature range for the circuit of Figure 1 with a 12.1Ω resistor added as described. The output DC offset will then be dominated by the input offset voltage multiplied by the signal gain. For the circuit of Figure 1, this will give a worst-case output DC offset of ±1.6mV • 20 = ±32mV over the full temperature range. A fine-scale output offset null, or DC operating point adjustment is sometimes required. Numerous techniques are available for introducing a DC offset control into an op amp circuit. Most of these techniques eventually reduce to setting up a DC current through the feedback resistor. One key consideration to selecting a technique is to insure that it has a minimal impact on the desired signal path frequency response. If the signal path is intended to be non-inverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the non-inverting input can be considered. For a DC-coupled inverting input signal, this DC offset signal will set up a DC current back into the source that must be considered. An offset adjustment placed on the inverting op amp input can also change the noise gain and frequency response flatness. Figure 8 shows one example of an offset adjustment for a DC-coupled signal path that will have minimum impact on the signal frequency response. In this case, the input is brought into an inverting gain resistor with the DC adjustment and additional current summed into the inverting node. The resistor values setting this offset adjustment are much larger than the signal path resistors. This will insure that this adjustment has minimal impact on the loop gain and hence, the frequency response. +5V Supply Decoupling Not Shown 0.1µF 95.3Ω OPA687 VO –5V +5V VI ±250mV Output Adjustment RG 50Ω 5kΩ RF 2kΩ 20kΩ 10kΩ 0.1µF 5kΩ VO VI =– RF RG = –40 –5V FIGURE 8. DC-Coupled, Inverting Gain of –40, with Offset Adjustment. ® OPA687 14 DISABLE OPERATION The OPA687 provides an optional disable feature that may be used to reduce system power. If the DIS control pin is left unconnected, the OPA687 will operate normally. To disable, the control pin must be asserted low. Figure 9 shows a simplified internal circuit for the disable control feature. +VS Note that it is the power in the output stage and not in the load that determines internal power dissipation. As an absolute worst-case example, compute the maximum TJ using an OPA687N (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 100Ω load. PD = 10V (20.5mA) + 52/(4 • (100Ω || 789Ω)) = 275mW Maximum TJ = +85°C + (0.28W • 150°C/W) = 127°C All actual applications will operate at a lower junction temperature than the 127°C computed above. Compute your actual output stage power to get an accurate estimate of maximum junction temperature, or use the results shown here as an absolute maximum. 15kΩ Q1 BOARD LAYOUT 25kΩ VDIS IS Control 110kΩ –VS Achieving optimum performance with a high frequency amplifier like the OPA687 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the non-inverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA687. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as non-inverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feed® FIGURE 9. Simplified Disabled Control Circuit. In normal operation, base current to Q1 is provided through the 110kΩ resistor while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As VDIS is pulled low, additional current is pulled through the 15kΩ resistor, eventually turning on these two diodes (≈ 100µA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-based voltage of Q1 at approximately zero volts. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 9. THERMAL ANALYSIS The OPA687 will not require heatsinking or airflow in most applications. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 • RL) where RL includes feedback network loading. This is the absolute highest power that can be dissipated for a given RL. All actual applications will dissipate less power in the output stage. 15 OPA687 back resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 2.0kΩ, this parasitic capacitance can add a pole and/or a zero below 400MHz that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. It has been suggested here that a good starting point for design would be set the RG be set to 39.2Ω for non-inverting applications. Doing this will automatically keep the resistor noise terms low, and minimize the effect of their parasitic capacitance. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 4pF) may not need an RS since the OPA687 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic cap. loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doublyterminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA687 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high speed part like the OPA687 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA687 onto the board. INPUT AND ESD PROTECTION The OPA687 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies as shown in Figure 10. +V CC External Pin Internal Circuitry –V CC FIGURE 10. Internal ESD Protection. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA687), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. ® OPA687 16