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PCA9517
SCPS157E – DECEMBER 2007 – REVISED JUNE 2014
PCA9517 Level-Translating I2C Bus Repeater
Not Recommended for New Designs
1 Features
2 Description
•
•
•
This dual bidirectional I2C buffer is operational at
2.7 V to 5.5 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
Two-Channel Bidirectional Buffer
I2C Bus and SMBus Compatible
Operating Supply Voltage Range of 0.9 V to 5.5 V
on A Side
Operating Supply Voltage Range of 2.7 V to 5.5 V
on B Side
Voltage-Level Translation From 0.9 V to 5.5 V and
2.7 V to 5.5 V
Footprint and Function Replacement for
PCA9515A
Active-High Repeater-Enable Input
Open-Drain I2C I/O
5.5-V Tolerant I2C and Enable Input Support
Mixed-Mode Signal Operation
Lockup-Free Operation
Accommodates Standard Mode and Fast Mode
I2C Devices and Multiple Masters
Powered-Off High-Impedance I2C Pins
400-kHz Fast I2C Bus
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The PCA9517 is a BiCMOS integrated circuit
intended for I2C bus and SMBus systems. It can also
provide bidirectional voltage-level translation (uptranslation/down-translation) between low voltages
(down to 0.9 V) and higher voltages (2.7 V to 5.5 V)
in mixed-mode applications. This device enables I2C
and similar bus systems to be extended, without
degradation of performance even during level shifting.
The PCA9517 buffers both the serial data (SDA) and
the serial clock (SCL) signals on the I2C bus, thus
allowing two buses of 400-pF bus capacitance to be
connected in an I2C application. This device can also
be used to isolate two halves of a bus for voltage and
capacitance.
The PCA9517 has two types of drivers—A-side
drivers and B-side drivers. All inputs and I/Os are
overvoltage tolerant to 5.5 V, even when the device is
unpowered (VCCB and/or VCCA = 0 V).
The PCA9517 doesnot support clock stretching and
arbitration across the repeater.
Device Information(1)
PART NUMBER
PCA9517
1
8
VCCB
SCLA
2
7
SCLB
SDAA
3
6
SDAB
GND
4
5
EN
BODY SIZE (NOM)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
D PACKAGE
(TOP VIEW)
VCCA
PACKAGE
SOIC (8)
DGK PACKAGE
(TOP VIEW)
VCCA
SCLA
SDAA
GND
1
2
3
4
8
7
6
5
VCCB
SCLB
SDAB
EN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Not Recommended for New Designs
PCA9517
SCPS157E – DECEMBER 2007 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
2
3
4
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
6
6
7
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
I2C Interface Timing Requirements...........................
7
8
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Functional Block Diagram ......................................... 9
8.2 Feature Description................................................. 10
8.3 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 12
9.1 Typical Application ................................................. 12
10 Device and Documentation Support ................. 15
10.1 Trademarks ........................................................... 15
10.2 Electrostatic Discharge Caution ............................ 15
10.3 Glossary ................................................................ 15
11 Mechanical, Packaging, and Orderable
Information ........................................................... 15
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2012) to Revision E
Page
•
Added Clock Stretching Errata section. ............................................................................................................................... 10
•
Added Load Dependent Undershoot Errata section............................................................................................................. 10
•
Added Glitch/Noise Susceptibility Errata section.................................................................................................................. 11
•
Added Load Susceptibility Errata section. ............................................................................................................................ 11
Changes from Revision B (May 2010) to Revision C
•
2
Page
Deleted all references to arbitration and clock stretching support. This does not effect min/max specifications. ................ 1
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SCPS157E – DECEMBER 2007 – REVISED JUNE 2014
4 Description (Continued)
The B-side drivers operate from 2.7 V to 5.5 V and behave like the drivers in the PCA9515A. The output low
level for this internal buffer is approximately 0.5 V, but the input voltage must be 70 mV or more below the output
low level when the output internally is driven low. The higher-voltage low signal is called a buffered low. When
the B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a
lockup condition from occurring when the input low condition is released.
This type of design on the B side prevents it from being used in series with the PCA9515A and another
PCA9517 (B side). This is because these devices do not recognize buffered low signals as a valid low and do
not propagate it as a buffered low again.
The A-side drivers operate from 0.9 V to 5.5 V and drive more current. They do not require the buffered low
feature (or the static offset voltage). This means that a low signal on the B side translates to a nearly 0-V low on
the A side, which accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the
A side drives a hard low, and the input level is set at 0.3 VCCA to accommodate the need for a lower low level in
systems where the low-voltage-side supply voltage is as low as 0.9 V.
The A side of two or more PCA9517s can be connected together to allow a star topography, with the A side on
the common bus. Also, the A side can be connected directly to any other buffer with static- or dynamic-offset
voltage. Multiple PCA9517s can be connected in series, A side to B side, with no buildup in offset voltage and
with only time-of-flight delays to consider.
The PCA9517 drivers are enabled when VCCA is above 0.8 V and VCCB is above 2.5 V.
The PCA9517 has an active-high enable (EN) input with an internal pullup to VCCB, which allows the user to
select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It
should never change state during an I2C operation, because disabling during a bus operation hangs the bus, and
enabling part way through a bus cycle could confuse the I2C parts being enabled. The EN input should change
state only when the global bus and repeater port are in an idle state, to prevent system failures.
The PCA9517 includes a power-up circuit that keeps the output drivers turned off until VCCB is above 2.5 V and
the VCCA is above 0.8 V. VCCB and VCCA can be applied in any sequence at power up. After power up and with
the EN high, a low level on the A side (below 0.3 VCCA) turns the corresponding B-side driver (either SDA or
SCL) on and drives the B side down to approximately 0.5 V. When the A side rises above 0.3 VCCA, the B-side
pulldown driver is turned off and the external pullup resistor pulls the pin high. When the B side falls first and
goes below 0.3 VCCB, the A-side driver is turned on and the A side pulls down to 0 V. The B-side pulldown is not
enabled unless the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5 V, the Aside driver turns off when the B-side voltage is above 0.7 VCCB. If the B-side low voltage goes below 0.4 V, the Bside pulldown driver is enabled, and the B side is able to rise to only 0.5 V until the A side rises above 0.3 VCCA.
Then the B side continues to rise, being pulled up by the external pullup resistor. VCCA is only used to provide the
0.3 VCCA reference to the A-side input comparators and for the power-good-detect circuit. The PCA9517 logic
and all I/Os are powered by the VCCB pin.
As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered
bus. The PCA9517 has standard open-collector configuration of the I2C bus. The size of these pullup resistors
depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to
work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices
only specify 3 mA in a generic I2C system, where Standard mode devices and multiple masters are possible.
Under certain conditions, higher termination currents can be used.
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5 Pin Configuration and Functions
D PACKAGE
(TOP VIEW)
VCCA
1
8
VCCB
SCLA
2
7
SCLB
SDAA
3
6
SDAB
GND
4
5
EN
DGK PACKAGE
(TOP VIEW)
VCCA
SCLA
SDAA
GND
8
7
6
5
1
2
3
4
VCCB
SCLB
SDAB
EN
Pin Functions
PIN
NAME
NO.
DESCRIPTION
VCCA
1
A-side supply voltage (0.9 V to 5.5 V)
SCLA
2
Serial clock bus, A side. Connect to VCCA through a pullup resistor.
SDAA
3
Serial data bus, A side. Connect to VCCA through a pullup resistor.
GND
4
Supply ground
EN
5
Active-high repeater enable input
SDAB
6
Serial data bus, B side. Connect to VCCB through a pullup resistor.
SCLB
7
Serial clock bus, B side. Connect to VCCB through a pullup resistor.
VCCB
8
B-side and device supply voltage (2.7 V to 5.5 V)
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCB
Supply voltage range
–0.5
7
V
VCCA
Supply voltage range
–0.5
7
V
VI
Enable input voltage range (2)
–0.5
7
V
7
V
2
(2)
VI/O
I C bus voltage range
IIK
Input clamp current
VI < 0
–50
IOK
Output clamp current
VO < 0
–50
Continuous output current
IO
(1)
(2)
–0.5
Continuous current through VCC or GND
mA
±50
mA
±100
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
4
Electrostatic discharge
MAX
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
UNIT
°C
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCPS157E – DECEMBER 2007 – REVISED JUNE 2014
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCCA
Supply voltage, A-side bus
VCCB
Supply voltage, B-side bus
VIH
MIN
MAX
(1)
5.5
V
2.7
5.5
V
SDAA, SCLA
0.7 × VCCA
5.5
SDAB, SCLB
0.7 × VCCB
5.5
EN
0.7 × VCCB
5.5
0.9
High-level input voltage
SDAA, SCLA
VIL
Low-level input voltage
Low-level output current
TA
Operating free-air temperature
(1)
(2)
V
–0.5 0.28 × VCCA
SDAB, SCLB
EN
IOL
UNIT
–0.5 (2)
0.3 × VCCB
–0.5
0.3 × VCCB
VCCB = 2.7 V
6
VCCB = 3 V
6
–40
V
mA
85
°C
Low-level supply voltage
VIL specification is for the first low level seen by the SDAB and SCLB lines. VILc is for the second and subsequent low levels seen by the
SDAB and SCLB lines.
6.4 Thermal Information
PCA9517
THERMAL METRIC (1)
RθJA
(1)
Junction-to-ambient thermal resistance
D
DGK
8 PINS
8 PINS
97
172
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
VCCB = 2.7 V to 5.5 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input clamp voltage
Low-level output
voltage
VOL
VCCB
II = –18 mA
2.7 V to 5.5 V
SDAB, SCLB
IOL = 100 μA or 6 mA,
VILA = VILB = 0 V
2.7 V to 5.5 V
SDAA, SCLA
IOL = 6 mA
VOL – VILc
Low-level input voltage
below low-level output
voltage
SDAB, SCLB
2.7 V to 5.5 V
VILC
SDA and SCL low-level
SDAB, SCLB
input voltage contention
2.7 V to 5.5 V
ICC
Quiescent supply current for VCCA
5.5 V
In contention,
SDAA = SCLA = GND and
SDAB = SCLB = GND
SDAB, SCLB
II
Input leakage current
SDAA, SCLA
EN
IOH
High-level output
leakage current
CI
Input capacitance
SDAB, SCLB
SDAA, SCLA
EN
CIO
Input/output
capacitance
SCLA, SCLB
MAX
UNIT
–1.2
V
0.52
0.7
0.1
0.2
70
–0.5
0.4
1.5
4
1.5
5
1.5
5
VI = VCCB
±1
VI = 0.2 V
10
VI = VCCB
VI = 0.2 V
±1
2.7 V to 5.5 V
10
VI = VCCB
mV
mA
mA
μA
±1
VI = 0.2 V
VO = 3.6 V
V
V
1
Both channels low,
SDAA = SCLA = GND and
SDAB = SCLB = open, or
SDAA = SCLA = open and
SDAB = SCLB = GND
Quiescent supply current
0.45
TYP
Both channels low,
SDAA = SCLA = GND and
SDAB = SCLB = open, or
SDAA = SCLA = open and
SDAB = SCLB = GND
Both channels high,
SDAA = SCLA = VCCA and
SDAB = SCLB = VCCB and
EN = VCCB
ICC
MIN
–10
10
2.7 V to 5.5 V
VI = 3 V or 0 V
VI = 3 V or 0 V
SDAA, SDAB VI = 3 V or 0 V
–30
10
3.3 V
6
7
3.3 V
6
9
0V
6
8
3.3 V
6
9
0V
6
8
μA
pF
pF
6.6 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
tsu
Setup time, EN high before Start condition (1)
100
ns
th
Hold time, EN high after Stop condition (1)
100
ns
(1)
6
EN should change state only when the global bus and the repeater port are in an idle state.
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6.7 I2C Interface Timing Requirements
VCCB = 2.7 V to 5.5 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
tPLZ
Propagation delay
FROM
(INPUT)
TO
(OUTPUT)
SDAB, SCLB (2)
(see Figure 4)
SDAA, SCLA (2)
(see Figure 4)
(3)
(3)
SDAA, SCLA
(see Figure 3)
SDAB, SCLB
tPZL
tTLH
SDAA, SCLA
Propagation delay
Transition time
SDAA, SCLA (3)
(see Figure 3)
SDAB, SCLB (3)
(see Figure 3)
20%
80%
B side to A side
(see Figure 3)
A side to B side
(see Figure 2)
Transition time
80%
20%
(3)
(4)
(5)
(6)
(7)
TYP (1) MAX UNIT
169
255
25
67
110
VCCA ≤ 2.7 V
(see Figure 2)
15
68 (4)
110
2.7 V ≤ VCCA ≤ 3 V
(see Figure 2)
20
79
130
VCCA ≥ 3 V
(see Figure 2)
10
103 (5)
300
45
118
230
1
6
30
20
31
170
VCCA ≤ 2.7 V
(see Figure 3)
1
3 (6)
105
2.7 V ≤ VCCA ≤ 3 V
(see Figure 2)
1
6
120
VCCA ≥ 3 V
(see Figure 3)
1
25 (7)
175
1
12
90
ns
ns
ns
A side to B side
(see Figure 2)
(1)
(2)
MIN
100
SDAB, SCLB
(see Figure 3)
B side to A side
tTHL
TEST CONDITIONS
ns
Typical values were measured with VCCA = VCCB = 2.7 V at TA = 25°C, unless otherwise noted.
The tPLH delay data from B to A side is measured at 0.5 V on the B side to 0.5 VCCA on the A side when VCCA is less than 2 V, and
1.5 V on the A side if VCCA is greater than 2 V.
The proportional delay data from A to B side is measured at 0.3 VCCA on the A side to 1.5 V on the B side.
Typical value measured with VCCA = 0.9 V at TA = 25°C
Typical value measured with VCCA = 5.5 V at TA = 25°C
Typical value measured with VCCA = 0.9 V at TA = 25°C
Typical value measured with VCCA = 5.5 V at TA = 25°C
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7 Parameter Measurement Information
VCC
VIN
RL
(see Note A)
VOUT
PULSE
GENERATOR
VCC
S1
DUT
GND
CL = 57 pF
(see Note C)
RT
(see Note B)
TEST
S1
tPLZ/tPZL
VCC
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
A.
RL = 167 Ω on the A side and 1.35 kΩ on the B side
B.
RT termination resistance should be equal to ZOUT of pulse generators.
C.
CL includes probe and jig capacitance.
D.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
slew rate ≥ 1 V/ns.
E.
The outputs are measured one at a time, with one transition per measurement.
F.
tPLH and tPHL are the same as tpd.
G.
tPLZ and tPHZ are the same as tdis.
H.
tPZL and tPZH are the same as ten.
Figure 1. Test Circuit
3V
INPUT
1.5 V
1.5 V
0.1 V
tPZL
tPLZ
1.2 V
80%
80%
OUTPUT
0.6 V
20%
0.6 V
20%
VOL
tTHL
tTLH
Figure 2. Waveform 1 – Propagation Delay and Transition Times for B Side to A Side
VCCA
VCCA
INPUT
0.3 VCCA
0.3 VCCA
tPZL
tPLZ
3V
80%
OUTPUT
1.5 V
20%
80%
1.5 V
20%
Figure 3. Waveform 2 – Propagation Delay and Transition Times for A Side to B Side
8
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Parameter Measurement Information (continued)
INPUT
SDAB, SCLB
0.5 V
50% is VCCA is less than 2 V
1.5 V if VCCA is greater than 2 V
OUTPUT
SCLA, SDAA
tPLH
Figure 4. Waveform 3
8 Detailed Description
8.1 Functional Block Diagram
VCCA
VCCB
1
8
6
3
SDAA
SDAB
7
2
SCLA
SCLB
VCCB
5
Pullup
Resistor
EN
4
GND
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8.2 Feature Description
8.2.1 Clock Stretching Errata
Description
Due to the static offset on the B-side and the possibility of an overshoot above 500mV during events like clock
stretching, the device should not be used with rise time accelerators on the B-side.
Rise time accelerator pulling SDAB high
after SDAA overshoots past 500mV
SDAA
SDAB
SCL
Figure 5. Waveform of Clock Stretching with Rise Time Accelerator on the Bus
System Impact
An incorrect logic state will be transferred to circuits, creating an I2C communication failure on the bus.
System Workaround
Usage of the TCA9517 is recommended.
There are two possible workarounds to avoid an I2C communication failure:
• Removing rise-time accelerators from the B-side bus
• Adding a larger capacitive load to the bus will limit the overshoot
8.2.2 Load Dependent Undershoot Errata
Description
There is a case in which a combination of weak pull-up resistance and light bus loading will cause
communication failure through the bus due to undershoot. During a low-to-high transition, when the B-side
releases from its 500mV VOL, an undershoot below VILC can occur. In this event, the A-side will recognize this
as a valid low coming from the B-side, causing the A-side to be pulled down by the buffer. The A-side being
improperly pulled down by the buffer will trigger the B-side to be pulled low. Since the B-side will be pulled to
500mV, this will not force the A-side to stay low. As the A-side begins transitioning high again, the issue will
repeat itself.
System Impact
An incorrect logic state will be transferred to circuits, creating an I2C communication failure on the bus.
System Workaround
Usage of the TCA9517 is recommended.
There are two possible workarounds to avoid an I2C communication failure:
• Removing rise-time accelerators from the B-side bus
• Adding a larger capacitive load to the bus will limit the overshoot
10
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Feature Description (continued)
8.2.3 Glitch/Noise Susceptibility Errata
Description
During the event of a glitch on the SDA/SCL line on one side of the buffer, this glitch can be propagated through
and widened by the device during transfer to the other side of the buffer
System Impact
The widened glitch can be recognized as a valid transmission logic, causing a communication failure on the I2C
bus
System Workaround
Usage of the TCA9517 is recommended.
Ensure glitch free SDA/SCL lines.
8.2.4 Load Susceptibility Errata
Description
There is a possibility of a race condition of the internal logic of the device that can arise due to bus loading.
Within a narrow window, dependent on the following parameters, the internal latch controlling the direction of
transfer is set in the wrong state after a falling edge on SCLA/SDAA
• Pull-up resistance
• Bus capacitance
• Temperature
This window location will shift based on the combination of these parameters, therefore cannot be bounded. The
typical bus capacitance window is observed to be ~2pF wide for a given pull-up resistance and at a given
temperature. The typical temperature window for a given pull-up resistance and bus capacitance is observed to
be ~0.8°C wide. This phenomenon can be exacerbated by noise/glitching on the bus.
System Impact
An incorrect logic state will be transferred through the device creating an I2C communication failure on the bus
(Figure 6). The bus has the potential to lock under certain external conditions.
SDAB
SDAB releasing improperly after a high-tolow transition on SDAA
SDAA
Figure 6. Load Susceptibility Failure Signature
System Workaround
Usage of the TCA9517 is recommended.
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8.3 Device Functional Modes
Table 1. Function Table
INPUT
EN
FUNCTION
L
Outputs disabled
H
SDAA = SDAB
SCLA = SCLB
9 Application and Implementation
9.1 Typical Application
A typical application is shown in Figure 7. In this example, the system master is running on a 3.3-V I2C bus, and
the slave is connected to a 1.2-V bus. Both buses run at 400 kHz. Master devices can be placed on either bus.
1.2 V
3.3 V
10 kW
BUS
MASTER
400 kHz
10 kW
VCCB
10 kW
VCCA
10 kW
SDA
SDAB
SDAA
SDA
SCL
SCLB SCLA
PCA9517
SCL
SLAVE
400 kHz
EN
BUS B
BUS A
Figure 7. Typical Application
12
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Typical Application (continued)
VCCA
10 kΩ
VCCB
10 kΩ
10 kΩ
10 kΩ
SDA
SDAA SDAB
SDA
SCL
SCLA SCLB
SCL
SLAVE
400 kHz
PCA9517
BUS
MASTER
EN
10 kΩ
10 kΩ
SDAA SDAB
SDA
SCLA SCLB
SCL
PCA9517
SLAVE
400 kHz
EN
10 kΩ
10 kΩ
SDAA SDAB
SDA
SCLA SCLB
SCL
PCA9517
EN
SLAVE
400 kHz
Figure 8. Typical Star Application
9.1.1 Design Requirements
The PCA9517 is 5-V tolerant, so it does not require any additional circuitry to translate between 0.9-V to 5.5-V
bus voltages and 2.7-V to 5.5-V bus voltages.
When the A side of the PCA9517 is pulled low by a driver on the I2C bus, a comparator detects the falling edge
when it goes below 0.3 VCCA and causes the internal driver on the B side to turn on, causing the B side to pull
down to about 0.5 V. When the B side of the PCA9517 falls, first a CMOS hysteresis-type input detects the
falling edge and causes the internal driver on the A side to turn on and pull the A-side pin down to ground. In
order to illustrate what would be seen in a typical application, refer to Figure 9 and Figure 10. If the bus master in
Figure 7 were to write to the slave through the PCA9517, waveforms shown in Figure 9 would be observed on
the A bus. This looks like a normal I2C transmission, except that the high level may be as low as 0.9 V, and the
turn on and turn off of the acknowledge signals are slightly delayed.
On the B-side bus of the PCA9517, the clock and data lines would have a positive offset from ground equal to
the VOL of the PCA9517. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which
is very close to ground in this example. At the end of the acknowledge, the level rises only to the low level set by
the driver in the PCA9517 for a short delay, while the A-bus side rises above 0.3 VCCA and then continues high.
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Typical Application (continued)
9.1.2 Detailed Design Procedure
Multiple PCA9517 A sides can be connected in a star configuration, allowing all nodes to communicate with each
other.
VCCB
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
SDA
SDAA SDAB
SDAA SDAB
SDAA SDAB
SDA
SCL
SCLA SCLB
SCLA SCLB
SCLA SCLB
SCL
PCA9517
EN
PCA9517
EN
PCA9517
EN
BUS
MASTER
SLAVE
400 kHz
Figure 9. Typical Series Application
Multiple PCA9517s can be connected in series as long as the A side is connected to the B side. I2C bus slave
devices can be connected to any of the bus segments. The number of devices that can be connected in series is
limited by repeater delay/time-of-flight considerations on the maximum bus speed requirements.
0.5 V/DIV
9th CLOCK PULSE — ACKNOWLEDGE
SCL
SDA
Figure 10. Bus A (0.9-V to 5.5-V Bus) Waveform
2 V/DIV
9th CLOCK PULSE — ACKNOWLEDGE
SCL
SDA
VOL OF PCA9517
VOL OF SLAVE
Figure 11. Bus B (2.7-V to 5.5-V Bus) Waveform
14
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10 Device and Documentation Support
10.1 Trademarks
All trademarks are the property of their respective owners.
10.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCA9517D
NRND
SOIC
D
8
75
Level-1-260C-UNLIM
-40 to 85
PD517
PCA9517DGKR
NRND
VSSOP
DGK
8
2500
RoHS & Green
RoHS & Green NIPDAU | NIPDAUAG
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(7EA, 7EE, 7EF)
PCA9517DGKRG4
NRND
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(7EA, 7EE, 7EF)
PCA9517DR
NRND
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD517
PCA9517P
NRND
PDIP
P
8
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of