PCA9538
PCA9538
SCPS126G – SEPTEMBER 2006 – REVISED MARCH
2021
SCPS126G – SEPTEMBER 2006 – REVISED MARCH 2021
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PCA9538 Remote 8-Bit I2C AND SMBus Low-power I/O Expander with Interrupt
Output, Reset, and Configuration Registers
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low standby current consumption of 1 μA max
I2C to parallel port expander
Open-drain active-low interrupt output
Active-low reset input
Operating power-supply voltage range of 2.3 V to
5.5 V
5-V Tolerant I/O ports
400-kHz Fast I2C bus
Two hardware address pins allow up to four
devices on the I2C/SMBus
Input and output configuration register
Polarity inversion register
Power-up with all channels configured as inputs
No glitch on power up
Noise filter on SCL/SDA inputs
Latched outputs with high-current drive maximum
capability for directly driving LEDs
Latch-up performance exceeds 100 mA Per JESD
78, class II
ESD protection exceeds JESD 22
– 2000-V Human-body model (A114-A)
– 200-V Machine model (A115-A)
– 1000-V Charged-device model (C101)
2 Description
The PCA9538 is an 8-bit I/O expander of general
purpose parallel input and output (I/O) expansion for
the two-line bidirectional I2C bus (or SMBus) protocol.
This device can operate with a power supply range
from 2.3 V to 5.5 V. This device supports both
100-kHz (Standard-mode) and 400-kHz (Fast-mode)
clock frequencies. This device, along with other I/O
expanders, provides a simple solution when additional
I/Os are needed for switches, sensors, push-buttons,
LEDs, fans, and so on.
The features of PCA9538 include an interrupt that
is generated on the INT pin whenever an input port
changes state. The A0 and A1 hardware selectable
address pins allow up to four PCA9538 devices on
the same I2C bus. This device can also be reset to its
default state by using the RESET feature or by cycling
the power supply to cause a power-on reset.
INT can be connected to the interrupt input of a
microcontroller. By sending an interrupt signal on this
line, the remote I/O can inform the microcontroller if
there is incoming data on its ports without having to
communicate via the I2C bus. Thus, the PCA9538 can
remain a simple slave device.
The device outputs (latched) have high-current drive
capability for directly driving LEDs. It has low current
consumption.
Two hardware pins (A0 and A1) are used to program
and vary the fixed I2C address and allow up to four
devices to share the same I2C bus or SMBus.
Device Information
PART NUMBER
PCA9538
(1)
INT
A0
A1
PACKAGE(1)
BODY SIZE (NOM)
SSOP (16)
6.20 mm × 5.30 mm
TVSOP (16)
3.60 mm × 4.40 mm
SOIC (16)
10.30 mm × 7.50 mm
TSSOP (16)
5.00 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
13
LP Filter
Interrupt Logic
1
2
P7-P0
SCL
SDA
14
15
Input Filter
I2C Bus Control
Shift Register
8 Bits
I/O Port
Write Pulse
RESET
VCC
GND
3
16
Power-On
Reset
Read Pulse
8
Block Diagram
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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SCPS126G – SEPTEMBER 2006 – REVISED MARCH 2021
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 ESD Ratings............................................................... 4
5.3 Recommended Operating Conditions.........................4
5.4 Thermal Information....................................................5
5.5 Electrical Characteristics.............................................5
5.6 I2C Interface Timing Requirements.............................7
5.7 RESET Timing Requirements..................................... 8
5.8 Switching Characteristics............................................8
5.9 Typical Characteristics................................................ 9
6 Parameter Measurement Information.......................... 11
7 Detailed Description......................................................15
7.1 Functional Block Diagram......................................... 15
7.2 Device Functional Modes..........................................16
7.3 Programming............................................................ 17
7.4 Register Maps...........................................................19
8 Application Information Disclaimer............................. 24
8.1 Application Information Disclaimer............................24
8.2 Typical Application.................................................... 24
9 Power Supply Recommendations................................26
9.1 Power-On Reset Requirements................................ 26
10 Device and Documentation Support..........................28
10.1 Receiving Notification of Documentation Updates..28
10.2 Support Resources................................................. 28
10.3 Trademarks............................................................. 28
10.4 Electrostatic Discharge Caution..............................28
10.5 Glossary..................................................................28
11 Mechanical, Packaging, and Orderable
Information.................................................................... 28
3 Revision History
Changes from Revision F (May 2014) to Revision G (March 2021)
Page
• Updated the Description and added the Block Diagram image.......................................................................... 1
• Deleted RGV and RGT packages from the Pin Configuration and Functions section........................................3
• Moved the "Storage temperature range" to the Absolute Maximum Ratings .................................................... 4
• Moved the "Package thermal impedance" to the Thermal Resistance Characteristic .......................................4
• Changed the VIH High-level input voltage (SDL, SDA) Max value From: 5.5 V To: VCC in the Recommended
Operating Conditions ......................................................................................................................................... 4
• Changed the VIH High-level input voltage (A0, A1, A2, P7–P0) MIN value From: 2 V To: 0.7 x VCC in the
Recommended Operating Conditions ................................................................................................................4
• Changed the VIL Low-level input voltage (A0, A1, A2, P7–P0) MAX value From: 0.8 V To: 0.3 x VCC in the
Recommended Operating Conditions ................................................................................................................4
• Added the Thermal Information table................................................................................................................. 5
• Changed the VPORR TYP value From: 1.5 V to: 1.2 Vand the MAX value From: 1.65 V To: 1.5 V in the
Electrical Characteristics ................................................................................................................................... 5
• Added the VPORF row in the Electrical Characteristics .......................................................................................5
• Changed the IOL (INT) row TYP value Fron: 10 mA to: 7 mA in the Electrical Characteristics ..........................5
• Changed the ICC Standby mode values in the Electrical Characteristics ...........................................................5
• Changed the ΔICC Additional current in standby mode (5.5 V) mAX value From: 1 mA To: 4 mA in the
Electrical Characteristics ................................................................................................................................... 5
• Added Note 4 to the Electrical Characteristics .................................................................................................. 5
• Changed the Typical Characteristics graphs...................................................................................................... 9
• Changed the Power Supply Recommendations .............................................................................................. 26
Changes from Revision E (September 2008) to Revision F (May 2014)
Page
• Added RESET Errata section........................................................................................................................... 16
• Added Interrupt Errata section .........................................................................................................................17
2
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4 Pin Configuration and Functions
A0
1
16
VCC
A1
2
15
SDA
RE SET
3
14
SCL
P0
4
13
INT
P1
5
12
P7
P2
6
11
P6
P3
7
10
P5
GND
8
9
P4
No t to scale
Figure 4-1. DBQ, DB, PW, DGV Package, 16-Pin, Top View
Table 4-1. Pin Functions
PIN
NAME
DESCRIPTION
NO.
A0
1
Address input. Connect directly to VCC or ground
A1
2
Address input. Connect directly to VCC or ground.
GND
8
Ground
INT
13
Interrupt output. Connect to VCC through a pullup resistor
P0
4
P-port input-output. Push-pull design structure
P1
5
P-port input-output. Push-pull design structure
P2
6
P-port input-output. Push-pull design structure
P3
7
P-port input-output. Push-pull design structure
P4
9
P-port input-output. Push-pull design structure
P5
10
P-port input-output. Push-pull design structure
P6
11
P-port input-output. Push-pull design structure
P7
12
P-port input-output. Push-pull design structure
RESET
3
Active-low reset input. Connect to VCC through a pullup resistor if no active connection is
used
SCL
14
Serial clock bus. Connect to VCC through a pullup resistor
SDA
15
Serial data bus. Connect to VCC through a pullup resistor
VCC
16
Supply voltage
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6
V
voltage(2)
–0.5
6
V
–0.5
6
V
VI
Input
VO
Output voltage(2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
–50
mA
ICC
Tstg
(1)
(2)
Continuous current through GND
–250
Continuous current through VCC
160
Storage temperature
–65
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
0
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
4
MIN
MAX
2.3
5.5
SCL, SDA
0.7 × VCC
VCC
A0, A1, RESET, P7–P0
0.7 × VCC
5.5
SCL, SDA
–0.5
0.3 × VCC
A0, A1, RESET, P7–P0
–0.5
0.3 × VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
UNIT
V
V
V
IOH
High-level output current
P7–P0
–10
mA
IOL
Low-level output current
P7–P0
25
mA
TA
Operating free-air temperature
85
°C
–40
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5.4 Thermal Information
PCA9538
THERMAL
RθJA
(1)
METRIC(1)
Junction-to-ambient thermal resistance
DB
(SSOP)
DBQ
(SSOP)
DGV
(TVSOP)
DW
(SOIC)
PW
(TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
113.2
90
86
46
122
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
5.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
VPORR
Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0
II = –18 mA
VPORF
Power-on reset voltage, VC7 falling VI = VCC or GND, IO = 0
VCC
MIN
2.3 V to 5.5 V
–1.2
0.75
2.3 V
IOH = –8 mA
VOH
P-port high-level output voltage(2)
IOH = –10 mA
SDA
VOL = 0.4 V
VOL = 0.5 V
IOL
P port(3)
VOL = 0.7 V
INT
II
SCL, SDA
A0, A1, RESET (4)
MAX
1.2
1.5
UNIT
V
1
V
V
1.8
3V
2.6
4.5 V
4.1
4.75 V
4.1
2.3 V
1.7
3V
2.5
4.5 V
TYP(1)
V
4
4.75 V
4
2.3 V to 5.5 V
3
8
2.3 V
8
10
3V
8
14
4.5 V
8
17
4.75 V
8
35
2.3 V
10
13
3V
10
19
4.5 V
10
24
4.75 V
10
45
VOL = 0.4 V
2.3 V to 5.5 V
3
7
VI = VCC or GND
2.3 V to 5.5 V
mA
±1
±1
μA
IIH
P port
VI = VCC
2.3 V to 5.5 V
1
μA
IIL
P port
VI = GND
2.3 V to 5.5 V
–1
μA
VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 400 kHz, no load
Operating mode
VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 100 kHz, no load
ICC
Standby mode
VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 0 kHz, no load
5.5 V
104
175
3.6 V
50
90
2.7 V
20
65
5.5 V
60
150
3.6 V
15
40
2.7 V
8
20
5.5 V
1.9
3.5
3.6 V
1.1
1.8
2.7 V
1
1.6
μA
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5.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ΔICC
Ci
Cio
(1)
(2)
(3)
(4)
6
Additional current in standby mode
SCL
SDA
P port
TEST CONDITIONS
One input at VCC – 0.6 V,
Other inputs at VCC or GND
All LED I/Os at VI = 4.3 V,
fscl = 0 kHz
VCC
MIN
TYP(1)
2.3 V to 5.5 V
MAX
UNIT
1.5
mA
5.5 V
4
VI = VCC or GND
2.3 V to 5.5 V
VIO = VCC or GND
2.3 V to 5.5 V
4
5
5.5
6.5
8
9.5
pF
pF
All typical values are at nominal supply voltage (2.5-, 3.3-, or 5-V VCC) and TA = 25°C.
The total current sourced by all I/Os must be limited to 85 mA.
Each I/O must be externally limited to a maximum of 25 mA, and the P port (P7–P0) must be limited to a maximum current of 200 mA.
RESET = VCC (held high) when all other input voltages, VI = GND.
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5.6 I2C Interface Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
MIN
MAX
UNIT
0
100
kHz
STANDARD MODE
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
tsdh
I2C serial-data hold time
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time
tbuf
I2C bus free time between Stop and Start
4.7
μs
tsts
I2C
4.7
μs
tsth
I2C Start or repeated Start condition hold
4
μs
tsps
I2C
4
μs
tvd(data)
Valid data time
SCL low to SDA output valid
300
ns
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
0.3
Cb
I2C bus capacitive load
clock high time
4
μs
4.7
μs
50
250
0
ns
1000
input fall time
10-pF to 400-pF bus
Start or repeated Start condition setup
Stop condition setup
ns
ns
ns
300
ns
300
ns
3.45
μs
400
ns
400
kHz
FAST MODE
fscl
I2C clock frequency
tsch
I2C clock high time
0.6
tscl
I2C
1.3
tsp
I2C spike time
tsds
I2C
tsdh
I2C serial-data hold time
ticr
I2C input rise time
20 + 0.1Cb
300
ns
ticf
I2C input fall time
20 + 0.1Cb
300
ns
tocf
I2C output fall time
20 + 0.1Cb
300
ns
tbuf
I2C bus free time between Stop and Start
tsts
I2C
tsth
I2C Start or repeated Start condition hold
tsps
I2C Stop condition setup
tvd(data)
Valid data time
SCL low to SDA output valid
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
0.1
Cb
I2C bus capacitive load
(1)
0
clock low time
μs
μs
50
serial-data setup time
100
ns
0
ns
(1)
(1)
10-pF to 400-pF bus
(1)
1.3
Start or repeated Start condition setup
ns
μs
0.6
μs
0.6
μs
0.6
μs
50
ns
0.9
μs
400
ns
Cb = Total capacitance of one bus in pF
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5.7 RESET Timing Requirements
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
STANDARD MODE and FAST MODE
tW
Reset pulse duration
tREC
Reset recovery time
tRESET
Time to reset
4
ns
0
ns
400
ns
5.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 6-2 and Figure 6-3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
P port
INT
MIN
MAX
UNIT
STANDARD MODE and FAST MODE
tiv
8
Interrupt valid time
4
μs
4
μs
200
ns
tir
Interrupt reset delay time
SCL
INT
tpv
Output data valid
SCL
P7–P0
tps
Input data setup time
P port
SCL
100
ns
tph
Input data hold time
P port
SCL
1
μs
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5.9 Typical Characteristics
TA = 25°C (unless otherwise noted)
22
1.8
1.8 V
2.5 V
3.3 V
5V
ICC - Supply Current (µA)
18
16
1.6
ICC - Supply Current (µA)
20
14
12
10
8
6
4
0
-40
-15
10
35
60
TA - Free-Air Temperature (°C)
fSCL = 400 kHz
1
0.8
1.8 V
2.5 V
3.3 V
5V
0.6
0.4
0
-40
85
-15
D001
fSCL = 0 kHz
I/Os = High or Low
Inputs
10
35
60
TA - Free-Air Temperature (°C)
85
D002
I/Os = High or Low
Inputs
Figure 5-2. Supply Current (ICC, Standby Mode) vs Temperature
(TA) at Four Supply Voltages
Figure 5-1. Supply Current (ICC, Operating Mode) vs
Temperature (TA) at Four Supply Voltages
25
250
VOL - Output Low Voltage (mV)
ICC - Supply Current (µA)
1.2
0.2
2
20
15
10
5
0
0.5
1
fSCL = 400 kHz
1.5
2
2.5
3
3.5
4
VCC - Supply Voltage (V)
I/Os = High or Low
Inputs
4.5
5
200
150
100
VCC
VCC
VCC
VCC
50
0
-40
0
5.5
-15
D003
=
=
=
=
1.8 V, IOL = 8 mA
5 V, IOL = 8 mA
1.8 V, IOL = 10 mA
5 V, IOL = 10 mA
10
35
60
TA - Free-Air Temperature (°C)
85
D004
I/Os = High or Low
Inputs
TA = 25°C
Figure 5-3. Supply Current (ICC, Operating Mode) vs Supply
Voltage (VCC)
Figure 5-4. Output Low Voltage (VOL) vs Temperature (TA) for
P-Port I/Os
80
500
1.8 V
2.5 V
3.3 V
5V
70
60
(VCC - VOH) - Output High Voltage (mV)
IOL - Output Sink Current (mA)
1.4
50
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
VOL - Output Low Voltage - (V)
0.7
0.8
450
400
VCC
VCC
VCC
VCC
=
=
=
=
1.8 V, IOH = 8 mA
5 V, IOH = 8 mA
1.65 V, IOH = 10 mA
5 V, IOH = 10 mA
350
300
250
200
150
100
50
0
-40
D005
-15
10
35
60
TA - Free-Air Temperature (°C)
85
D006
Figure 5-6. Output High Voltage (VCC – VOH) vs Temperature (TA)
for P-Ports
TA = 25°C
Figure 5-5. Sink Current (IOL) vs Output Low Voltage (VOL) for
P-Ports at Four Supply Voltages
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5.9 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
6
1.8 V
2.5 V
3.3 V
5V
60
50
VOH - Output High Voltage (V)
IOH - Output Source Current (mA)
70
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
(VCC - VOH) - Output High Voltage (V)
0.7
0.8
4
3
2
1
IOH = -8 mA
IOH = -10 mA
0
0
1
D007
TA = 25°C
2
3
4
VCC - Supply Voltage (V)
5
6
D008
TA = 25°C
Figure 5-7. Source Current (IOH) vs Output High Voltage (VOH)
for P-Ports at Four Supply Voltages
10
5
Figure 5-8. Output High Voltage (VOH) vs Supply Voltage (VCC)
for P-Ports
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6 Parameter Measurement Information
VCC
RL = 1 NŸ
DUT
SDA
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Condition
(S)
Address
Bit 7
(MSB)
Address
Bit 6
tscl
Address
Bit 1
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 x VCC
SCL
0.3 x VCC
ticr
tbuf
tsts
tPHL
ticf
tPLH
tsp
0.7 x VCC
SDA
0.3 x VCC
ticf
ticr
tsdh
tsds
tsth
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 6-1. I2C Interface Load Circuit and Voltage Waveforms
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V CC
R L = 4.7 kW
INT
DUT
C L = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
1
1
1
0
0
A1
A0
1
A
1
2
3
4
5
6
7
8
A
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
t ir
t ir
B
B
INT
A
t iv
t sps
A
Data
Into
Port
Address
Data 1
0.7 × V CC
INT
SCL
0.3 × V CC
Data 2
0.7 × V CC
R/W
t iv
A
0.3 × V CC
t ir
0.7 × V CC
Pn
0.7 × V CC
INT
0.3 × V CC
0.3 × V CC
View A−A
View B−B
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 6-2. Interrupt Load Circuit and Voltage Waveforms
12
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Pn
500 Ÿ
DUT
2 x VCC
CL = 50 pF
(see Note A)
500 Ÿ
P-PORT LOAD CONFIGURATION
SCL
0.7 x VCC
P0
A
P3
0.3 x VCC
Slave
ACK
SDA
tpv
(see Note B)
Unstable Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 x VCC
SCL
P0
A
P3
0.3 x VCC
tph
tps
0.7 x VCC
Pn
0.3 x VCC
READ MODE (R/W = 1)
A.
B.
C.
D.
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Figure 6-3. P-Port Load Circuit and Voltage Waveforms
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V CC
Pn
R L = 1 kW
DUT
500 Ω
DUT
SDA
2 × V CC
C L = 50 pF
(see Note A)
500 Ω
C L = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 x VCC
t RESET
RESET
VCC / 2
t REC
tw
Px
(see Note D)
VCC / 2
t RESET
A.
B.
C.
D.
E.
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs.
All parameters and waveforms are not applicable to all devices.
Figure 6-4. Reset Load Circuits and Voltage Waveforms
14
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7 Detailed Description
7.1 Functional Block Diagram
INT
A0
A1
13
LP Filter
Interrupt Logic
1
2
P7-P0
SCL
SDA
14
15
Input Filter
I2C Bus Control
Shift Register
8 Bits
I/O Port
Write Pulse
RESET
VCC
GND
3
Read Pulse
Power-On
Reset
16
8
Pin numbers shown are for the DB, DBQ, DGV, DW, or PW package.
Figure 7-1. Functional Block Diagram
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
VCC
Configuration
Register
Q1
D Q
FF
Write Configuration
Pulse
D Q
FF
CK Q
Write Pulse
P0 to P7
CK Q
Output Port
Register
Q2
Input Port
Register
D Q
FF
CK Q
Read Pulse
Data From Shift
Register
D Q
FF
CK Q
Write Polarity
Pulse
ESD Protection
Diode
GND
Input Port
Register Data
To INT
Polarity
Register Data
Polarity Inversion
Register
At power-on reset, all registers return to default values.
Figure 7-2. Simplified Schematic Of P0 To P7
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7.2 Device Functional Modes
7.2.1 RESET Input
The RESET input can be asserted to reset the system while keeping the VCC at its operating level. A reset can
be accomplished by holding the RESET pin low for a minimum of tW. The PCA9538 registers and I2C/SMBus
state machine are changed to their default states once RESET is low (0). Once RESET is high (1), the I/O levels
at the P port can be changed externally or through the master. This input requires a pullup resistor to VCC if no
active connection is used.
7.2.1.1 RESET Errata
If RESET voltage set higher than VCC, current flows from RESET pin to VCC pin.
System Impact
VCC is pulled above its regular voltage level.
System Workaround
Design such that RESET voltage is same or lower than VCC.
7.2.2 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9538 in a reset condition until
VCC has reached VPOR. At that point, the reset condition is released and the PCA9538 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
7.2.3 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 7-2) are off, creating a high-impedance input.
The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register.
In this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin must not exceed the recommended levels for proper operation.
16
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7.2.4 Interrupt Output ( INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv,
the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the
original setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting
of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause
an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the
pin does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to VCC.
7.2.4.1 Interrupt Errata
The INT will be improperly de-asserted if the following two conditions occur:
1. The last I²C command byte (register pointer) written to the device was 00h.
Note
This generally means the last operation with the device was a Read of the input register. However,
the command byte may have been written with 00h without ever going on to read the input register.
After reading from the device, if no other command byte written, it remains 00h.
2. Any other slave device on the I²C bus acknowledges an address byte with the R/W bit set high
System Impact
Can cause improper interrupt handling as the Master sees the interrupt as being cleared.
System Workaround
Minor software change: User must change command byte to something besides 00h after a Read operation to
the PCA9538 device or before reading from another slave device.
Note
Software change are compatible with other versions (competition and TI redesigns) of this device.
7.3 Programming
7.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 7-3). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/ W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A1) of the slave device must
not be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 7-4).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 7-3).
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Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure
7-5). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the
master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times
must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 7-3. Definition Of Start And Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
Of Data
Allowed
Figure 7-4. Bit Transfer
Data Output
By Transmitter
NACK
Data Output
By Receiver
ACK
SCL From
Master
1
2
S
8
9
Clock Pulse for
Acknowledgment
Start
Condition
Figure 7-5. Acknowledgment On I2C Bus
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7.4 Register Maps
Table 7-1 shows the address byte of the PCA9538.
Table 7-1. Interface Definition Table
BYTE
I2C
slave address
Px I/O data bus
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
H
H
H
L
L
A1
A0
R/ W
P7
P6
P5
P4
P3
P2
P1
P0
7.4.1 Device Address
Figure 7-6 shows the address byte of the PCA9538.
Slave Address
1
1
1
0
0
A1
Fixed
A0
R/W
Hardware
Selectable
Figure 7-6. PCA9538 Address
Table 7-2 shows the PCA9538 address reference.
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Table 7-2. Address Reference Table
INPUTS
A1
I2C BUS SLAVE ADDRESS
A0
L
L
112 (decimal), 70 (hexadecimal)
L
H
113 (decimal), 71 (hexadecimal)
H
L
114 (decimal), 72 (hexadecimal)
H
H
115 (decimal), 73 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected while a low (0) selects a write operation.
7.4.2 Control Register And Command Byte
Following the successful Acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9538 (see Figure 7-7). Two bits of this command byte state the operation
(read or write) and the internal register (input, output, polarity inversion or configuration) that are affected. This
register can be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
Figure 7-7 shows the PCA9538 control register bits and Table 7-3 shows the command byte.
0
0
0
0
0
0
B1
B0
Figure 7-7. Control Register Bits
Table 7-3. Command Byte Table
CONTROL REGISTER BITS
20
B1
B0
COMMAND BYTE
(HEX)
REGISTER
PROTOCOL
POWER-UP DEFAULT
0
0
0×00
Input Port
Read byte
XXXX XXXX
0
1
0×01
Output Port
Read/write byte
1111 1111
1
0
0×02
Polarity Inversion
Read/write byte
0000 0000
1
1
0×03
Configuration
Read/write byte
1111 1111
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7.4.3 Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin
is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register is accessed next. See Table 7-4.
Table 7-4. Register 0 (Input Port Register) Table
BIT
I7
I6
I5
I4
I3
I2
I1
I0
DEFAULT
X
X
X
X
X
X
X
X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See Table
7-5.
Table 7-5. Register 1 (Output Port Register) Table
BIT
O7
O6
O5
O4
O3
O2
O1
O0
DEFAULT
1
1
1
1
1
1
1
1
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained. See Table 7-6.
Table 7-6. Register 2 (Polarity Inversion Register) Table
BIT
N7
N6
N5
N4
N3
N2
N1
N0
DEFAULT
0
0
0
0
0
0
0
0
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output. See Table 7-7.
Table 7-7. Register 3 (Configuration Register) Table
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
1
1
1
1
1
1
1
1
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7.4.4 Bus Transactions
Data is exchanged between the master and PCA9538 through write and read commands.
7.4.4.1 Writes
Data is transmitted to the PCA9538 by sending the device address and setting the least-significant bit (LSB) to a
logic 0 (see Figure 7-6 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte (see Figure 7-8 and Figure 7-9). There is no limitation
on the number of data bytes sent in one write transmission.
1
SCL
3
2
6
4
7
8
9
Slave Address
SDA S
1
1
1
0
Command Byte
0 A1 A0 0
Start Condition
A
0
0
0
0
0
Data to Register
0
0
R/W ACK From Slave
1
A
Data 1
A
P
ACK From Slave
ACK From Slave
Write to
Port
Data Out
From Port
Data 1 Valid
tpv
Figure 7-8. Write To Output Port Register
1
SCL
2
3
4
6
7
8
9
Slave Address
SDA
S
1
1
1
Start Condition
0
Command Byte
0 A1 A0 0
A
0
0
0
0
R/W ACK From Slave
0
0
Data to Register
1 1/0 A
Data
A
P
ACK From Slave
ACK From Slave
Data to
Register
Figure 7-9. Write To Configuration Or Polarity Inversion Registers
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7.4.4.2 Reads
The bus master first must send the PCA9538 address with the LSB set to a logic 0 (see Figure 7-6 for device
address). The command byte is sent after the address and determines which register is accessed. After a
restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined
by the command byte then is sent by the PCA9538 (see Figure 7-10 and Figure 7-11). After a restart, the value
of the register defined by the command byte matches the register being accessed when the restart occurred.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
S 1
1
1
0
ACK From
Slave
ACK From
Slave
Slave Address
0 A1 A0 0
Command Byte
A
A S 1
ACK From
ACK From
Master
Slave Data from Register
Slave Address
1
1
0
Data
A
Data from Register
NACK From
Master
0 A1 A0 1 A
R/W
R/W
Data
NA P
Last Byte
Figure 7-10. Read From Register
1
SCL
2
3
4
5
6
7
8
9
Data From Port
Slave Address
SDA
S
1
1
1
0
0 A1 A0 1
Start
Condition
R/W
Data 1
A
Data From Port
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
t ph
Data 3
Data 4
Data 5
t ps
INT
t iv
t ir
A. This figure assumes the command byte has previously been programmed with 00h.
B. Transfer of data can be stopped at any moment by a Stop condition.
C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data
transfer from the P port. See Figure 7-10 for these details.
Figure 7-11. Read From Input Port Register
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8 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.2 Typical Application
Figure 8-1 shows an application in which the PCA9538 can be used.
VCC
(5 V)
10 NŸ
VCC
10 NŸ
10 NŸ
2 NŸ
10 NŸ
VCC
SCL
SCL
SDA
SDA
100 NŸ
(x3)
Subsystem 1
(e.g., temperature
sensor)
P0
Master
Controller
INT
P1
INT
P2
RESET
P3
RESET
PCA9536
GND
Subsystem 2
(e.g., counter)
P4
P5
A1
A
P6
A0
P7
GND
Controlled Device
(eg.g., CBT device)
ENABLE
B
ALARM
Subsystem 2
(e.g., counter)
VCC
A.
B.
C.
D.
Device address is configured as 1110000 for this example.
P0, P2, and P3 are configured as outputs.
P1, P4, and P5 are configured as inputs.
P6 and P7 are not used and must be configured as outputs.
Figure 8-1. Typical Application
8.2.1 Detailed Design Procedure
8.2.1.1 Minimizing ICC When I/Os Control Leds
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 8-1. The LED acts as a diode, so when the LED is off, the I/O VIN is about 1.2 V less than VCC. ICC in
Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC.
24
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For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when
the LED is off to minimize current consumption. Figure 8-2 shows a high-value resistor in parallel with the LED.
Figure 8-3 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O
VIN at or above VCC and prevents additional supply current consumption when the LED is off.
VCC
LED
100 kW
VCC
LEDx
Figure 8-2. High-Value Resistor in Parallel with Led
3.3 V
VCC
5V
LED
LEDx
Figure 8-3. Device Supplied by a Lower Voltage
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9 Power Supply Recommendations
9.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9538 can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 9-1 and Figure 9-2.
VCC
Ramp-Up
Re-Ramp-Up
Ramp-Down
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 9-1. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
VCC
Ramp-Down
Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 9-2. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC
Table 9-1 specifies the performance of the power-on reset feature for PCA9538 for both types of power-on reset.
Table 9-1. Recommended Supply Sequencing And Ramp Rates (1)
PARAMETER
MIN
TYP
MAX
UNIT
VCC_FT
Fall rate
See Figure 9-1
1
100
ms
VCC_RT
Rise rate
See Figure 9-1
0.01
100
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 9-1
0.001
ms
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 9-2
0.001
ms
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 9-3
VCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 9-3
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on rising VCC
1.033
1.428
V
(1)
1.2
V
μs
TA = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
the device impedance are factors that affect power-on reset performance. Figure 9-3 and Table 9-1 provide more
information on how to measure these specifications.
26
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PCA9538
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SCPS126G – SEPTEMBER 2006 – REVISED MARCH 2021
VCC
VCC_GH
Time
VCC_GW
Figure 9-3. Glitch Width And Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all
the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs
based on the VCC being lowered to or from 0. Figure 9-4 and Table 9-1 provide more details on this specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 9-4. VPOR
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCA9538DB
ACTIVE
SSOP
DB
16
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD538
PCA9538DBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD538
PCA9538DGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD538
PCA9538DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9538
PCA9538DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9538
PCA9538PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD538
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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