PCM1606

PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 24-BIT, 192-kHz SAMPLING, 6-CHANNEL, ENHANCED MULTILEVEL, DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER FEATURES D 24-Bit Resolution D Analog Performance: – Dynamic Range: 103 dB, Typical – SNR: 103 dB, Typical – THD+N: 0.004%, Typical – Full-Scale Output: 3.1 Vp-p, Typical 8× Oversampling Interpolation Filter: – Stopband Attenuation: –55 dB – Passband Ripple: ±0.03 dB Sampling Frequency: – 5 kHz to 200 kHz (Channels 1 and 2) – 5 kHz to 100 kHz (Channels 3, 4, 5, and 6) Accepts 16- and 24-Bit Audio Data Data Formats: Standard, I2S, and Left-Justified, TDM System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768 fS Digital De-Emphasis for 32 kHz, 44.1 kHz, 48 kHz Power Supply: 5-V Single Supply 20 -Lead SSOP Package DESCRIPTION The PCM1606 is a CMOS monolithic integrated circuit that features six 24-bit audio digital-to-analog converters and support circuitry in a small 20-lead SSOP package. The digital-to-analog converters utilize Texas Instruments’ enhanced multilevel, delta-sigma architecture, which employs 2nd-order noise shaping and 8-level amplitude quantization to achieve excellent signal-to-noise performance and a high tolerance to clock jitter. The PCM1606 accepts industry-standard audio data formats with 16- to 24-bit audio data. Sampling rates up to 200 kHz are supported. D D D D D D D D PCM1606 (TOP VIEW) APPLICATIONS D Integrated A/V Receivers D DVD Movie and Audio Players D HDTV Receivers D Car Audio Systems D DVD Add-On Cards for High-End PCs D Digital Audio Workstations D Other Multichannel Audio Systems DATA1 DATA2 DATA3 FMT1 FMT0 ZEROA AGND VOUT5 VOUT6 VOUT1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SCKI BCK LRCK DEMP1 DEMP0 VCC VCOM VOUT4 VOUT3 VOUT2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2002, Texas Instruments Incorporated www.ti.com 1 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER ZZ334 1 ZZ334-1 OPERATION TEMPERATURE RANGE –25°C to 85°C PACKAGE MARKING PCM1606E ORDERING NUMBER† PCM1606E TRANSPORT MEDIA TUBE PCM1606E/2K Tape and Reel † Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of PCM1606Y/2K gets a single 2000-piece tape and reel. PCM1606E 20 Lead SSOP 20-Lead functional block diagram DAC Serial Input I/F 4x / 8x Oversampling Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter BCK LRCK DATA1(1, 2) DATA2(3, 4) DATA3(5, 6) Enhanced Multilevel Delta-Sigma Modulator VOUT1 DAC VOUT2 DAC VOUT3 Digital Filter with Function Controller DEMP1 DEMP0 FMT1 FMT0 Function Control I/F DAC VCOM VOUT4 DAC VOUT5 DAC System Clock SCKI System Clock VOUT6 Manager Zero Detect Power Supply ZEROA VCC AGND 2 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 Terminal Functions TERMINAL NAME AGND BCK DATA1 DATA2 DATA3 DEMP0 DEMP1 FMT1 FMT0 LRCK SCKI VCC VCOM VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 ZEROA PIN 7 19 1 2 3 16 17 4 5 18 20 15 14 10 11 12 13 8 9 6 I/O — I I I I I I I I I I — — O O O O O O O Analog and digital ground Shift clock input for serial audio data (see Note 2) Serial audio data input for VOUT1 and VOUT2 (see Note 2) Serial audio data input for VOUT3 and VOUT4 (see Note 2) Serial audio data input for VOUT5 and VOUT6 (see Note 2) De-emphasis control (see Note 1) De-emphasis control (see Note 1) Format select (see Note 1) Format select (see Note 1) Left and right clock input. This clock is equal to the sampling rate, fS (see Note 2) System clock in. Input frequency is 128 fS, 192 fS, 256 fS, 384 fS, 512 fS or 768 fS (see Note 2) Analog and digital power supply, 5 V Common voltage output. This pin should be bypassed with a 10-µF capacitor to AGND Voltage output for audio signal corresponding to L-channel on DATA1. Up to 192 kHz Voltage output for audio signal corresponding to R-channel on DATA1. Up to 192 kHz Voltage output for audio signal corresponding to L-channel on DATA2. Up to 96 kHz Voltage output for audio signal corresponding to R-channel on DATA2. Up to 96 kHz Voltage output for audio signal corresponding to L-channel on DATA3. Up to 96 kHz Voltage output for audio signal corresponding to R-channel on DATA3. Up to 96 kHz Zero-data flag. Logical AND of ZERO1 through ZERO6 DESCRIPTIONS NOTES: 1. Schmitt-trigger input with internal pulldown. 2. Schmitt-trigger input. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Digital input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Analog input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Input current (except power supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (soldering, 5s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5s Package temperature (IR reflow, 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10s † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. www.ti.com 3 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data (unless otherwise noted) PCM1606E PARAMETER RESOLUTION DATA FORMAT Audio data interface format Audio data bit length Audio data format fS Sampling frequency System clock frequency DIGITAL INPUT/OUTPUT Logic family (TTL compatible) VIH VIL IIH IIL VOH VOL High-level input voltage Low-level input voltage High-level input current Low-level input current High-level output voltage Low-level output voltage VIN = VCC VIN = 0 V IOH = –4 mA IOL = 4 mA fS = 44.1 kHz/384 fS fS = 96 kHz/256 fS fS = 192 kHz/128 fS fS = 44.1 kHz/348 fS VOUT = –60 dB 60 dB fS = 96 kHz / 256 fS fS = 192 kHz/128 fS EIAJ, A-weighted, fS = 44.1 kHz/384 fS Dynamic range range A-weighted, fS = 96 kHz/256 fS A-weighted, fS = 192 kHz/128 fS EIAJ, A-weighted, fS = 44.1 kHz/384 fS Signal to noise ratio Signal-to-noise ratio A-weighted, fS = 96 kHz/256 fS A-weighted, fS = 192 kHz/128 fS Channel se aration separation Level linearity error DC ACCURACY Gain error Gain mismatch, channel-to-channel Bipolar zero error ANALOG OUTPUT Output voltage Center voltage Load impedance Ac load 5 Full scale (–0 dB) 62% of VCC 50% of VCC Vp-p Vdc kΩ VOUT = 0.5 VCC at BPZ ±1 %FSR ±1.3 %FSR ±30 mV fS = 44.1 kHz/384 fS fS = 96 kHz/256 fS fS = 192 kHz/128 fS VOUT = –90 dB 95 98 98 2.4 1 0.004% 0.005% 0.002% 1% 1.2% 1% 103 99 101 103 100 101 100 95 100 ±0.5 dB dB dB dB 0.01% 67 2 0.8 100 –10 V V µA µA V V VOUT1, VOUT2 VOUT3, VOUT4, VOUT5, VOUT6 Standard, I2S, Left-Justified, TDM 16 or 24 bits, selectable MSB first, 2s complement 5 5 200 100 kHz TEST CONDITIONS MIN TYP 24 MAX UNIT Bits 128, 192, 256, 384, 512, 768 fS DYNAMIC PERFORMANCE VOUT = 0 dB dB THD+N Total harmonic harmonic distortion plus noise 4 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data (unless otherwise noted) (continued) PCM1606E PARAMETER DIGITAL FILTER PERFORMANCE FILTER CHARACTERISTICS Passband Stopband Passband ripple Stopband attenuation ANALOG FILTER PERFORMANCE Frequency response POWER SUPPLY REQUIREMENTS (see Note 4) VCC ICC Voltage range fS = 44.1 kHz/384 fS fS = 96 kHz/256 fS fS = 192 kHz/128 fS fS = 44.1 kHz/384 fS Power dissi ation dissipation TEMPERATURE RANGE Operation temperature –25 85 °C θJA Thermal resistance 20-pin SSOP 115 °C/W NOTES: 3. Analog performance specs are tested using System Two Cascade Plus by Audio Precision with 400-Hz HPF, 30-kHz LPF on at RMS with 20-kHz LPF, 400-Hz HPF in calculation. Shibasoku #725 THD meter, 400 Hz HPF, 30 kHz LPF on, at average mode with 20-kHz bandwidth limiting. The load connected to the analog output is 5 kΩ or larger via capacitance coupling. 4. Condition in 192-kHz operation is channel 3 through channel 6 are disabled. fS = 96 kHz/256 fS fS = 192 kHz/128 fS 4.5 5 50 72 68 250 360 340 358 mW 5.5 65 mA VDC At 20 kHz –0.03 dB Stopband = 0.546 fS Stopband = 0.567 fS –50 –55 dB ±0.03 dB –3 dB 0.546 fS ±0.03 dB 0.454 fS 0.487 fS TEST CONDITIONS MIN TYP MAX UNIT Supply current Su ly current timing requirements system clock input The PCM1606 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCKI (pin 20). Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. Texas Instruments’ PLL1700 multiclock generator is an excellent choice for providing the PCM1606 system clock source. The 192-kHz sampling frequency operation is available on DATA1 for VOUT1 and VOUT2. When the system clock of 128 fS or 192 fS is detected, VOUT3, VOUT4, VOUT5 and VOUT6 are automatically forced to the bipolar zero level (= 0.5 VCC). Table 1 lists the typical system clock frequency. www.ti.com 5 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 timing requirements (continued) power-on reset functions The PCM1606 includes a power-on reset function. Figure 2 shows the operation of this function. With the system clock active and VCC > 3 V typical (2.2 V to 3.7 V), the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VCC > 3 V. After the initialization period, the PCM1606 is set to its reset default state. Table 1. System Clock Rates for Common Audio Sampling Frequencies SAMPLING FREQUENCY 8 kHz 16 kHz 32 kHz 44.1 kHz 48 kHz 96 kHz 192 kHz SYSTEM CLOCK FREQUENCY (fSCLK) (MHz) 128 fS — — — — — — 24.576 192 fS — — — — — — 36.864 256 fS 2.048 4.096 8.192 11.2896 12.288 24.576 See Note 6 384 fS 3.072 6.144 12.288 16.9344 18.432 36.864 See Note 6 512 fS 4.096 8.192 16.384 22.5792 24.576 49.152 See Note 6 768 fS 6.144 12.288 24.576 33.8688 36.864 See Note 5 See Note 6 NOTES: 5. The 768-fS system clock rate is not supported for fS > 64 kHz. 6. This system clock is not supported for the given sampling frequency. t(SCKH) 2.0 V System Clock 0.8 V t(SCKL) † 1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS and 1/768 fS. PARAMETERS t(SCKH) t(SCKL) System clock pulse duration HIGH System clock pulse duration LOW MIN 10 10 MAX UNIT ns ns System Clock Pulse Cycle Time† Figure 1. System Clock Timing VDD 3.7 V 3.0 V 2.2 V 0V Reset Reset Removal Internal Reset Don’t Care System Clock 1024 System Clocks Figure 2. Power-On Reset Timing 6 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 timing requirements (continued) audio serial interface The audio serial interface for the PCM1606 comprises a 5-wire synchronous serial port. It includes LRCK (pin 18), BCK (pin 19), DATA1 (pin 1), DATA2 (pin 2) and DATA3 (pin 3). BCK is the serial audio bit clock and is used to clock the serial data present on DATA1, DATA2, and DATA3 into the audio interface serial shift registers. Serial data is clocked into the PCM1606 on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK is used to latch serial data into the serial audio interface internal registers. Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK be derived from the system clock input or output, SCKI. The left/right clock, LRCK, is operated at the sampling frequency (fS). The bit clock, BCK, may be operated at 32, 48, or 64 times the sampling frequency. audio data formats and timing The PCM1606 supports industry-standard audio data formats, including standard, I2S, left-justified, and TDM. The data formats are shown in Figure 6. Data formats are selected using the format pins, FMT1 (pin 4) and FMT0 (pin 5). All formats require binary 2s complement, MSB-first audio data. Figure 3 shows a detailed timing diagram for the serial audio interface, with the exception of TDM format. DATA1, DATA2, and DATA3 each carry two audio channels, designated as the left and right channels. The left channel data always precedes the right channel data in the serial data stream for all data formats. Table 2 shows the mapping of the digital input data to the analog output pins. TDM format is able to interface by 3-wire synchronous serial port. All data inputs from DATA1, BCK can be operated at 128, 256, and 512 times the sampling frequency. The rising edge of LRCK means the start of a data frame. Only channel 1 and channel 2 data are acceptable at the 192-kHz sampling frequency (fS); channel 3, channel 4, channel 5, and channel 6 data are don’t care. Figure 4 shows the timing requirements for BCK input for TDM format. Figure 5 shows the detailed timing diagram for TDM format. Table 2. Audio Input Data to Analog Output Mapping DATA INPUT DATA1 DATA1 DATA2 DATA2 DATA3 DATA3 † Up to 192 kHz ‡ Up to 96 kHz CHANNEL Left Right Left Right Left Right ANALOG OUTPUT VOUT1† VOUT2† VOUT3‡ VOUT4‡ VOUT5‡ VOUT6‡ www.ti.com 7 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 timing requirements (continued) LRCK t(BCH) BCK t(BCY) t(BL) t(BCL) t(LB) 1.4 V 1.4 V DATA1, DATA2, DATA3 tsu(D) PARAMETER t(BCY) t(BCH) t(BCL) t(BL) t(LB) BCK pulse cycle time BCK high-level time BCK low-level time BCK rising edge to LRCK edge LRCK falling edge to BCK rising edge 35 35 10 10 10 10 th(D) MIN MAX 32 fS / 48 fS / 64 fS† 1.4 V UNIT ns ns ns ns ns ns tsu(D) DATA setup time th(D) DATA hold time † fS is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.) Figure 3. Audio Interface Timing Table 3. Bit Clock Rates for TDM Format Sampling Frequencies SAMPLING FREQUENCY 8 kHz 16 kHz 32 kHz 44.1 kHz 48 kHz 96 kHz 192 kHz SYSTEM CLOCK FREQUENCY (fSCKI) (MHz) 128 fS — — — — — — 24.576 256 fS 2.048 4.096 8.192 11.2896 12.288 24.576 See Note 7 512 fS 4.096 8.192 16.384 22.5792 24.576 49.152 See Note 7 NOTE 7: This bit clock is not supported for the given sampling frequency. 8 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 timing requirements (continued) t(BCKH) 2.0 V BCK 0.8 V t(BCKL) Bit Clock Pulse Cycle Time† MIN 10 10 MAX UNIT ns ns PARAMETERS t(BCKH) Bit clock pulse duration HIGH t(BCKL) Bit clock pulse duration LOW † 1/128 fS, 1/256 fS, and 1/512 fS. Figure 4. Bit Clock Timing for TDM Format LRCK t(BCH) BCK t(BCY) t(BL) t(BCL) t(LB) 1.4 V 1.4 V DATA1 tsu(D) PARAMETER t(BCY) t(BCH) t(BCL) t(BL) t(LB) tsu(D) th(D) BCK pulse cycle time BCK high-level time BCK low-level time BCK rising edge to LRCK edge LRCK falling edge to BCK rising edge DATA setup time DATA hold time th(D) MIN 20 10 10 7 7 7 7 MAX 1.4 V UNIT ns ns ns ns ns ns ns Figure 5. Audio Interface Timing for TDM Format www.ti.com 9 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 timing requirements (continued) (1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L–Channel R–Channel BCK (= 32 fS, 48 fS or 64 fS) 16-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 14 15 16 16-Bit Right-Justified, BCK = 32 fS DATA 14 15 16 1 2 3 1 2 3 14 15 16 LSB 14 15 16 LSB 1 2 3 1 2 3 14 15 16 LSB 14 15 16 LSB MSB MSB MSB MSB (2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L–Channel R–Channel BCK DATA 1 2 3 N –2 N –1 N 1 2 3 N –2 N –1 N 1 2 MSB LSB MSB LSB (3) I2S Data Format; L-Channel = LOW, R-Channel = HIGH 1/fS LRCK L–Channel R–Channel BCK (= 48 fS or 64 fS) DATA 1 2 3 N –2 N –1 N 1 2 3 N –2 N –1 N 1 2 MSB LSB MSB LSB Figure 6. Audio Data Input Format 10 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 timing requirements (continued) (4) TDM Data Format BCK = 256 fS Channel 1 LRCK 32 BCK BCK 32 BCK Channel 2 1/fS Channel 3 Channel 6 1 2 3 22 23 24 LSB LOW Fix 1 24 LOW Fix LOW Fix 64 Bit 1 2 MSB BCK = 128 fS Channel 1 LRCK 32 BCK BCK 32 BCK Channel 2 1/fS 1 2 3 22 23 24 LSB LOW Fix MSB 1 24 LOW Fix LSB LOW Fix 64 Bit 1 2 MSB BCK = 512 fS Channel 1 LRCK 64 BCK BCK 64 BCK Channel 2 1/fS Channel 3 Channel 6 LOW Fix 1 2 MSB LSB 24 LOW Fix 1 LOW Fix 1 Figure 6. Audio Data Input Format (Continued) functional description The PCM1606 has several built-in functions including digital input data format selection and digital de-emphasis. These functions are hardware controlled with static control signals and used on pin FMT1 (pin 4), pin FMT0 (pin 5), pin DEMP1 (pin 17), and DEMP0 (pin 16). data format selection The PCM audio data format can be selected by pin FMT1 (pin 4) and FMT0 (pin 5) as shown in Table 4. Table 4. Data Format Control FMT1 (pin 4) LOW LOW HIGH HIGH FMT0 (pin 5) LOW HIGH LOW HIGH AUDIO INTERFACE I2S TDM Standard Left-justified www.ti.com 11 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 functional description (continued) de-emphasis control The de-emphasis control can be selected by DEMP1 (pin 17) and DEMP0 (pin 16). See Table 5. Table 5. De-Emphasis Control DEMT1 (pin 17) LOW LOW HIGH HIGH DEMT0 (pin 16) LOW HIGH LOW HIGH AUDIO INTERFACE OFF 48 kHz 44.1 kHz 32 kHz analog outputs The PCM1606 includes six independent output channels, VOUT1 through VOUT6. These are unbalanced outputs, each capable of driving 3.1 Vp-p typical into a 5-kΩ ac load with VCC = 5 V. The internal output amplifiers for VOUT1 through VOUT6 are dc-biased to the common-mode (or bipolar zero) voltage, equal to VCC/2. The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise shaping characteristics of the PCM1606’s delta-sigma D/A converters. The frequency response of this filter is shown in Figure 7. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application Information section of this data sheet. LEVEL vs FREQUENCY 20 0 –20 Level – dB –40 –60 –80 –100 1 10 100 1k 10k 100k 1M 10M f – Frequency – Hz Figure 7. Output Filter Frequency Response 12 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 functional description (continued) VCOM output One unbuffered common-mode voltage output pin, VCOM (pin 14) is brought out for decoupling purposes. This pin is nominally biased to a dc voltage level equal to VCC/2. If this pin is to be used to bias external circuitry, a voltage follower is required for buffering purposes. Figure 8 shows an example of using the VCOM pin for external biasing applications. PCM1606 4 14 + 3 – OPA337 1 V BIAS [ VCOM + V CC 2 10 µF Figure 8. Biasing External Circuits Using the VCOM Pin zero flag zero detect condition Zero detection for each output channel is independent from the others. If the data for a given channel remains at a 0 level for 1024 sample periods (or LRCK clock periods), a zero detect condition exists for that channel. zero output flag When the data for all channels remains at a 0 level for 1024 sample periods (or LRCK clock periods), the ZEROA (pin 6) is set to a logic 1 state. The zero flag pin can be used to operate external mute circuits, or used as a status indicator for a microcontroller, audio signal processor, or other digitally controlled functions. www.ti.com 13 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 TYPICAL CHARACTERISTICS—DIGITAL FILTER AMPLITUDE vs FREQUENCY 0 –20 –40 Amplitude – dB Amplitude – dB –60 –80 –100 –120 –0.04 –140 0 1 2 f – Frequency [ fS] 3 4 –0.05 0.0 VCC = 5 V fS = 44.1 kHz TA = 25°C De-emphasis Off 0.05 0.04 0.03 0.02 0.01 0.00 –0.01 –0.02 –0.03 VCC = 5 V fS = 44.1 kHz TA = 25°C De-emphasis Off AMPLITUDE vs FREQUENCY 0.1 0.2 0.3 0.4 0.5 f – Frequency [ fS] Figure 9 DE-EMPHASIS LEVEL vs FREQUENCY 0 –1 –2 De-emphasis Level – dB –3 –4 –5 –6 –7 –8 –9 –10 0 2 4 6 8 10 12 14 f – Frequency – kHz VCC = 5 V fS = 32 kHz TA = 25°C De-emphasis Error – dB 0.5 0.4 0.3 0.2 0.1 –0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 2 VCC = 5 V fS = 32 kHz TA = 25°C Figure 10 DE-EMPHASIS ERROR vs FREQUENCY 4 6 8 10 12 14 f – Frequency – kHz Figure 11 Figure 12 All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted. 14 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 TYPICAL CHARACTERISTICS—DIGITAL FILTER DE-EMPHASIS LEVEL vs FREQUENCY 0 –1 –2 De-emphasis Level – dB –3 –4 –5 –6 –7 –8 –9 –10 0 2 4 6 8 10 12 14 16 18 20 f – Frequency – kHz VCC = 5 V fS = 44.1 kHz TA = 25°C De-emphasis Error – dB 0.5 0.4 0.3 0.2 0.1 –0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 2 4 DE-EMPHASIS ERROR vs FREQUENCY VCC = 5 V fS = 44.1 kHz TA = 25°C 6 8 10 12 14 16 18 20 f – Frequency – kHz Figure 13 Figure 14 DE-EMPHASIS LEVEL vs FREQUENCY 0 –1 –2 De-emphasis Level – dB –3 –4 –5 –6 –7 –8 –9 –10 0 2 4 6 8 10 12 14 16 18 20 22 f – Frequency – kHz VCC = 5 V fS = 48 kHz TA = 25°C De-emphasis Error – dB 0.5 0.4 0.3 0.2 0.1 –0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 2 4 DE-EMPHASIS ERROR vs FREQUENCY VCC = 5 V fS = 48 kHz TA = 25°C 6 8 10 12 14 16 18 20 22 f – Frequency – kHz Figure 15 Figure 16 All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted. www.ti.com 15 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 TYPICAL CHARACTERISTICS—ANALOG DYNAMIC PERFORMANCE TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE 100.00 10 THD+N – Total Harmonic Distortion + Noise – % VCC = 5 V fS = 44.1 kHz TA = 25°C 10.00 1 44.1 kHz 384 fS 1.00 0.1 192 kHz 128 fS –60 dB 192 kHz 128 fS 96 kHz 256 fS Dynamic Range – dB 106 VCC = 5 V fS = 44.1 kHz TA = 25°C DYNAMIC RANGE vs SUPPLY VOLTAGE 104 44.1 kHz 384 fS 102 192 kHz 128 fS 100 96 kHz 256 fS 0.10 0.01 96 kHz 256 fS 44.1 kHz 384 fS 98 0 dB 0.01 0.001 4.0 4.5 5.0 5.5 6.0 96 4.0 4.5 5.0 5.5 6.0 VCC – Supply Voltage – V VCC – Supply Voltage – V Figure 17 SNR vs SUPPLY VOLTAGE 106 VCC = 5 V fS = 44.1 kHz TA = 25°C 104 Figure 18 CHANNEL SEPARATION vs SUPPLY VOLTAGE VCC = 5 V fS = 44.1 kHz TA = 25°C 104 Channel Separation – dB 44.1 kHz 384 fS 102 192 kHz 128 fS 44.1 kHz 384 fS 100 SNR – dB 102 192 kHz 128 fS 100 96 kHz 256 fS 98 96 96 kHz 256 fS 98 94 96 4.0 4.5 5.0 5.5 6.0 92 4.0 4.5 5.0 5.5 6.0 VCC – Supply Voltage – V VCC – Supply Voltage – V Figure 19 Figure 20 All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted. 16 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 TYPICAL CHARACTERISTICS—ANALOG DYNAMIC PERFORMANCE TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE 100.00 10 THD+N – Total Harmonic Distortion + Noise – % VCC = 5 V fS = 44.1 kHz 10.00 1 44.1 kHz 384 fS 1.00 0.1 96 kHz 256 fS 44.1 kHz 384 fS –60 dB Dynamic Range – dB 102 192 kHz 128 fS 96 kHz 256 fS 192 kHz 128 fS 104 106 VCC = 5 V fS = 44.1 kHz 44.1 kHz 384 fS DYNAMIC RANGE vs FREE-AIR TEMPERATURE 100 96 kHz 256 fS 98 0.10 0.01 192 kHz 128 fS 0 dB 0.01 0.001 –50 –25 0 25 50 75 100 TA – Free-Air Temperature – °C 96 –50 –25 0 25 50 75 100 TA – Free-Air Temperature – °C Figure 21 SNR vs FREE-AIR TEMPERATURE 106 VCC = 5 V fS = 44.1 kHz 104 44.1 kHz 384 fS Channel Separation – dB 104 VCC = 5 V fS = 44.1 kHz 102 Figure 22 CHANNEL SEPARATION vs FREE-AIR TEMPERATURE 44.1 kHz 384 fS 102 SNR – dB 192 kHz 128 fS 100 100 98 192 kHz 128 fS 96 kHz 256 fS 98 96 kHz 256 fS 96 96 94 94 –50 –25 0 25 50 75 100 92 –50 –25 0 25 50 75 100 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 23 Figure 24 All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted. www.ti.com 17 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 TYPICAL CHARACTERISTICS—ANALOG DYNAMIC PERFORMANCE –90-dB OUTPUT SPECTRUM 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 0.0 VCC = 5 V fS = 44.1 kHz TA = 25°C 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 0.0 VCC = 5 V fS = 44.1 kHz TA = 25°C –90-dB OUTPUT SPECTRUM Amplitude – dB Amplitude – dB 0.5 1.0 f – Frequency – MHz 1.5 2.0 0.1 0.2 f – Frequency – MHz 0.3 0.4 Figure 25 Figure 26 DYNAMIC RANGE vs JITTER 106 104 102 Dynamic Range – dB 100 98 96 94 92 90 0 100 200 300 Jitter – ps 400 500 600 VCC = 5 V fS = 44.1 kHz TA = 25°C Figure 27 All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted. 18 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 APPLICATION INFORMATION connection diagrams A basic connection diagram is shown in Figure 28, with the necessary power supply bypassing and decoupling components. Texas Instruments recommends using the component values shown in Figure 28 for all designs. A typical application diagram is shown in Figure 29. Texas Instruments’ PLL1700 is used to generate the system clock input at SCKI, as well as generating the clock for the audio signal processor. The use of series resistors (22 Ω to 100 Ω) is recommended for SCKI, LRCK, BCK, DATA1, DATA2, and DATA3. The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter which removes high-frequency noise from the digital signal, thus, reducing high-frequency emission. ML Microcontroller MC MD + DATA1 DATA2 DATA3 FMT1 FMT0 ZEROA PLL1700 SCKO3 +5 V Power Supply 10 µF 1 2 3 4 5 6 7 LPF LPF LPF 8 9 DATA1 DATA2 DATA3 FMT1 FMT0 ZEROA AGND VOUT5 VOUT6 PCM1606 SCKI BCK LRCK DEMP1 DEMP0 VCC VCOM VOUT4 VOUT3 VOUT2 20 19 18 17 16 15 14 13 12 11 + 10 µF LPF LPF LPF BCK LRCK DEMP1 DEMP0 10 VOUT1 Figure 28. Basic Connection Diagram www.ti.com 19 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 APPLICATION INFORMATION DIGITAL SECTION ANALOG SECTION µC/µP{ RSw 1 RS Audio DSP or Decoder 2 RS 3 RS 4 RS 5 RS 6 7 Buffer PLL1700 SCKO3} XT1 8 9 FMT1 FMT0 ZEROA AGND VOUT5 VOUT6 PCM1606 DEMP1 DEMP0 VCC VCOM VOUT4 VOUT3 VOUT2 17 16 15 14 13 12 11 + + + + + 27-MHz Master Clock + 10 µF 10 µF 10 µF 10 µF 10 µF 10 µF Output Low-Pass FiltersW Down Mix L R LF RF LS RS CTR SUB 5-V Analog 10 µF + 10 µF DATA3 LRCK 18 DATA2 BCK 19 DATA1 SCKI 20 10 VOUT1 0.1 µF + † Format and de-emphasis control can be provided by the DSP/decoder. ‡ Actual clock output used is determined by the application. § RS = 22 Ω to 100 Ω ¶ See the Application Information section of this data sheet for more information. Figure 29. Typical Application Diagram power supply and grounding The PCM1606 requires a 5-V supply. The 5-V supply is used to power the DAC analog output-filter circuitry, the digital filter, and the serial interface circuitry. Two capacitors are required for supply bypassing, as shown in Figure 29. These capacitors should be located as close as possible to the PCM1606 package. The 10-µF capacitors should be tantalum or aluminum electrolytic, while the 0.1-µF capacitors are ceramic (X7R type is recommended for surface-mount applications). 20 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 APPLICATION INFORMATION D/A output filter circuits Delta-sigma D/A converters utilize noise shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band noise must be low-pass filtered in order to provide optimal converter performance. This is accomplished by a combination of on-chip and external low-pass filtering. Figure 30 and Figure 31 show the recommended external low-pass active filter circuits for dual- and single-supply applications. These circuits are 2nd-order Butterworth filters using the multiple feedback (MFB) circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature. For more information regarding MFB active filter design, see your local Texas Instruments sales office. Because the overall system performance is defined by the quality of the D/A converters and their associated analog output circuitry, high-quality audio op amps are recommended for the active filters. Texas Instruments’ OPA2134 and OPA2353 dual op amps are shown in Figure 30 and Figure 31, and are recommended for use with the PCM1606. R2 R1 VIN C2 AV [ * R2 R1 R3 C1 2 3 – OPA2134 1 R4 VOUT + Figure 30. Dual-Supply Filter Circuit AV [ * R2 R1 R2 R1 VIN C2 R3 C1 2 3 – OPA2134 1 R4 VOUT + PCM1606 VCOM +C 2 10 µF – OPA337 + To Additional Low-Pass Filter Circuits Figure 31. Single-Supply Filter Circuit www.ti.com 21 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 APPLICATION INFORMATION PCB layout guidelines A typical PCB layout for the PCM1606 is shown in Figure 32. A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1606 should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital audio interface and control signals originating from the digital section of the board. Separate power supplies are recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital supply from contaminating the analog power supply and degrading the dynamic performance of the D/A converters. In cases where a common 5-V supply must be used for the analog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 33 shows the recommended approach for single-supply applications. Digital Power +VD DGND Analog Power AGND +5VA +VS –VS VCC Digital Logic and Audio Processor PCM1606 Output Circuits Digital Ground AGND Analog Ground Digital Section Analog Section Return Path for Digital Signals Figure 32. Recommended PCB Layout 22 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 APPLICATION INFORMATION PCB layout guidelines (continued) Power Supplies RF Choke or Ferrite Bead +5V AGND +VS –VS VDD VCC PCM1606 Output Circuits AGND Common Ground Digital Section Analog Section Figure 33. Single-Supply PCB Layout key performance parameters measurement This section provides information on how to measure key dynamic performance parameters for the PCM1606. In all cases, a System Two Cascade Plus by Audio Precision or equivalent audio measurement system is used to perform the testing. total harmonic distortion + noise Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio D/A converters, because it takes into account both harmonic distortion and all noise sources within a specified measurement bandwidth. The true rms value of the distortion and noise is referred to as THD+N. For the PCM1606 D/A converters, THD+N is measured with a full scale, 1-kHz digital sine wave as the test stimulus at the input of the DAC. The digital generator is set to 24-bit audio word length and a sampling frequency of 44.1 kHz or 96 kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the measurement system. The S/PDIF data is transmitted via coaxial cable to the digital audio receiver on the DEM–DAI1606 demo board. The receiver is then configured to output 24-bit data in either I2S or left-justified data format. The DAC audio interface format is programmed to match the receiver output format. The analog output is then taken from the DAC post filter and connected to the analog analyzer input of the measurement system. The analog input is band-limited using filters resident in the analyzer. The resulting THD+N is measured by the analyzer and displayed by the measurement system. www.ti.com 23 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 APPLICATION INFORMATION total harmonic distortion + noise (continued) Evaluation Board DEM-DAI1606 S/PDIF Receiver 2nd-Order Low-Pass Filter f–3 dB = 54 kHz PCM1606 S/PDIF Output Digital Generator 100% Full-Scale, 24-Bit, 1-kHz Sine Wave Analyzer and Display RMS Mode Band Limit Notch Filter HPF = 22 Hz† fc = 1 kHz LPF = 22 kHz† Option = 20-kHz Apogee Filter‡ † There is little difference in measured THD+N when using the various settings for these filters.. ‡ Required for THD+N test. Figure 34. Test Setup for THD+N Measurements dynamic range Dynamic range is specified as A-weighted, THD+N measured with a –60 dB of full-scale (FS), 1-kHz digital sine wave stimulus at the input of the D/A converter. This measurement is designed to give a good indicator of how the DAC performs given a low-level input signal. The measurement setup for the dynamic range measurement is shown in Figure 35, and is similar to the THD+N test setup discussed previously. The differences include the band limit filter selection, the additional A-weighting filter, and the –60-dB FS input level. idle channel signal-to-noise ratio The signal-to-noise ratio (SNR) test provides a measure of the noise floor of the D/A converter. The input to the D/A is all 0s data. This ensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (if present) can be observed and affect the SNR measurement. The dither function of the digital generator must also be disabled to ensure an all 0s data stream at the input of the D/A converter. The measurement setup for SNR is identical to that used for dynamic range, with the exception of the input signal level. (See the note provided in Figure 35). 24 www.ti.com PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 APPLICATION INFORMATION idle channel signal-to-noise ratio (continued) Evaluation Board DEM-DAI1606 S/PDIF Receiver 2nd-Order Low-Pass Filter f–3 dB = 54 kHz PCM1606 S/PDIF Output Digital Generator 0% Full-Scale, Dither Off (SNR) –60 dB FS, 1 kHz Sine Wave (Dynamic Range) Analyzer and Display RMS Mode A-Weight Filter† Band Limit Notch Filter HPF = 22 Hz fc = 1 kHz LPF = 22 kHz Option = A-Weighting† † Results without A-Weighting will be approximately 3 dB worse. Figure 35. Test Setup for Dynamic Range and SNR Measurements www.ti.com 25 PCM1606 SLES014B – OCTOBER 2001 – REVISED AUGUST 2002 MECHANICAL DATA DB (R-PDSO-G**) 28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M PLASTIC SMALL-OUTLINE 0,15 NOM 5,60 5,00 8,20 7,40 Gage Plane 1 A 14 0°– 8° 0,25 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** DIM A MAX 14 16 20 24 28 30 38 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065 /D 09/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15 mm. Falls within JEDEC MO-150 26 www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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