Not Recommended for New Designs
®
PCM49%
171
7
PCM1717
®
FPO
For most current data sheet and other product
information, visit www.burr-brown.com
Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● ACCEPTS 16- OR 18-BIT INPUT DATA
The PCM1717 is a complete low cost stereo, audio
digital-to-analog converter, including digital interpolation filter, 3rd-order delta-sigma DAC, and analog
output amplifiers. PCM1717 is fabricated on a highly
advanced 0.6µ CMOS process. PCM1717 accepts
16- or 18-bit normal input data format, or 16- or
18-bit I 2S data format.
● COMPLETE STEREO DAC:
8X Oversampling Digital Filter
Multi-Level Delta-Sigma DAC
Analog Low Pass Filter
Output Amplifier
● HIGH PERFORMANCE:
–90dB THD+N
96dB Dynamic Range
100dB SNR
The digital filter performs an 8X interpolation function, as well as special functions such as soft mute,
digital attenuation, and digital de-emphasis. The digital filter features –35dB stop band attenuation and
±0.17dB ripple in the pass band.
● SYSTEM CLOCK: 256fs or 384fs
● WIDE POWER SUPPLY: +2.7V to +5.5V
PCM1717 is suitable for a wide variety of cost-sensitive
consumer applications where good performance is required. Its low cost, small size, and single +5V power
supply make it ideal for automotive CD players, bookshelf CD players, BS tuners, keyboards, MPEG audio,
MIDI applications, set-top boxes, CD-ROM drives,
CD-Interactive, and CD-Karaoke systems.
● SELECTABLE FUNCTIONS:
Soft Mute
Digital Attenuation (256 Steps)
Digital De-emphasis
Output Mode: L, R, Mono, Mute
● SMALL SSOP-20 PACKAGE
BCKIN
LRCIN
DIN
ML/MUTE
MC/DM0
MD/DM1
Serial
Input
I/F
8X Oversampling
Digital Filter with
Multi Function
Control
Mode
Control
I/F
Multi-level
Delta-Sigma
Modulator
DAC
Multi-level
Delta-Sigma
Modulator
DAC
Output Amp
and
Low-pass
Filter
Output Amp
and
Low-pass
Filter
VOUTL
D/C_L
VOUTR
D/C_R
ZERO
BPZ-Cont.
MODE
Open Drain
RSTB
Reset
Clock/OSC Manager
XTI XTO
Power Supply
CLKO
VCC
AGND
VDD
DGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1995 Burr-Brown Corporation
SBAS038
PDS-1289D
1
Printed in U.S.A. March, 2000
PCM1717
Not Recommended for New Designs
SPECIFICATIONS
All specifications at +25°C, +VCC = +VDD = +5V, fs = 44.1kHz, and 16-bit input data, SYSCLK = 384fs, unless otherwise noted. Measurement bandwidth is 20kHz.
PCM1717E
PARAMETER
CONDITIONS
MIN
RESOLUTION
TYP
16
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic Level:
VIH(2)
VIL(2)
VIH(3)
VIL(3)
VIH(4)
VIL(4)
Input Logic Current:
IIH(5)
IIL(5)
IIH(6)
IIL(6)
IIH(4)
IIL(4)
Output Logic Level: (+VDD = +5V)
VOH(7)
VOL(7)
VOL(8)
Interface Format
Data Format
Sampling Frequency
System Clock Frequency
DC ACCURACY
Gain Error
Gain Mismatch Channel-to-Channel
Bipolar Zero Error
–6.0
–120
–2
0.02
40
–40
µA
µA
µA
µA
µA
µA
1.0
1.0
V
V
V
70% of VDD
30% of VDD
64% of VDD
VIN = 3.2V
VIN = 1.4V
IOH = –5mA
IOL = +5mA
IOL = +5mA
3.8
256fs/384fs
Selectable Normal, I2S
16/18 Bits MSB First Binary Two’s Complement
32
44.1
48
8.192/12.288 11.2896/16.9344 12.288/18.432
kHz
MHz
±5.0
±5.0
VO = 1/2 VCC at Bipolar Zero
±1.0
±1.0
±30
% of FSR
% of FSR
mV
–90
–34
96
100
97
±0.5
–80
dB
dB
dB
dB
dB
dB
VCC = +3V, f = 991Hz
EIAJ, A-weighted
EIAJ, A-weighted
90
92
90
–86
91
94
EIAJ, A-weighted
EIAJ, A-weighted
dB
dB
dB
±0.17
–35
0.445
(fs = 32kHz ~ 48kHz)
0.555
–0.2
+0.55
11.125/fs
FS (0dB) OUT
50% of VCC
+VCC
+VCC
+VCC
+VCC
+VCC
+VDD
= +VDD
= +VDD
= +VDD
= +VDD
+2.7
+2.7
=
=
=
=
+5V
+3V
+5V
+3V
TEMPERATURE RANGE
Operation
Storage
18.0
9.0
90
27
–25
–55
dB
dB
fs
fs
dB
sec
Vp-p
kΩ
V
62% of VCC
5
POWER SUPPLY REQUIREMENTS
Voltage Range:
Power Dissipation
28% of VDD
V
V
V
V
V
V
30% of VDD
DYNAMIC PERFORMANCE(1)
THD+N at FS (0dB)
Dynamic Range
Signal-To-Noise Ratio
Supply Current: +ICC +IDD(9)
Bits
70% of VDD
VCC = +5V, f = 991Hz
ANALOG OUTPUT
Voltage Range
Load Impedance
Center Voltage
UNITS
18
CMOS
DYNAMIC PERFORMANCE(1)
THD+N at FS (0dB)
THD+N at –60dB
Dynamic Range
Signal-To-Noise Ratio
Channel Separation
Level Linearity Error (–90dB)
DIGITAL FILTER PERFORMANCE
Pass Band Ripple
Stop Band Attenuation
Pass Band
Stop Band
De-emphasis Error
Delay Time (Latency)
MAX
+5.5
+5.5
25.0
15.0
125
45
VDC
VDC
mA
mA
mW
mW
+85
+100
°C
°C
NOTES: (1) Tested with Shibasoku #725 THD. Meter 400Hz HPF, 30kHz LPF On, Average Mode with 20kHz bandwidth limiting. (2) Pins 4, 5, 6, 14: LRCIN, DIN,
BCKIN, FORMAT. (3) Pins 15, 16, 17, 18: RSTB, DM0, DM1, MUTE (Schmitt trigger input). (4) Pin 1: XTI. (5) Pins 15, 16, 17, 18: RSTB, DM0, DM1, MUTE (if
pull-up resistor is used). (6) Pins 4, 5, 6: LRCIN, DIN, BCKIN (if pull-up resistor is not used). (7) Pin 19: CLKO. (8) Pin 7: ZERO. (9) No load on pins 19 (CLKO)
and 20 (XTO).
®
PCM1717
2
Not Recommended for New Designs
PIN CONFIGURATION
PIN ASSIGNMENTS
PIN
NAME
FUNCTION
Data Input Interface Pins
XTI
1
20
XTO
4
LRCIN
Sample Rate Clock Input. Controls the update rate (fs).
5
DIN
Serial Data Input. MSB first, right justified (Sony format)
or I2S (Philips). Contains a frame of 16- or 18-bit data.
BCKIN
Bit Clock Input. Clocks in the data present on DIN input.
DGND
2
19
CLKO
VDD
3
18
ML/MUTE
6
Mode Control and Clock Signals
LRCIN
4
17
MC/DM1
DIN
5
16
MD/DM0
BCKIN
6
15
RSTB
ZERO
7
14
MODE
D/C_R
8
13
DC_L
VOUTR
9
12
VOUTL
AGND 10
11
VCC
1
XTI
Oscillator Input (External Clock Input). For an internal
clock, tie XTI to one side of the crystal oscillator. For an
external clock, tie XTI to the output of the chosen
external clock.
14
MODE
Operation Mode Select. For Software Mode, tie Mode
“HIGH”. For Hardware Mode, tie Mode “LOW”.
16
MD/DM0
Mode Control for Data Input or De-emphasis. When
“HIGH” MD is selected, and a “LOW” selects DM0.
17
MC/DM1
Mode Control for BCKIN or De-emphasis. When “HIGH”,
MC is selected, and a “LOW” selects DM1.
18
ML/MUTE
Mode Control for Strobe Clock or Mute. When “HIGH”,
ML is selected, and a “LOW” selects mute.
19
CLKO
20
XTO
ABSOLUTE MAXIMUM RATINGS
Buffered Output of Oscillator. Equivalent to XTI.
Oscillator Output. When using the internal clock, tie to
the opposite side (from pin 1) of the crystal oscillator.
When using an external clock, leave XTO open.
Operational Controls and Flags
Power Supply Voltage ...................................................................... +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V)
Power Dissipation .......................................................................... 200mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) .................................................. +260°C
Thermal Resistance, θJA ....................................................................................... +70°C/W
7
ZERO
Infinite Zero Detection Flag, open drain output. When
the zero detection feature is muting the output, ZERO
is “LOW”. When non-zero input data is present, ZERO
is in a high impedance state. When the input data is
continuously zero for 65.536 BCKIN cycles, zero will be
low.
15
RSTB
Resets DAC operation with an active “LOW” pulse.
Analog Output Functions
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
8
D/C_R
Right Channel Output Amplifier Common. Bypass to
ground with 10µF capacitor.
9
VOUTR
Right Channel Analog Output. VOUT max = 0.62 x VCC.
12
VOUTL
Left Channel Analog Output. VOUT max = 0.62 x VCC.
13
D/C_L
Left Channel Output Amplifier Common. Bypass to
ground with 10µF capacitor.
Power Supply Connections
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
2
DGND
3
VDD
10
AGND
11
VCC
Digital Ground.
Digital Power Supply (+5V).
Analog Ground.
Analog Power Supply (+3V).
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
PCM1717E
SSOP-20
334-1
–25°C to +85°C
PCM1717E
"
"
"
"
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PCM1717E
PCM1717E/2K
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “PCM1717E/2K” will get a single 2000-piece Tape and Reel.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN
product for use in life support devices and/or systems.
®
3
PCM1717
Not Recommended for New Designs
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VCC = +VDD = +5V, fs = 44.1kHz, and 16-bit input data, SYSCLK = 384fs, unless otherwise noted.
DYNAMIC PERFORMANCE
THD+N vs VCC, VDD
fIN = 1kHz, 384fS
–30
–60dB
–88
–34
–90
–92
98
Dynamic Range (dB)
THD+N at FS (dB)
–86
100
THD+N at –60dB (dB)
–84
DYNAMIC RANGE vs INPUT DATA
fIN = 1kHz
–38
96
384fS
94
92
0dB
–94
90
3.0
3.5
4.0
4.5
5.0
5.5
16-Bit
Input Data
THD+N vs TEMPERATURE
fIN = 1kHz, 384fS
THD+N vs INPUT DATA
fIN = 1kHz, FS (0dB)
–30
–34
–60dB
–90
–92
–86
THD+N (dB)
–88
–84
THD+N at –60dB (dB)
–86
–38
–88
384fS
–90
–92
256fS
0dB
–90
–25
18-Bit
VCC, VDD (V)
–84
–94
0
25
50
75
85
100
16-Bit
Temperature (°C)
DYNAMIC RANGE AND SNR vs VCC, VDD
fIN = 1kHz, 384fS
100
SNR
98
96
Dynamic
Range
94
92
90
3.0
3.5
4.0
VCC, VDD
®
PCM1717
18-Bit
Input Data
(dB)
THD+N at FS (dB)
256fS
4
4.5
5.0
5.5
Not Recommended for New Designs
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VCC = +VDD = +5V, fs = 44.1kHz, and 16-bit input data, SYSCLK = 384fs, unless otherwise noted.
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTIC
PASSBAND RIPPLE CHARACTERISTIC
0
–20
–0.2
–40
–0.4
dB
dB
0
–60
–0.6
–80
–0.8
–100
–1
0 0.4536fS
1.3605fS
2.2675fS
3.1745fS
4.0815fS
0
0.1134fS
Frequency (Hz)
5k
10k
15k
Frequency (Hz)
20k
25k
Level (dB)
Error (dB)
10k
15k
20k
3628
0
25k
Level (dB)
Error (dB)
10k
15k
20k
14512
4999.8375
9999.675
Frequency (Hz)
14999.5125
19999.35
DE-EMPHASIS ERROR (48kHz)
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
0
–2
–4
–6
–8
–10
–12
5k
10884
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
Frequency (Hz)
0
7256
Frequency (Hz)
DE-EMPHASIS ERROR (44.1kHz)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
5k
0.4535fS
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
0
–2
–4
–6
–8
–10
–12
0
0.3402fS
DE-EMPHASIS ERROR (32kHz)
Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (32kHz)
0
–2
–4
–6
–8
–10
–12
0
0.2268fS
Frequency (Hz)
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
25k
Frequency (Hz)
5442
10884
Frequency (Hz)
16326
21768
®
5
PCM1717
Not Recommended for New Designs
SYSTEM CLOCK
and system clocks is greater than 6 bit clocks (BCKIN), the
synchronization is performed internally. While the synchronization is processing, the analog output is forced to a DC
level at bipolar zero. The synchronization typically occurs in
less than 1 cycle of LRCIN.
The system clock for PCM1717 must be either 256fS or
384fS, where fS is the audio sampling frequency (typically
32kHz, 44.1kHz, or 48kHz). The system clock is used to
operate the digital filter and the modulator.
The system clock can be either a crystal oscillator placed
between XTI (pin 1) and XTO (pin 20), or an external clock
input to XTI. If an external system clock is used, XTO is
open (floating). Figure 1 illustrates the typical system clock
connections.
DATA INTERFACE FORMATS
Digital audio data is interfaced to PCM1717 on pins 4, 5,
and 6—LRCIN (left-right clock), DIN (data input) and
BCKIN (bit clock). PCM1717 can accept both normal and
I2S data formats. Normal data format is MSB first, two’s
complement, right-justified. I2S data is compatible with
Philips serial data protocol. In the I2S format, the data is 16or 18-bit, selectable by bit 0 on Register 3 (Software Control
Mode). In the Hardware Mode, PCM1717 can only function
with 16-bit normal data. Figures 5 through 9 illustrate timing
and input formats.
PCM1717 has a system clock detection circuit which automatically senses if the system clock is operating at 256fS or
384fS. The system clock should be synchronized with LRCIN
(pin 4) clock. LRCIN (left-right clock) operates at the
sampling frequency fs. In the event these clocks are not
synchronized, PCM1717 can compensate for the phase difference internally. If the phase difference between left-right
CLKO
CLKO
Internal System Clock
C1
X’tal
Internal System Clock
XTI
External Clock
XTI
C2
XTO
C1, C2 = 10 to 20pF
XTO
PCM1717E
PCM1717E
CRYSTAL RESONATOR CONNECTION
EXTERNAL CLOCK INPUT
XTO pin = No Connection
FIGURE 1. Internal Clock Circuit Diagram and Oscillator Connection.
tXTIH
1/256fS or 1/384fS
64% OF VDD
28% OF VDD
tXTIL
External System Clock High
External System Clock Low
t XTIH
tXTIL
FIGURE 2. External Clock Timing Requirements.
®
PCM1717
6
10ns (min)
10ns (min)
Not Recommended for New Designs
Reset
PCM1717 has both internal power on reset circuit and the
RSTB-pin (pin 15) which accepts external forced reset by
RSTB = LOW. For internal power on reset, initialize (reset)
is done automatically at power on VDD >2.2V (typ). During
internal reset = LOW, the output of the DAC is invalid and
the analog outputs are forced to VCC /2. Figure 3 illustrates
the timing of internal power on reset.
For the RSTB-pin, PSTB-pin accepts external forced reset by
RSTB = L. During RSTB = L, the output of the DAC is
invalid and the analog outputs are forced to VCC /2 after
internal initialize (1024 system clocks count after RSTB = H.)
Figure 4 illustrates the timing of RSTB-pin reset.
2.6V
VCC/VDD 2.2V
1.8V
Reset
Reset Removal
Internal Reset
1024 system (= XTI) clocks
XTI Clock
FIGURE 3. Internal Power-On Reset Timing.
RSTB-pin
50% of VDD
tRST(1)
Reset
Reset Removal
Internal Reset
1024 system (XTI) clocks
XTI Clock
NOTE: (1) tRST = 20ns min
FIGURE 4. RSTB-Pin Reset Timing.
®
7
PCM1717
Not Recommended for New Designs
OPERATIONAL CONTROL
DIGITAL DE-EMPHASIS (Pins 16 and 17)
Pins 16 and 17 are used as a two-bit parallel register to
control de-emphasis modes:
PCM1717 can be controlled in two modes. Software Mode
allows the user to control operation with a 16-bit serial
register. Hardware Mode allows the user to hard-wire operation of PCM1717 using four parallel wires. The MODE pin
determines which mode PCM1717 is in; a LOW level on pin
14 places PCM1717 in Hardware Mode, and a HIGH on pin
14 places PCM1717 in Software Mode.
MODE (Pin 14)
Selected Mode
Pin 16
Pin 17
Pin 18
“HIGH”
“LOW”
Software Mode
Hardware Mode
MD
DM0
MC
DM1
ML
MUTE
PIN 16
PIN 17
0
1
0
1
0
0
1
1
MODE
De-emphasis
De-emphasis
De-emphasis
De-emphasis
disabled
enabled at 48kHz
enabled at 44.1kHz
enabled at 32kHz
RESET MODE (Pin 15)
A LOW level on pin 15 will force the digital filters, modulators and mode controls into a reset (disable) mode. While
this pin is held low, the output of PCM1717 will be forced
to VCC/2 (Bipolar Zero). Bringing pin 15 HIGH will initialize all DAC functions, and allow for normal operation.
Table I indicates which functions are selectable within the
user’s chosen mode. All of the functions shown are selectable in the Software Mode, but only soft mute and deemphasis control may be selected in the Hardware Mode.
SOFTWARE MODE
(Pin 14 = “1”)
The Software Mode uses a three-wire interface on pins 16,
17 and 18. Pin 17 (MC) is used to clock in the serial control
data, pin 18 (ML) is used to synchronize the serial control
data, and pin 16 (MD) is used to latch in the serial control
register. There are four distinct registers, with bits 9 and 10
(of 16) determining which register is in use.
SOFTWARE
HARDWARE
MODE
DEFAULT
MODE
DEFAULT
SELECTABLE
SELECTABLE
FUNCTION
Input Data Format
Normal Format
I2S Format
Input Resolution
16 Bits
18 Bits
LRCIN Polarity
L/R = High/Low
L/R = Low/High
Yes
Normal
No
Normal Only
Normal
16 Bits
No
16 Bits Only
16 Bits
Yes
Yes
L/R = H/L
De-emphasis Control
32kHz
44.1kHz
48kHz
OFF
Soft Mute
Digital Attenuation
Analog Output Mode
Infinite Zero Detection
DAC Operation Control
Yes
No
L/R = H/L
Only
Yes
OFF
Yes
Yes
Yes
Yes
Yes
REGISTER CONTROL (Bits 9, 10)
L/R = H/L
OFF
0dB
Stereo
Disabled
ON
OFF
Yes
No
No
No
No
OFF
0dB
Stereo
Disabled
ON
REGISTER
B9 (A0)
B10 (A1)
0
1
2
3
0
1
0
1
0
0
1
1
Control data timing is shown in Figure 6. ML is used to latch
the data from the control registers. After each register’s
contents are checked in, ML should be taken low to latch in
the data. A “res” in the register indicates that location is
reserved for factory use. When loading the registers, the
“res” bits should be set LOW.
TABLE I. Feature Selections by Mode.
HARDWARE MODE
REGISTER 0
(Pin 14 = “0”)
This mode is controlled by logic levels present on pins 15,
16, 17 and 18. Hardware Mode allows for control of soft
mute, digital de-emphasis and disable ONLY. Other functions such as attenuation, I/O format and infinite zero detect
can only be controlled in the Software Mode.
B15 B14 B13 B12 B11 B10 B9 B8
Register 0 is used to control left channel attenuation. Bits
0-7 (AL0-AL7) are used to determine the attenuation level.
The level of attenuation is given by:
SOFT MUTE (Pin 18)
A LOW level on pin 18 will force both channels to be muted;
a HIGH level on pin 18 will allow for normal operation.
ATT = [20log10 (ATT_DATA/255)] dB
®
PCM1717
B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
8
Not Recommended for New Designs
ATTENUATION DATA LOAD CONTROL
Bits 3 (OPE) and 4 (IZD) are used to control the infinite zero
detection features. Tables II through IV illustrate the relationship between IZD, OPE, and RSTB (reset control):
Bit 8 (LDL) is used to control the loading of attenuation data
in B0:B7. When LDL is set to 0, attenuation data will be
loaded into AL0:AL7, but it will not affect the attenuation
level until LDL is set to 1. LDR in Register 1 has the same
function for right channel attenuation. The attenuation level
is given by:
DATA INPUT
DAC OUTPUT
Zero
Forced to BPZ(1)
Other
Normal
IZD = 1
IZD = 0
ATT = 20log (y/256) (dB), where y = x, when 0 ≤ x ≤ 254
Zero(2)
Other
Normal
TABLE II. Infinite Zero Detection (IZD) Function.
y = x + 1, when x = 255
X is the user-determined step number, an integer value
between 0 and 255.
DATA INPUT
DAC OUTPUT
SOFTWARE MODE
INPUT
Enabled
OPE = 1
Example:
let x = 255
Zero
OPE = 0
255 + 1
ATT = 20 log
= 0dB
256
Zero
Forced to BPZ(1)
Other
Forced to BPZ(1)
Enabled
Zero
Controlled by IZD
Enabled
Other
Normal
Enabled
TABLE III. Output Enable (OPE) Function.
DATA INPUT
DAC OUTPUT
SOFTWARE
MODE
INPUT
Zero
Controlled by OPE and IZD
Enabled
Other
Controlled by OPE and IZD
Enabled
Zero
Forced to BPZ(1)
Disabled
Other
Forced to BPZ(1)
Disabled
let x = 254
254
ATT = 20 log
= –0. 068dB
256
RSTB = “HIGH”
let x = 1
RSTB = “LOW”
1
= –48.16dB
ATT = 20 log
256
TABLE IV. Reset (RSTB) Function.
NOTE: (1) ∆∑ is disconnected from output amplifier. (2) ∆∑ is connected to
output amplifier.
let x = 0
0
= –∞
ATT = 20 log
256
OPE controls the operation of the DAC: when OPE is
“LOW”, the DAC will convert all non-zero input data. If the
input data is continuously zero for 65,536 cycles of BCKIN,
the output will only be forced to zero only if IZD is “HIGH”.
When OPE is “HIGH”, the output of the DAC will be forced
to bipolar zero, irrespective of any input data.
REGISTER 1
B15 B14 B13 B12 B11 B10 B9 B8
res res res res res
B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
IZD controls the operation of the zero detect feature: when
IZD is “LOW”, the zero detect circuit is off. Under this
condition, no automatic muting will occur if the input is
continuously zero. When IZD is “HIGH”, the zero detect
feature is enabled. If the input data is continuously zero for
65,536 cycle of BCKIN, the output will be immediately
forced to a bipolar zero state (VCC/2). The zero detection
feature is used to avoid noise which may occur when the
input is DC. When the output is forced to bipolar zero, there
may be an audible click. PCM1717 allows the zero detect
feature to be disabled so the user can implement an external
muting circuit.
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0-7 (AR0-AR7) control the level of
attenuation.
REGISTER 2
B15 B14 B13 B12 B11 B10 B9 B8
res res res res res A1
B7
B6 B5
B4
B3
B2
B1
B0
A0 res res res res IZD OPE DM1 DM0 MUTE
Register 2 is used to control soft mute, digital de-emphasis,
disable, and infinite zero detect. Bit 0 is used for soft mute;
a HIGH level on bit 0 will cause the output to be muted.
Bits 1 and 2 are used to control digital de-emphasis as
shown below:
BIT 1 (DM0)
BIT 2 (DM1)
0
0
De-emphasis disabled
1
0
De-emphasis enabled at 48kHz
0
1
De-emphasis enabled at 44.1kHz
1
1
De-emphasis enabled at 32kHz
REGISTER 3
B15 B14 B13 B12 B11 B10 B9 B8
res res res res res A1
DE-EMPHASIS
B7
B6 B5
B4
B3
A0 res PL3 PL2 PL1 PL0 ATC
B2
B1
IW LRP
B0
IIS
Register 3 is used to select the I/O data formats. Bit 0 (IIS)
is used to control the input data format. If the input data
source is normal (16- or 18-bit, MSB first, right-justified),
set bit 0 “LOW”. If the input format is IIS, set bit 0 “HIGH”.
®
9
PCM1717
Not Recommended for New Designs
1 f/s
Left-channel Data
Right-channel Data
LRCIN (pin 4)
BCKIN (pin 6)
Audio Data Word = 16-Bit
MSB
DIN (pin 5)
1
14 15 16
Audio Data Word = 18-Bit
MSB
DIN (pin 5)
1
16 17 18
LSB
2
3
14
15 16
16
17 18
MSB
LSB
2
3
LSB
1
2
2
3
3
14
15 16
16
17 18
MSB
1
LSB
FIGURE 5. “Normal” Data Input Timing.
1 f/s
Left-channel Data
Right-channel Data
LRCIN (pin 4)
BCKIN (pin 6)
Audio Data Word = 16-Bit
MSB
DIN (pin 5)
1
Audio Data Word = 18-Bit
MSB
1
DIN (pin 5)
LSB
2
3
2
3
14
MSB
15 16
1
LSB
16
LSB
2
3
2
3
14
15 16
MSB
17 18
1
1
2
1
2
LSB
16
17 18
FIGURE 6. “I2S” Data Input Timing.
Bit 3 is used as an attenuation control. When bit 3 is set
HIGH, the attenuation data on Register 0 is used for both
channels, and the data in Register 1 is ignored. When bit 3
is LOW, each channel has separate attenuation data.
50% of VDD
LRCIN
tBCH
tBCL
tLB
Bits 4 through 7 are used to determine the output format, as
shown in Table V:
50% of VDD
BCKIN
tBL
tBCY
DIN
50% of VDD
tDH
tDS
BCKIN Pulsewidth (High Level)
BCKIN Pulsewidth (Low Level)
BCKIN Pulse Cycle Time
BCKIN Rising Edge ➝ LRCIN Edge
LRCIN Edge ➝ BCKIN Rising Edge
DIN Setup Time
DIN Hold Time
tBCH
tBCL
tBCY
tBL
tLB
tDS
tDH
50ns (min)
50ns (min)
100ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
FIGURE 7. Data Input Timing.
Bit 1 is used to select the polarity of LRCIN (sample rate
clock). When bit 1 is LOW, a HIGH state on LRCIN is used
for the left channel, and a LOW state on LRCIN is used for
the right channel. When bit 1 is HIGH the polarity of LRCIN
is reversed.
PL1
PL2
PL3
Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
REVERSE
STEREO
MONO
TABLE V. PCM1717 Output Mode Control.
REGISTER RESET STATES
After reset, each register is set to a predetermined state:
Bit 2 is used to select the input word length. When bit 2 is
LOW, the input word length is set for 16 bits; when bit 2 is
HIGH, the input word length is set for 18 bits.
Register
Register
Register
Register
®
PCM1717
PL0
10
0
1
2
3
0000
0000
0000
0000
0000
0010
0100
0110
1111
1111
0000
1001
1111
1111
0000
0000
Not Recommended for New Designs
ML (pin 18)
MC (pin 17)
MD (pin 16)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
tMLS
tMLH
50% of VDD
ML
tMCH
tMCY
tMCL
tMLL
tMHH
MC
50% of VDD
50% of VDD
MD
tMDS
tMDH
MC Pulse Cycle
MC Pulsewidth “L”
MC Pulse Cycle “H”
MD Setup Time
MD Hold Time
ML Setup Time
ML Hold Time
ML Pulsewidth “L”
ML High Level Time
tMCY
tMCL
t MCH
tMDS
tMDH
tMLS
tMLH
tMLL
t MHH
100ns (min)
50ns (min)
50ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns + 1SYSCLK (min)
30ns + 1SYSCLK (min)
FIGURE 8. Control Data Timing in Software Mode Control.
50% of VDD
RSTB
RSTB Pulsewidth
tRST
20ns (min)
FIGURE 9. External Reset Timing.
0.1µF ~ 10µF
Bypass Capacitor
+5V Analog Power Supply
2
10pF ~ 22pF
1
DGND
XTI
3
VDD
FOUT = Inverted XTI (1 pin)
to Other System
CLKO 19
20 XTO
10pF ~ 22pF
PCM
Audio Data
Processor
4
LRCIN
5
DIN
6
BCKIN
VOUTR
9
D/C_R
8
Post
Low Pass
Filter
+
+
Mode Control
14 MODE
D/C_L 13
18 ML/MUTE
VOUTL 12
(optional)
10µF
10µF
Post
Low Pass
Filter
VDD
Control
Processor
17 MC/DM1
16 MD/DM0
15 RSTB
(optional)
4.7kΩ
ZERO
AGND
VCC
10
11
Reset
7
To External Mute Circuit
0.1µF ~ 10µF
Bypass Capacitor
FIGURE 10. Typical Connection Diagram of PCM1717.
®
11
PCM1717
Not Recommended for New Designs
POWER SUPPLY
CONNECTIONS
PCM1717 has two power supply connections: digital (VDD)
and analog (VCC). Each connection also has a separate
ground. If the power supplies turn on at different times, there
is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection
between the digital and analog power supplies. If separate
supplies are used without a common connection, the delta
between the two supplies during ramp-up time must be less
than 0.6V.
A block diagram of the 5-level delta-sigma modulator is
shown in Figure 12. This 5-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8-times interpolation filter is 48fS for
a 384fS system clock, and 64fS for a 256fS system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 13.
An application circuit to avoid a latch-up condition is shown
in Figure 11.
Digital
Power Supply
Analog
Power Supply
VDD
VCC
DGND
AGND
3rd-ORDER ∆Σ MODULATOR
20
0
–20
–40
Gain (–dB)
FIGURE 11. Latch-up Prevention Circuit.
BYPASSING POWER SUPPLIES
–60
–80
–100
The power supplies should be bypassed as close as possible
to the unit. Refer to Figure 10 for optimal values of bypass
capacitors.
–120
–140
–160
0
THEORY OF OPERATION
+
+
8fS
18-Bit
10
FIGURE 13. Quantization Noise Spectrum.
+
Z–1
+
+
–
+
Z–1
–
+
+
5-level Quantizer
+
4
3
Out
48fS (384fS)
64fS (256fS)
2
1
0
FIGURE 12. 5-Level ∆Σ Modulator Block Diagram.
®
PCM1717
15
Frequency (kHz)
The delta-sigma section of PCM1717 is based on a 5-level
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level deltasigma format.
In
5
12
Z–1
20
25
Not Recommended for New Designs
APPLICATION
CONSIDERATIONS
The performance of the internal low pass filter from DC to
24kHz is shown in Figure 14. The higher frequency rolloff
of the filter is shown in Figure 15. If the user’s application
has the PCM1717 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 16. For some applications, a
passive RC filter or 2nd-order filter may be adequate.
DELAY TIME
There is a finite delay time in delta-sigma converters. In A/D
converters, this is commonly referred to as latency. For a
delta-sigma D/A converter, delay time is determined by the
order number of the FIR filter stage, and the chosen sampling
rate. The following equation expresses the delay time of
PCM1717:
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
1.0
TD = 11.125 x 1/fS
0.5
For fS = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs
dB
Applications using data from a disc or tape source, such as
CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is
important for total delay time to be less than 2ms.
0
–0.5
–1.0
INTERNAL RESET
When power is first applied to PCM1717, an automatic reset
function occurs after 1,024 cycles of XTI clock. Refer to
Table I for default conditions. During the first 1,024 cycles
of XTI clock, PCM1717 cannot be programmed (Software
Control). Data can be loaded into the control registers during
this time, and after 1,204 cycles of XTI clock, a "LOW" on
ML (pin 18) will initiate programming.
20
100
1k
Frequency (Hz)
10k
24k
FIGURE 14. Low Pass Filter Frequency Response.
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
dB
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1717 using a 20kHz low pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low pass filter removes out of band
noise. Although it is not audible, it may affect dynamic
specification numbers.
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
FIGURE 15. Low Pass Filter Frequency Response.
GAIN vs FREQUENCY
6
90
+
VSIN
10kΩ
10kΩ
680pF
OPA604
10kΩ
0
–34
–90
–54
–180
Phase (°)
1500pF
Gain (dB)
Gain
–14
Phase
100pF
–
–74
–270
–94
–360
100
1k
10k
Frequency (Hz)
100k
1M
FIGURE 16. 3rd-Order LPF.
®
13
PCM1717
Not Recommended for New Designs
Test Disk
Shibasoku #725
Through
Lch
CD
Player
Digital
DAI
DEMPCM1717
PGA
THD
Meter
0dB/60dB
30KHz LPF on
11th-order
LPF
Rch
For test of S/N ratio and Dynamic Range, A-filter ON.
FIGURE 17. Test Block Diagram.
TEST CONDITIONS
Figure 17 illustrates the actual test conditions applied to
PCM1717 in production. The 11th-order filter is necessary
in the production environment for the removal of noise
resulting from the relatively long physical distance between
the unit and the test analyzer. In most actual applications, the
3rd-order filter shown in Figure 16 is adequate. Under
normal conditions, THD+N typical performance is –70dB
with a 30kHz low pass filter (shown here on the THD
meter), improving to –89dB when the external 20kHz 11thorder filter is used.
110
Dynamic Range (dB)
105
100
Multi-level
95
90
85
80
75
PWM
70
65
EVALUATION FIXTURES
60
0
Three evaluation fixtures are available for PCM1717.
100
200
300
400
500
600
Clock Jitter (ps)
DEM-PCM1717
FIGURE 18. Simulation Results of Clock Jitter Sensitivity.
This evaluation fixture is primarily intended for quick evaluation of the PCM1717’s performance. DEM-PCM1717 can
accept either an external clock or a user-installed crystal
oscillator. All of the functions can be controlled by on-board
switches. DEM-PCM1717 does not contain a receiver chip
or an external low pass filter. DEM-PCM1717 requires a
single +5V power supply.
2
1
0
OUT-OF-BAND NOISE CONSIDERATIONS
Delta-sigma DACs are by nature very sensitive to jitter on
the master clock. Phase noise on the clock will result in an
increase in noise, ultimately degrading dynamic range. It is
difficult to quantify the effect of jitter due to problems in
synthesizing low levels of jitter. One of the reasons deltasigma DACs are prone to jitter sensitivity is the large
quantization noise when the modulator can only achieve two
discrete output levels (0 or 1). The multi-level delta-sigma
DAC has improved theoretical SNR because of multiple
output states. This reduces sensitivity to jitter. Figure 18
contrasts jitter sensitivity between a one-bit PWM type DAC
and multi-level delta-sigma DAC. The data was derived
using a simulator, where clock jitter could be completely
synthesized.
–1
48fs
2
FIGURE 19. Simulation Method for Clock Jitter.
®
PCM1717
14.4ps
14
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
PCM1717E-3
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
PCM1717E-3G4
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2016
Addendum-Page 2
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