PCM1794A

Burr Brown Products from Texas Instruments PCM1794A SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 24 BIT, 192 kHz SAMPLING, ADVANCED SEGMENT, AUDIO STEREO DIGITAL TO ANALOG CONVERTER FEATURES D 24-Bit Resolution D Analog Performance: − Dynamic Range: 132 dB (9 V RMS, Mono) 129 dB (4.5 V RMS, Stereo) 127 dB (2 V RMS, Stereo) − THD+N: 0.0004% D Dual-Supply Operation: − 5-V Analog, 3.3-V Digital D 5-V Tolerant Digital Inputs D Small 28-Lead SSOP Package APPLICATIONS D A/V Receivers D DVD Players D Musical Instruments D HDTV Receivers D Car Audio Systems D Digital Multitrack Recorders D Other Applications Requiring 24-Bit Audio DESCRIPTION The PCM1794A is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1794A provides balanced current outputs, allowing the user to optimize analog performance externally. Sampling rates up to 200 kHz are supported. D Differential Current Output: 7.8 mA p-p D 8× Oversampling Digital Filter: − Stop-Band Attenuation: –130 dB − Pass-Band Ripple: ±0.00001 dB D Sampling Frequency: 10 kHz to 200 kHz D System Clock: 128, 192, 256, 384, 512, or D Accepts 16- and 24-Bit Audio Data D PCM Data Formats: Standard, I2S, and Left-Justified 768 fS With Autodetect D Optional Interface Available to External Digital Filter or DSP D D D D Digital De-Emphasis Digital Filter Rolloff: Sharp or Slow Soft Mute Zero Flag This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2006, Texas Instruments Incorporated PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE 28DB OPERATION TEMPERATURE RANGE –25°C to 85°C PACKAGE MARKING PCM1794A ORDERING NUMBER PCM1794ADB PCM1794ADBR TRANSPORT MEDIA Tube Tape and reel PCM1794ADB 28-lead SSOP ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PCM1794A Supply voltage VCC1, VCC2L, VCC2R VDD –0.3 V to 6.5 V –0.3 V to 4 V ±0.1 V ±0.1 V –0.3 V to 6.5 V –0.3 V to (VDD + 0.3 V) < 4 V –0.3 V to (VCC + 0.3 V) < 6.5 V ±10 mA –40°C to 125°C –55°C to 150°C 150°C 260°C, 5 s 250°C Supply voltage differences: VCC1, VCC2L, VCC2R Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND Digital input voltage Analog input voltage Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (IR reflow, peak) LRCK, DATA, BCK, SCK, FMT1, FMT0, MONO, CHSL, DEM, MUTE, RST, ZERO (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PCM1794ADB PARAMETER RESOLUTION DATA FORMAT Audio data interface format Audio data bit length Audio data format fS Sampling frequency System clock frequency DIGITAL INPUT/OUTPUT Logic family VIH VIL IIH IIL VOH VOL Input logic level Input logic current Output logic level VIN = VDD VIN = 0 V IOH = –2 mA IOL = 2 mA 2.4 0.4 VDC 2 0.8 10 –10 TTL compatible VDC µA Standard, I2S, left justified 16-, 24-bit selectable MSB first, 2s complement 10 200 kHz 128, 192, 256, 384, 512, 768 fS TEST CONDITIONS MIN TYP 24 MAX UNIT Bits 2 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PCM1794ADB PARAMETER DYNAMIC PERFORMANCE (2-V RMS OUTPUT) (1)(2) THD+N at VOUT = 0 dB dB fS = 44.1 kHz fS = 96 kHz fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz Channel separation fS = 44.1 kHz fS = 96 kHz 120 123 123 0.0004% 0.0008% 0.0015% 127 127 127 127 127 127 123 122 120 ±1 0.0004% 0.0008% 0.0015% 129 129 129 129 129 129 124 123 121 0.0004% 0.0008% 0.0015% 132 132 132 132 132 132 dB dB dB dB dB dB dB dB dB 0.0008% TEST CONDITIONS MIN TYP MAX UNIT fS = 192 kHz Level linearity error VOUT = –120 dB DYNAMIC PERFORMANCE (4.5-V RMS Output) (1)(3) THD+N at VOUT = 0 dB dB fS = 44.1 kHz fS = 96 kHz fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz Channel separation DYNAMIC PERFORMANCE (MONO MODE) (1)(3) THD+N at VOUT = 0 dB dB fS = 44.1 kHz fS = 96 kHz fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz fS = 44.1 kHz fS = 96 kHz fS = 192 kHz (1) Filter condition: THD+N: 20-Hz HPF, 20-kHz apogee LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Twot Cascade audio measurement system by Audio Precision in the averaging mode. (2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 24. (3) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 25. Audio Precision and System Two are trademarks of Audio Precision, Inc. Other trademarks are the property of their respective owners. 3 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PCM1794ADB PARAMETER ANALOG OUTPUT Gain error Gain mismatch, channel-to-channel Bipolar zero error Output current Center current DIGITAL FILTER PERFORMANCE De-emphasis error FILTER CHARACTERISTICS-1: SHARP ROLLOFF Pass band Stop band Pass-band ripple Stop-band attenuation Delay time FILTER CHARACTERISTICS-2: SLOW ROLLOFF Pass band Stop band Pass-band ripple Stop-band attenuation Delay time POWER SUPPLY REQUIREMENTS VDD VCC1 VCC2L VCC2R IDD Supply current (1) ICC 3 Voltage range 4.75 fS = 44.1 kHz fS = 96 kHz fS = 192 kHz fS = 44.1 kHz fS = 96 kHz fS = 192 kHz (1) Power dissipation (1) TEMPERATURE RANGE Operation temperature θJA Thermal resistance (1) Input is BPZ data. 28-pin SSOP –25 100 85 °C °C/W fS = 44.1 kHz fS = 96 kHz fS = 192 kHz 3.3 5 12 23 45 33 35 37 205 250 335 250 mW 40 mA 3.6 5.25 15 mA VDC VDC Stop band = 0.732 fS –100 18/fS ±0.04 dB –3 dB 0.732 fS ±0.001 dB dB s 0.254 fS 0.46 fS Stop band = 0.546 fS –130 55/fS ±0.00001 dB –3 dB 0.546 fS ±0.00001 dB dB s 0.454 fS 0.49 fS ±0.004 dB At BPZ Full scale (0 dB) At BPZ –6 –3 –2 ±2 ±0.5 ±0.5 7.8 –6.2 6 3 2 % of FSR % of FSR % of FSR mA p-p mA TEST CONDITIONS MIN TYP MAX UNIT 4 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 PIN ASSIGNMENTS PCM1794A (TOP VIEW) MONO CHSL DEM LRCK DATA BCK SCK DGND VDD MUTE FMT0 FMT1 ZERO RST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC2L AGND3L IOUTL– IOUTL+ AGND2 VCC1 VCOML VCOMR IREF AGND1 IOUTR– IOUTR+ AGND3R VCC2R 5 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 Terminal Functions TERMINAL NAME AGND1 AGND2 AGND3L AGND3R BCK CHSL DATA DEM DGND FMT0 FMT1 IOUTL+ IOUTL– IOUTR+ IOUTR– IREF LRCK MONO MUTE RST SCK VCC1 VCC2L VCC2R VCOML VCOMR VDD PIN 19 24 27 16 6 2 5 3 8 11 12 25 26 17 18 20 4 1 10 14 7 23 28 15 22 21 9 I/O – – – – I I I I – I I O O O O – I I I I I – – – – – – Analog ground (internal bias) Analog ground (internal bias) Analog ground (L-channel DACFF) Analog ground (R-channel DACFF) Bit clock input (1) L-, R-channel select (1) Serial audio data input (1) De-emphasis enable (1) Digital ground Audio data format select (1) Audio data format select (1) L-channel analog current output + L-channel analog current output – R-channel analog current output + R-channel analog current output – Output current reference bias pin Left and right clock (fS) input (1) Monaural mode enable (1) Mute control (1) Reset(1) System clock input(1) Analog power supply, 5 V Analog power supply (L-channel DACFF), 5 V Analog power supply (R-cahnnel DACFF), 5 V L-channel internal bias decoupling pin R-channel internal bias decoupling pin Digital power supply, 3.3 V Zero flag DESCRIPTIONS ZERO 13 O (1) Schmitt-trigger input, 5-V tolerant 6 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 FUNCTIONAL BLOCK DIAGRAM LRCK BCK DATA Audio Data Input I/F Current Segment DAC IOUTL+ IOUTL– VOUTL MUTE FMT1 FMT0 MONO CHSL Function Control I/F 8 Oversampling Digital Filter and Function Control VCOML Advanced Segment DAC Modulator Bias and Vref IREF VCOMR I/V and Filter IOUTR– Current Segment DAC IOUTR+ VOUTR DEM RST I/V and Filter ZERO Zero Detect System Clock Manager Power Supply SCK AGND3L AGND3R AGND1 AGND2 VCC2L VCC2R DGND VCC1 VDD 7 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 TYPICAL PERFORMANCE CURVES DIGITAL FILTER Digital Filter Response AMPLITUDE vs FREQUENCY 0 2 0.00002 AMPLITUDE vs FREQUENCY −50 Amplitude – dB 1 0.00001 Amplitude – dB −100 0 −150 −1 –0.00001 −200 0 1 2 Frequency [× fS] 3 4 −2 –0.00002 0.0 0.1 0.2 0.3 0.4 0.5 Frequency [× fS] Figure 1. Frequency Response, Sharp Rolloff AMPLITUDE vs FREQUENCY 0 Figure 2. Pass-Band Ripple, Sharp Rolloff AMPLITUDE vs FREQUENCY 0 −2 −4 −50 −6 Amplitude – dB Amplitude – dB 0 1 2 Frequency [× fS] 3 4 −8 −10 −12 −14 −150 −16 −18 −200 −20 0.0 −100 0.1 0.2 0.3 0.4 0.5 0.6 Frequency [× fS] Figure 3. Frequency Response, Slow Rolloff 8 Figure 4. Transition Characteristics, Slow Rolloff PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 De-Emphasis Filter DE-EMPHASIS LEVEL vs FREQUENCY 0 fS = 44.1 kHz 15 0.015 −2 De-Emphasis Level – dB De-Emphasis Error – dB 10 0.010 5 0.005 0 −5 –0.005 −10 –0.010 −15 –0.015 −10 0 2 4 6 8 10 12 14 16 18 20 f – Frequency – kHz −20 –0.020 0 2 4 6 8 10 12 14 16 18 20 f – Frequency – kHz 20 0.020 fS = 44.1 kHz DE-EMPHASIS ERROR vs FREQUENCY −4 −6 −8 Figure 5 Figure 6 9 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 ANALOG DYNAMIC PERFORMANCE Supply Voltage Characteristics TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE 0.01 THD+N – Total Harmonic Distortion + Noise – % 132 DYNAMIC RANGE vs SUPPLY VOLTAGE 130 fS = 96 kHz Dynamic Range – dB 128 fS = 192 kHz 126 fS = 48 kHz 0.001 fS = 192 kHz fS = 96 kHz 124 fS = 48 kHz 0.0001 4.50 122 4.50 4.75 5.00 5.25 5.50 4.75 5.00 5.25 5.50 VCC – Supply Voltage – V VCC – Supply Voltage – V Figure 7 SIGNAL-to-NOISE RATIO vs SUPPLY VOLTAGE 132 130 Figure 8 CHANNEL SEPARATION vs SUPPLY VOLTAGE SNR – Signal-to-Noise Ratio – dB 130 fS = 96 kHz 128 fS = 48 kHz 126 fS = 192 kHz Channel Separation – dB 128 126 fS = 96 kHz fS = 192 kHz fS = 48 kHz 124 124 122 122 4.50 4.75 5.00 5.25 5.50 120 4.50 4.75 5.00 5.25 5.50 VCC – Supply Voltage – V VCC – Supply Voltage – V Figure 9 NOTE: TA = 25°C, VDD = 3.3 V, measurement circuit is Figure 25 (VOUT = 4.5 V rms). Figure 10 10 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 Temperature Characteristics TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE 0.01 THD+N – Total Harmonic Distortion + Noise – % 132 DYNAMIC RANGE vs FREE-AIR TEMPERATURE 130 Dynamic Range – dB fS = 96 kHz fS = 48 kHz 128 fS = 192 kHz 0.001 fS = 192 kHz 126 fS = 96 kHz fS = 48 kHz 124 0.0001 −50 −25 0 25 50 75 100 122 −50 −25 0 25 50 75 100 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 11 Figure 12 SIGNAL-to-NOISE RATIO vs FREE-AIR TEMPERATURE 132 130 CHANNEL SEPARATION vs FREE-AIR TEMPERATURE SNR – Signal-to-Noise Ratio – dB 130 Channel Separation – dB fS = 96 kHz 128 fS = 192 kHz fS = 48 kHz 126 128 126 fS = 48 kHz 124 fS = 192 kHz fS = 96 kHz 122 124 122 −50 −25 0 25 50 75 100 120 −50 −25 0 25 50 75 100 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 13 NOTE: VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 25 (VOUT = 4.5 V rms). Figure 14 11 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 AMPLITUDE vs FREQUENCY 0 −20 −40 −60 Amplitude – dB −60 −80 −100 −120 −140 −160 0 2 4 6 8 10 12 14 16 18 20 0 10 20 30 −80 −100 −120 −140 −160 −180 f – Frequency – kHz 0 −20 −40 AMPLITUDE vs FREQUENCY Amplitude – dB 40 50 60 70 80 90 100 f – Frequency – kHz NOTE: fS = 48 kHz, 32768 point 8 average, TA = 25°C, VDD = 3.3 V, NOTE: fS = 48 kHz, 32768 point 8 average, TA = 25°C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 25. VCC = 5 V, measurement circuit is Figure 25. Figure 15. –60-db Output Spectrum, BW = 20 kHz Figure 16. –60-db Output Spectrum, BW = 100 kHz TOTAL HARMONIC DISTORTION + NOISE vs INPUT LEVEL 10 THD+N – Total Harmonic Distortion + Noise – % 1 0.1 0.01 0.001 0.0001 −100 −80 −60 −40 −20 0 Input Level – dBFS NOTE: fS = 48 kHz, TA = 25°C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 25. Figure 17. THD+N vs Input Level 12 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 SYSTEM CLOCK AND RESET FUNCTIONS System Clock Input The PCM1794A requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1794A has a system clock detection circuit that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators is an excellent choice for providing the PCM1794A system clock. Table 1. System Clock Rates for Common Audio Sampling Frequencies SAMPLING FREQUENCY 32 kHz 44.1 kHz 48 kHz 96 kHz 192 kHz SYSTEM CLOCK FREQUENCY (fSCK) (MHz) 128 fS 4.096 5.6488 6.144 12.288 24.576 192 fS 6.144 8.4672 9.216 18.432 36.864 256 fS 8.192 11.2896 12.288 24.576 49.152 384 fS 12.288 16.9344 18.432 36.864 73.728 512 fS 16.384 22.5792 24.576 49.152 (1) 768 fS 24.576 33.8688 36.864 73.728 (1) (1) This system clock rate is not supported for the given sampling frequency. t(SCKH) H System Clock (SCK) L t(SCKL) PARAMETERS t(SCY) System clock pulse cycle time t(SCKH) System clock pulse duration, HIGH t(SCKL) System clock pulse duration, LOW t(SCY) MIN 13 0.4t (SCY) 0.4t (SCY) MAX UNITS ns ns ns 0.8 V 2V Figure 18. System Clock Input Timing Power-On and External Reset Functions The PCM1794A includes a power-on reset function. Figure 19 shows the operation of this function. With VDD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V. The PCM1794A also includes an external reset capability using the RST input (pin 14). This allows an external controller or master reset circuit to force the PCM1794A to initialize to its default reset state. Figure 20 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The external reset is especially useful in applications where there is a delay between the PCM1794A power up and system clock activation. 13 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 VDD 2.4 V (Max) 2 V (Typ) 1.6 V (Min) Reset Internal Reset Reset Removal 1024 System Clocks System Clock Figure 19. Power-On Reset Timing RST (Pin 14) 50 % of VDD t(RST) Reset Internal Reset 1024 System Clocks System Clock PARAMETERS t(RST) Reset pulse duration, LOW MIN 20 MAX UNITS ns Reset Removal Figure 20. External Reset Timing 14 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 AUDIO DATA INTERFACE Audio Serial Interface The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM1794A on the rising edge of BCK. LRCK is the serial audio left/right word clock. The PCM1794A requires the synchronization of LRCK and the system clock, but does not need a specific phase relation between LRCK and the system clock. If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is initialized within 1/fS and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the system clock is completed. PCM Audio Data Formats and Timing The PCM1794A supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified. The data formats are shown in Figure 22. Data formats are selected using the format bits, FMT1 (pin 12), and FMT0 (pin 11) as shown in Table 2. All formats require binary twos-complement, MSB-first audio data. Figure 21 shows a detailed timing diagram for the serial audio interface. LRCK t(BCH) BCK t(BCY) DATA t(DS) PARAMETERS t(BCY) t(BCL) t(BCH) t(BL) t(LB) t(DS) t(DH) — BCK pulse cycle time BCK pulse duration, LOW BCK pulse duration, HIGH BCK rising edge to LRCK edge LRCK edge to BCK rising edge DATA setup time DATA hold time LRCK clock duty t(DH) MIN 70 30 30 10 10 10 10 MAX UNITS ns ns ns ns ns ns ns t(BL) 50% of VDD t(BCL) t(LB) 50% of VDD 50% of VDD 50% ± 2 bit clocks Figure 21. Timing of Audio Interface 15 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 (1) Standard Data Format (Right Justified); L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK Audio Data Word = 16-Bit DATA 14 15 16 1 2 MSB 15 16 LSB 1 2 15 16 Audio Data Word = 24-Bit DATA 22 23 24 1 2 MSB 23 24 LSB 1 2 23 24 (2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK Audio Data Word = 24-Bit DATA 1 2 MSB 23 24 LSB 1 2 23 24 1 2 (3) I2S Data Format; L-Channel = LOW, R-Channel = HIGH 1/fS L-Channel R-Channel LRCK BCK Audio Data Word = 24-Bit DATA 1 2 MSB 23 24 LSB 1 2 23 24 1 2 Figure 22. Audio Data Input Formats 16 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 FUNCTION DESCRIPTIONS Audio data format Audio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1794A also supports monaural mode and DF bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1794A can select the DF rolloff characteristics. Table 2. Audio Data Format Select MONO 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CHSL 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FMT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FMT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FORMAT I2S Left-justified format Standard, 16-bit Standard, 24-bit I2S Left-justified format Standard, 16-bit Digital filter bypass I2S Left-justified format Standard, 16-bit Standard, 24-bit I2S Left-justified format Standard, 16-bit Standard, 24-bit STEREO/MONO Stereo Stereo Stereo Stereo Stereo Stereo Stereo Mono Mono, L-channel Mono, L-channel Mono, L-channel Mono, L-channel Mono, R-channel Mono, R-channel Mono, R-channel Mono, R-channel DF ROLLOFF Sharp Sharp Sharp Sharp Slow Slow Slow – Sharp Sharp Sharp Sharp Sharp Sharp Sharp Sharp Soft Mute The PCM1794A supports mute operation. When MUTE (pin 10) is set to HIGH, both analog outputs are transitioned to the bipolar zero level in –0.5-dB steps with a transition speed of 1/fS per step. This system provides pop-free muting of the DAC output. De-Emphasis The PCM1794A has a de-emphasis filters for the sampling frequency of 44.1 kHz. The de-emphasis filter is controlled using DEM (pin 3). Zero Detect When the PCM1794A detects that the audio input data in the L-channel and the R-channel is continuously zero for 1024 LRCKs in the PCM mode or that the audio input data is continuously zero for 1024 WDCKs in the external filter mode, the PCM1794A sets ZERO (pin 13) to HIGH. 17 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 TYPICAL CONNECTION DIAGRAM 5V 0.1 µF 1 Controller 2 3 4 PCM Audio Data Source 5 6 7 0.1 µF 8 9 MONO CHSL DEM LRCK DATA BCK SCK VCC2L AGND3L IOUTL– IOUTL+ AGND2 VCC1 VCOML 28 27 26 25 24 23 22 21 20 19 18 17 16 15 + 3.3 V + 10 µF 10 µF 0.1 µF + + 47 µF 10 kΩ – + Cf 5V – + Rf Differential to Single Converter With Low-Pass Filter 47 µF + 10 µF 5V – + Cf Rf + 10 µF – + Cf Rf Differential to Single Converter With Low-Pass Filter Cf Rf VOUT L-Channel PCM1794A DGND VCOMR VDD IREF AGND1 IOUTR– IOUTR+ AGND3R VCC2R 10 MUTE 11 FMT0 Controller 12 FMT1 13 ZERO 14 RST VOUT R-Channel Figure 23. Typical Application Circuit 18 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 APPLICATION INFORMATION APPLICATION CIRCUIT The design of the application circuit is very important in order to actually realize the high S/N ratio of which the PCM1794A is capable. This is because noise and distortion that are generated in an application circuit are not negligible. In the circuit of Figure 24, the output level is 2 V RMS, and 127 dB S/N is achieved. The circuit of Figure 25 can realize the highest performance. In this case the output level is set to 4.5 V RMS and 129 dB S/N is achieved (stereo mode). In monaural mode, if the output of the L-channel and R-channel is used as a balanced output, 132 dB S/N is achieved (see Figure 26). I/V Section The current of the PCM1794A on each of the output pins (IOUTL+, IOUTL–, IOUTR+, IOUTR–) is 7.8 mA p-p at 0 dB (full scale). The voltage output level of the I/V converter (Vi) is given by following equation: Vi = 7.8 mA p–p × Rf (Rf : feedback resistance of I/V converter) An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the audio dynamic performance of the I/V section. Differential Section The PCM1794A voltage outputs are followed by differential amplifier stages, which sum the differential signals for each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter function. The operational amplifier recommended for the differential circuit is the Linear Technology LT1028, because its input noise is low. 19 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 C1 2200 pF R1 750 Ω VCC VCC C11 0.1 µF C17 22 pF 5 – + 4 8 6 U1 NE5534 C12 0.1 µF VEE C2 2200 pF R4 560 Ω R3 560 Ω C3 2700 pF R5 270 Ω C15 0.1 µF C19 33 pF 5 – + 4 U3 LT1028 C16 0.1 µF VEE 6 R7 100 Ω 7 IOUT– 2 3 7 2 3 R6 270 Ω C4 2700 pF R2 750 Ω VCC C13 0.1 µF C18 22 pF 5 – + 4 8 6 U2 NE5534 C14 0.1 µF VEE 7 IOUT+ 2 3 VCC = 15 V VEE = –15 V fC = 217 kHz Figure 24. Measurement Circuit, VOUT = 2 V RMS 20 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 C1 2200 pF R1 820 Ω VCC VCC C11 0.1 µF C17 22 pF 5 – + 4 8 6 U1 NE5534 C12 0.1 µF VEE C2 2200 pF R4 360 Ω R3 360 Ω C3 2700 pF R5 360 Ω C15 0.1 µF C19 33 pF 5 – + 4 U3 LT1028 C16 0.1 µF VEE 6 R7 100 Ω 7 IOUT– 2 3 7 2 3 R6 360 Ω C4 2700 pF R2 820 Ω VCC VCC = 15 V VEE = –15 V fC = 162 kHz C13 0.1 µF C18 22 pF 5 – + 4 8 6 U2 NE5534 C14 0.1 µF VEE 7 IOUT+ 2 3 Figure 25. Measurement Circuit, VOUT = 4.5 V RMS 21 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 IOUTL– (Pin 26) IOUTL+ (Pin 25) IOUT– Figure 25 Circuit IOUT+ OUT+ 3 1 2 IOUTR– (Pin 18) IOUTR+ (Pin 17) IOUT– Figure 25 Circuit IOUT+ OUT– Balanced Out Figure 26. Measurement Circuit for Monaural Mode APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE VDD External Filter Device 1 2 3 WDCK DATA BCK SCK 4 5 6 7 8 9 MONO CHSL DEM LRCK DATA BCK SCK VCC2L AGND3L IOUTL– IOUTL+ AGND2 VCC1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Analog Output Stage (See Figure 23) VCOML PCM1794A DGND VCOMR VDD IREF AGND1 IOUTR– IOUTR+ AGND3R VCC2R 10 MUTE 11 FMT0 12 FMT1 13 ZERO 14 RST Figure 27. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application 22 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 Application for Interfacing With an External Digital Filter For some applications, it may be desirable to use a programmable digital signal processor as an external digital filter to perform the interpolation function. The following pin settings enable the external digital filter application mode. D D D D MONO (pin 1) = LOW CHSL (Pin 2) = HIGH FMT0 (Pin 11) = HIGH FMT1 (pin 12) = HIGH The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of Figure 27. The word clock (WDCK) must be operated at 8× or 4× the desired sampling frequency, fS. System Clock (SCK) and Interface Timing The PCM1794A in an application using an external digital filter requires the synchronization of WDCK and the system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, and DATA is shown in Figure 29. Audio Format The PCM1794A in the external digital filter interface mode supports right-justified audio formats including 24-bit audio data, as shown in Figure 28. 1/4 fS or 1/8 fS WDCK BCK Audio Data Word = 24-Bit DATA 23 24 1 2 3 MSB 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LSB Figure 28. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application 23 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 WDCK t(BCH) BCK t(BCY) DATA t(DS) PARAMETER t(BCY) BCK pulse cycle time t(BCL) BCK pulse duration, LOW t(BCH) BCK pulse duration, HIGH t(BL) BCK rising edge to WDCK falling edge t(LB) t(DS) t(DH) WDCK falling edge to BCK rising edge DATA setup time DATA hold time t(DH) MIN 20 7 7 5 5 5 5 MAX UNITS ns ns ns ns ns ns ns t(BL) t(BCL) t(LB) 50% of VDD 50% of VDD 50% of VDD Figure 29. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application THEORY OF OPERATION Upper 6 Bits ICOB Decoder 0–62 Level 0–66 Advanced DWA 0–4 Level Current Segment DAC Analog Output Digital Input 24 Bits 8 fS MSB and Lower 18 Bits 3rd-Order 5-Level Sigma-Delta Figure 30. Advanced Segment DAC The PCM1794A uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1794A provides balanced current outputs. Digital input data via the digital filter is separated into 6 upper bits and 18 lower bits. The 6 upper bits are converted to inverted complementary offset binary (ICOB) code. The lower 18 bits, associated with the MSB, are processed by a five-level third-order delta-sigma modulator operated at 64 fS by default. The 1 level of the modulator is equivalent to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order delta-sigma modulator are summed together to create an up-to-66-level digital code, and then processed by data-weighted averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from the DWA is converted to an analog output in the differential-current segment section. This architecture has overcome the various drawbacks of conventional multibit processing and also achieves excellent dynamic performance. 24 PCM1794A www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 Analog output The following table and Figure 31 show the relationship between the digital input code and analog output. 800000 (–FS) IOUTN [mA] IOUTP [mA] VOUTN [V] VOUTP [V] –2.3 –10.1 –1.725 –7.575 000000 (BPZ) –6.2 –6.2 –4.65 –4.65 7FFFFF (+FS) –10.1 –2.3 –7.575 –1.725 VOUT [V] –2.821 0 2.821 NOTE: VOUTN is the output of U1, VOUTP is the output of U2, and VOUT is the output of U3 in the measurement circuit of Figure 24. OUTPUT CURRENT vs INPUT CODE 0 −2 IO – Output Current – mA IOUTN −4 −6 −8 IOUTP −10 −12 800000(–FS) 000000(BPZ) Input Code – Hex 7FFFFF(+FS) Figure 31. The Relationship Between Digital Input and Analog Output 25 PACKAGE OPTION ADDENDUM www.ti.com 7-May-2007 PACKAGING INFORMATION Orderable Device PCM1794ADB PCM1794ADBG4 PCM1794ADBR PCM1794ADBRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type SSOP SSOP SSOP SSOP Package Drawing DB DB DB DB Pins Package Eco Plan (2) Qty 28 28 28 28 47 47 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2007 Device Package Pins Site Reel Diameter (mm) 0 Reel Width (mm) 0 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 12 W Pin1 (mm) Quadrant 16 NONE PCM1794ADBR DB 28 NST 8.5 10.8 2.4 TAPE AND REEL BOX INFORMATION Device PCM1794ADBR Package DB Pins 28 Site NST Length (mm) 0.0 Width (mm) 0.0 Height (mm) 0.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M PLASTIC SMALL-OUTLINE 0,25 0,09 5,60 5,00 8,20 7,40 Gage Plane 1 A 14 0°– 8° 0,25 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** DIM A MAX 14 16 20 24 28 30 38 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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