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PCM1802
SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016
PCM1802 Single-Ended Analog-Input 24-Bit, 96-kHz Stereo A/D Converter
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
24-Bit Delta-Sigma Stereo A/D Converter
Single-Ended Voltage Input: 3 VP–P
Antialiasing Filter Included
Oversampling Decimation Filter
– Oversampling Frequency: ×64, ×128
– Pass-Band Ripple: ±0.05 dB
– Stop-Band Attenuation: –65 dB
– On-Chip High-Pass Filter: 0.84 Hz (44.1 kHz)
High Performance
– THD+N: 96 dB (Typical)
– SNR: 105 dB (Typical)
– Dynamic Range: 105 dB (Typical)
PCM Audio Interface
– Master and Slave Mode Selectable
– Data Formats: 24-Bit Left-Justified; 24-Bit I2S;
20-bit or 24-Bit Right-Justified
Sampling Rate: 16 kHz to 96 kHz
System Clock: 256 fS, 384 fS, 512 fS, 768 fS
Dual Power Supplies: 5 V (Analog), 3.3 V (Digital)
Package: 20-Pin SSOP
AV Amplifier Receivers
MD Players
CD Recorders
Multitrack Receivers
Electric Musical Instruments
3 Description
The PCM1802 is a high-performance, low-cost,
single-chip stereo analog-to-digital converter with
single-ended analog voltage input. The PCM1802
uses a delta-sigma modulator with 64-times or
128‑times oversampling, and includes a digital
decimation filter and high-pass filter (HPF), which
removes the DC component of the input signal. For
various applications, the PCM1802 supports master
and slave modes and four data formats in serial
interface. The PCM1802 is suitable for a wide variety
of cost-sensitive consumer applications where good
performance, 5-V analog supply, and 3.3-V digital
supply operation is required. The PCM1802 is
fabricated using a highly advanced CMOS process
and is available in the DB 20-pin SSOP package.
Device Information(1)
PART NUMBER
PCM1802
PACKAGE
BODY SIZE (NOM)
SSOP (20)
7.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
VINL
Single-End
/Differential
Converter
5th Order
Delta-Sigma
Modulator
×1/64 (×1/128)
Decimation
Filter
with
High-Pass Filter
VREF1
Reference
VREF2
VINR
Single-End
/Differential
Converter
BCK
LRCK
Serial
Interface
FSYNC
DOUT
Mode/
Format
Control
5th Order
Delta-Sigma
Modulator
FMT0
FMT1
MODE0
MODE1
BYPAS
OSR
Clock and Timing Control
Power Supply
VCC
AGND DGND
PDWN
SCKI
VDD
B0004-07
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM1802
SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagrams ..................................... 12
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2005) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Lead temperature (soldering), 260°C for 5 s, from Absolute Maximum Ratings table ............................................. 4
•
Added Thermal Information table ........................................................................................................................................... 5
•
Changed Thermal resistance, RθJA, value in Thermal Information table From: 115°C/W To: 80.8°C/W ............................... 5
2
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SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016
5 Pin Configuration and Functions
DB Package
20-Pin SSOP
Top View
VINL
1
20
MODE1
VINR
2
19
MODE0
VREF1
3
18
FMT1
VREF2
4
17
FMT0
VCC
5
16
OSR
AGND
6
15
SCKI
PDWN
7
14
VDD
BYPAS
8
13
DGND
FSYNC
9
12
DOUT
10
11
BCK
LRCK
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AGND
6
—
Analog GND
BCK
11
I/O
Bit clock input and output (1)
BYPAS
8
I
DGND
13
—
Digital GND
DOUT
12
O
Audio data output
FMT0
17
I
Audio data format select 0 (see Data Format) (2)
FMT1
18
I
Audio data format select 1 (see Data Format) (2)
FSYNC
9
I/O
Frame synchronous clock input and output (1)
LRCK
10
I/O
Sampling clock input and output (1)
MODE0
19
I
Mode select 0 (see Interface Mode) (2)
MODE1
20
I
Mode select 1 (see Interface Mode) (2)
OSR
16
I
Oversampling ratio select. Low: ×64 fS; High: ×128 fS (2)
PDWN
7
I
Power-down control, active-low (2)
SCKI
15
I
System clock input; 256 fS, 384 fS, 512 fS, or 768 fS (3)
VCC
5
—
Analog power supply, 5 V
VDD
14
—
Digital power supply, 3.3 V
VINL
1
I
Analog input, L-channel
VINR
2
I
Analog input, R-channel
VREF1
3
—
Reference-1 decoupling capacitor
VREF2
4
—
Reference-2 voltage input, normally connected to VCC
(1)
(2)
(3)
HPF bypass control. Low: normal mode (DC cut); High: bypass mode (through) (2)
Schmitt-Trigger input
Schmitt-Trigger input with internal pulldown (50 kΩ typically), 5-V tolerant
Schmitt-Trigger input, 5-V tolerant
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PCM1802
SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
MAX
VCC
6.5
VDD
4
UNIT
V
Ground voltage differences
AGND and DGND
±0.1
V
Supply voltage difference (VCC – VDD)
VCC and VDD
3V
V
FSYNC, LRCK, BCK, and DOUT
–0.3
VDD + 0.3
Digital input voltage
PDWN, BYPAS, SCKI, OSR, FMT0, FMT1,
MODE0, and MODE1
–0.3
6.5
Analog input voltage
VINL, VINR, VREF1, and VREF2
–0.3
VCC + 0.3
V
±10
mA
125
°C
150
°C
260
°C
150
°C
Input current (any pins except supplies)
Ambient temperature under bias
–40
Junction temperature
Package temperature (IR reflow, peak)
Storage temperature, Tstg
(1)
–55
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
Analog supply voltage, VCC
5
Digital supply voltage, VDD
VP–P
TTL
Sampling clock
System clock
8.192
49.152
MHz
32
96
kHz
20
pF
85
°C
Digital output load capacitance
Operating free-air temperature, TA
4
V
3
Digital input logic family
UNIT
V
3.3
Analog input voltage, full-scale (–0 dB)
Digital input clock frequency
MAX
–40
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6.4 Thermal Information
PCM1802
THERMAL METRIC (1)
DB (SSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
7.2
°C/W
ψJB
Junction-to-board characterization parameter
37
°C/W
(1)
80.8
°C/W
40
°C/W
37.6
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
24
Bits
DATA FORMAT
Left-justified, I2S, or
right‑justified
Audio data interface format
Audio data bit length
20 or 24
Audio data format
fS
Bits
MSB first or 2s complement
Sampling frequency
System clock frequency
16
44.1
96
256 fS
4.096
11.2896
24.576
384 fS
6.144
16.9344
36.864
512 fS
8.192
22.5792
49.152
12.288
33.8688
768 fS (1)
kHz
MHz
INPUT LOGIC
VIH
VIL
VIH
VIL
IIH
IIL
IIH
IIL
Input logic level (2)
Input logic level
(3)
Input logic current (4)
Input logic current
(5)
2
VDD
0
0.8
2
5.5
0
0.8
VIN = VDD
VDC
±10
VIN = 0 V
±10
VIN = VDD
65
VIN = 0 V
100
µA
±10
OUTPUT LOGIC
VOH
VOL
Output logic level (6)
IOUT = –1 mA
2.8
IOUT = 1 mA
0.5
VDC
DC ACCURACY
Gain mismatch,
channel-to-channel
Gain error
Bipolar zero error
(1)
(2)
(3)
(4)
(5)
(6)
(7)
HPF bypassed
(7)
±1%
±4%
FSR
±2%
±6%
FSR
±2%
FSR
Maximum system clock frequency is not applicable at 768 fS, fS = 96 kHz (see System Clock).
Applies to FSYNC, LRCK, BCK (Schmitt-trigger input in slave mode) pins.
Applies to PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, 5-V tolerant) pins.
Applies to FSYNC, LRCK, BCK (Schmitt-trigger input in slave mode), SCKI (Schmitt-trigger input) pins.
Applies to PDWN, BYPAS, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 50-kΩ typical pulldown resistor) pins.
Applies to FSYNC, LRCK, BCK (in master mode), DOUT pins.
High-pass filter
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Electrical Characteristics (continued)
TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fS = 44.1 kHz, VIN = –0.5 dB
0.0015%
0.003%
fS = 96 kHz, VIN = –0.5 dB, system clock = 256 fS,
oversampling ratio = ×64 (9)
0.0025%
UNIT
DYNAMIC PERFORMANCE (8)
THD+N
Total harmonic distortion + noise
fS = 44.1 kHz, VIN = –60 dB
0.7%
fS = 96 kHz, VIN = –60 dB, system clock = 256 fS,
oversampling ratio = ×64 (9)
1.2%
fS = 44.1 kHz, A-weighted
Dynamic range
100
fS = 96 kHz, A-weighted, system clock = 256 fS,
oversampling ratio = ×64 (9)
fS = 44.1 kHz, A-weighted
Signal to noise ratio
100
fS = 44.1 kHz
dB
103
fS = 96 kHz, A-weighted, system clock = 256 fS,
oversampling ratio = ×64 (9)
Channel separation
105
105
dB
103
96
fS = 96 kHz, system clock = 256 fS, oversampling
ratio = ×64 (9)
103
dB
98
ANALOG INPUT
VREF1
Input voltage
0.6 × VCC
Center voltage
0.5 × VCC
V
20
kΩ
300
kHz
Input impedance
Antialiasing filter frequency
response
–3 dB
VP–P
DIGITAL FILTER PERFORMANCE
Pass band
0.454 fS
Stop band
0.583 fS
Hz
Pass-band ripple
±0.05
Stop-band attenuation
–65
Delay time
HPF frequency response
–3 dB
Hz
dB
dB
17.4 / fS
s
0.019 fS
mHz
POWER SUPPLY REQUIREMENTS
VCC
VDD
ICC
IDD
PD
4.5
5
5.5
2.7
3.3
3.6
VCC = 5 V, VDD = 3.3 V
24
30
fS = 44.1 kHz VCC = 5 V, VDD = 3.3 V
8.3
10
fS = 96 kHz, VCC = 5 V, VDD = 3.3 V (8)
17
fS = 44.1 kHz, VCC = 5 V, VDD = 3.3 V
147
fS = 96 kHz, VCC = 5 V, VDD = 3.3 V (8)
176
Voltage
Supply current (10)
Power dissipation
Operation
Power down VCC = 5 V, VDD = 3.3 V
VDC
mA
183
mW
0.5
(8)
Analog performance specifications are tested with System Two™ audio measurement system by Audio Precision™, using 400-Hz HPF,
20-kHz LPF for 44.1-kHz operation or 40-kHz LPF for 96-kHz operation in RMS mode.
(9) fS = 96 kHz, system clock = 256 fS, oversampling ratio = ×64.
(10) Minimum load on DOUT, BCK, LRCK, and FSYNC.
6
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6.6 Typical Characteristics
TA = 25°C, VCC = 5 V, VDD = 3.3 V, Master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, and 24-bit
data (unless otherwise noted).
110
109
Dynamic Range and SNR − dB
THD+N − Total Harmonic Distortion + Noise − %
0.004
0.003
0.002
108
107
Dynamic Range
106
105
SNR
104
103
102
101
0.001
−50
−25
0
25
50
75
TA − Free-Air Temperature − °C
100
−50
100
25
50
75
100
G010
110
0.004
109
Dynamic Range and SNR − dB
THD+N − Total Harmonic Distortion + Noise − %
0
Figure 2. Dynamic Range and SNR
vs Free-Air Temperature
Figure 1. Total Harmonic Distortion + Noise
vs Free-Air Temperature
0.003
0.002
108
107
Dynamic Range
106
105
SNR
104
103
102
101
0.001
4.25
4.50
4.75
5.00
5.25
5.50
100
4.25
5.75
VCC − Supply Voltage − V
4.50
4.75
5.00
5.25
5.50
VCC − Supply Voltage − V
G011
Figure 3. Total Harmonic Distortion + Noise
vs Supply Voltage
5.75
G012
Figure 4. Dynamic Range and SNR vs Suppy Voltage
110
0.004
fS = 48 kHz, System Clock = 256 fS,
Oversampling Ratio = ×128.
fS = 96 kHz, System Clock = 256 fS,
Oversampling Ratio = ×64.
fS = 48 kHz, System Clock = 256 fS,
Oversampling Ratio = ×128.
fS = 96 kHz, System Clock = 256 fS,
Oversampling Ratio = ×64.
109
Dynamic Range and SNR − dB
THD+N − Total Harmonic Distortion + Noise − %
−25
TA − Free-Air Temperature − °C
G009
0.003
0.002
108
107
Dynamic Range
106
105
SNR
104
103
102
101
100
0.001
0
10
44.1
20
48
30
96
fSAMPLE Condition − kHz
0
40
20
48
30
96
fSAMPLE Condition − kHz
G013
Figure 5. Total Harmonic Distortion + Noise
vs fSAMPLE Condition
10
44.1
40
G014
Figure 6. Dynamic Range and SNR vs fSAMPLE Condition
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6.6.1 Typical Characteristics: Internal Filter
6.6.1.1 Digital Filter: Decimation Filter Frequency Response
TA = 25°C, VCC = 5 V, VDD = 3.3 V, Master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio =
×128, and 24-bit data (unless otherwise noted).
50
50
Oversampling Ratio = ´128
Oversampling Ratio = ×64
0
Amplitude − dB
Amplitude − dB
0
−50
−100
−150
−50
−100
−150
−200
−200
0
8
16
24
32
40
48
Frequency [× fS]
56
64
0
8
Figure 7. Amplitude vs Frequency Overall Characteristics
16
24
32
Frequency [× fS]
G001
G002
Figure 8. Amplitude vs Frequency Overall Characteristics
0
0.2
−10
0.0
−20
Amplitude − dB
Amplitude − dB
−30
−40
−50
−60
−70
−80
−90
−0.4
−0.6
−0.8
Oversampling
Ratio = ×128 and ×64
−100
0.00
0.25
Oversampling
Ratio = ×128 and ×64
0.50
Frequency [× fS]
0.75
1.00
−1.0
0.0
0.1
0.2
0.3
0.4
Frequency [× fS]
G003
Figure 9. Amplitude vs Frequency Stop-Band Attenuation
Characteristics
8
−0.2
0.5
0.6
G004
Figure 10. Amplitude vs Frequency Pass-Band Ripple
Characteristics
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Typical Characteristics: Internal Filter (continued)
6.6.1.2 HPF (High-Pass Filter) Frequency Response
TA = 25°C, VCC = 5 V, VDD = 3.3 V, Master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio =
×128, and 24-bit data (unless otherwise noted).
0
0.2
−10
0.0
−20
Amplitude − dB
Amplitude − dB
−30
−40
−50
−60
−70
−80
−0.2
−0.4
−0.6
−0.8
−90
−100
0.0
−1.0
0.1
0.2
0.3
Frequency [× fS/1000]
0.4
0
1
2
3
4
Frequency [× fS/1000]
G005
Figure 11. Amplitude vs Frequency HPF
Stop-Band Characteristics
G006
Figure 12. Amplitude vs Frequency HPF
Pass-Band Characteristics
6.6.1.3 Analog Filter: Antialiasing Filter Frequence Response
0
0.0
−5
−0.1
−10
−0.2
−15
−0.3
Amplitude − dB
Amplitude − dB
TA = 25°C, VCC = 5 V, VDD = 3.3 V, Master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio =
×128, and 24-bit data (unless otherwise noted).
−20
−25
−30
−0.4
−0.5
−0.6
−35
−0.7
−40
−0.8
−45
−0.9
−50
100
−1.0
1k
10k
100k
1M
1
10M
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
G008
G007
Figure 13. Amplitude vs Frequency Antialias Filter StopBand Characteristics
Figure 14. Amplitude vs Frequency Antialias Filter PassBand Characteristics
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6.6.2 Typical Characteristics: Output Spectrum
TA = 25°C, VCC = 5 V, VDD = 3.3 V, Master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio =
×128, and 24-bit data (unless otherwise noted).
0
0
Input Level = −60 dB
Data Points = 8192
−20
−20
−40
−40
Amplitude − dB
Amplitude − dB
Input Level = −0.5 dB
Data Points = 8192
−60
−80
−60
−80
−100
−100
−120
−120
−140
−140
0
5
10
15
20
0
5
10
15
20
f − Frequency − kHz
f − Frequency − kHz
G015
G016
Figure 15. Amplitude vs Frequency
Figure 16. Amplitude vs Frequency
THD+N − Total Harmonic Distortion + Noise − %
100
10
1
0.1
0.01
0.001
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
Signal Level − dB
G017
Figure 17. Total Harmonic Distortion + Noise vs Signal Level
10
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6.6.3 Typical Characteristics: Supply Current
TA = 25°C, VCC = 5 V, VDD = 3.3 V, Master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio =
×128, and 24-bit data (unless otherwise noted).
30
ICC
ICC and IDD − Supply Current − mA
25
20
15
IDD
10
fS = 48 kHz, System Clock = 256 fS,
Oversampling Ratio = ×128.
fS = 96 kHz, System Clock = 256 fS,
Oversampling Ratio = ×64.
5
0
0
10
44.1
20
48
30
96
fSAMPLE Condition − kHz
40
G018
Figure 18. Supply Current vs fSAMPLE Condition
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7 Detailed Description
7.1 Overview
The PCM1802 device consists of a reference circuit, two channels of single-ended-to-differential converter, a
fifth-order delta-sigma modulator with full differential architecture, a decimation filter with high-pass filter, and a
serial interface circuit. Figure 19 illustrates the total architecture of the PCM1802, Figure 20 illustrates the
architecture of single-ended-to-differential converter and antialiasing filter, and Figure 21 is the block diagram of
the fifth-order delta-sigma modulator and transfer function. An on-chip high-precision reference with one external
capacitor provides all reference voltages that are required by the PCM1802 device and defines the full-scale
voltage range for both channels. On-chip single-ended-to-differential signal converters save the design, space,
and extra parts cost for external signal converters. Full-differential architecture provides a wide dynamic range
and excellent power-supply rejection performance. The input signal is sampled at a ×64 or ×128 oversampling
rate, thus eliminating an external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of
five integrators using the switched capacitor technique and a comparator, shapes the quantization noise
generated by the comparator and 1-bit DAC outside of the audio signal band. The high-order delta-sigma
modulation randomizes the modulator outputs and reduces the idle tone level. The 64-fS or 128-fS, 1-bit stream
from the delta-sigma modulator is converted to a 1-fS, 24-bit or 20-bit digital signal by removing high-frequency
noise components with a decimation filter. The DC component of the signal is removed by the HPF, and the HPF
output is converted to a time-multiplexed serial signal through the serial interface, which provides flexible serial
formats.
7.2 Functional Block Diagrams
VINL
5th Order
Delta-Sigma
Modulator
Single-End
/Differential
Converter
×1/64 (×1/128)
Decimation
Filter
with
High-Pass Filter
VREF1
Reference
VREF2
VINR
BCK
LRCK
Serial
Interface
DOUT
Mode/
Format
Control
5th Order
Delta-Sigma
Modulator
Single-End
/Differential
Converter
FSYNC
FMT0
FMT1
MODE0
MODE1
BYPAS
OSR
Clock and Timing Control
Power Supply
VCC
AGND DGND
PDWN
SCKI
VDD
B0004-07
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Figure 19. Block Diagram
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Functional Block Diagrams (continued)
1 mF
20 kW
+
VINL
−
1
−
+
(+)
+
(−)
VREF1
Delta-Sigma
Modulator
3
+
0.1 mF
Reference
10 mF
VREF2
4
VCC
5
S0011-05
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Analog Front End (Left Channel)
Analog
In
X(z) +
−
1st
SW-CAP
Integrator
+
−
2nd
SW-CAP
Integrator
+
3rd
SW-CAP
Integrator
+
+
+
−
+
5th
SW-CAP
Integrator
4th
SW-CAP
Integrator
+
+
H(z)
+
Qn(z)
Digital
Out
Y(z)
+
Comparator
1-Bit
DAC
Y(z) = STF(z) ∗ X(z) + NTF(z) ∗ Qn(z)
Signal Transfer Function
STF(z) = H(z) / [1 + H(z)]
Noise Transfer Function
NTF(z) = 1 / [1 + H(z)]
B0005-02
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Block Diagram of Fifth-Order Delta-Sigma Modulator
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7.3 Feature Description
7.3.1 Hardware Control
The FMT0, FMT1, OSR, BYPASS, MD0, and MD1 pins allow the device to be controlled by tying these pins to
GPIO and GND or VDD from a host IC. These controls allow full configuration of the PCM1802.
7.3.2 Power-On Reset Sequence
The PCM1802 has an internal power-on reset circuit, and initialization (reset) is performed automatically when
the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts
after VDD > 2.2 V (typical), the PCM1802 stays in the reset state and the digital output is forced to zero. The
digital output is valid after the reset state is released and the time of 4480 / fS is passed. Figure 22 illustrates the
internal power-on reset timing and the digital output for power-on reset.
VDD
2.6 V
2.2 V
1.8 V
Reset
Reset Removal
Internal Reset
1024 System Clocks
4480 / fS
System Clock
DOUT
Zero Data
Normal Data
T0014-05
Figure 22. Internal Power-On Reset Timing
7.3.3 System Clock
The PCM1802 supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling
frequency. The system clock must be supplied on SCKI.
The PCM1802 has a system clock detection circuit which automatically senses if the system clock is operating at
256 fS, 384 fS, 512 fS, or 768 fS in slave mode. In master mode, the system clock frequency must be selected by
MODE0 and MODE1, and 768 fS is not available. For system clock inputs of 384 fS, 512 fS, and 768 fS, the
system clock is divided to 256 fS automatically, and the 256 fS clock operates the delta-sigma modulator and the
digital filter.
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Feature Description (continued)
Table 1 lists the relationship of typical sampling frequencies and system clock frequencies, and Table 2 shows
system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING RATE
FREQUENCY (kHz)
256 fS
384 fS
512 fS
768 fS
32
8.192
12.288
16.384
24.576
44.1
11.2896
16.9344
22.5792
33.8688
48
12.288
18.432
24.576
36.864
64
16.384
24.576
32.768
49.152
88.2
22.5792
33.8688
45.1584
—
96
24.576
36.864
49.152
—
tw(SCKH)
tw(SCKL)
SCKI
2V
SCKI
0.8 V
T0005B07
Table 2. System Clock Timing
PARAMETER
MIN
MAX
UNIT
tw(SCKH)
System clock-pulse duration, high
7
ns
tw(SCKL)
System clock-pulse duration, low
7
ns
7.4 Device Functional Modes
7.4.1 Power Down, HPF Bypass, Oversampling Control
PDWN controls the entire ADC operation. During power-down mode, both the supply current for the analog
portion and the clock signal for the digital portion are shut down, and power dissipation is minimized. DOUT is
also disabled and no system clock is accepted during power-down mode.
Table 3. Power-Down Control
PDWN
MODE
LOW
Power-down mode
HIGH
Normal operation mode
The built-in function for DC component rejection can be bypassed using the BYPAS control. In bypass mode, the
DC components of the analog input signal, such as the internal DC offset, are converted and included in the
digital output data.
Table 4. HPF Bypass Control
BYPAS
HPF (HIGH-PASS FILTER) MODE
LOW
Normal (no DC component on DOUT) mode
HIGH
Bypass (DC component on DOUT) mode
OSR controls the oversampling ratio of the delta-sigma modulator, ×64 or ×128. The ×128 mode is available for
fS < 50 kHz, and must be used carefully as the duty cycle of the 384 fS system clock affects performance.
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Table 5. Oversampling Control
OSR
OVERSAMPLING RATIO
LOW
×64
HIGH
×128 (fS < 50 kHz)
7.4.2 Serial Audio Data Interface
The PCM1802 interfaces with the audio system through BCK, LRCK, FSYNC, and DOUT.
7.4.2.1 Data Format
The PCM1802 supports four audio data formats in both master and slave modes, and they are selected by FMT1
and FMT0 as shown in Table 6. Figure 23 and Figure 25 illustrate the data formats in slave mode and master
mode, respectively.
Table 6. Data Format
16
FORMAT
FMT1
FMT0
FORMAT
0
0
0
Left-justified, 24-bit
1
0
1
I2S, 24-bit
2
1
0
Right-justified, 24-bit
3
1
1
Right-justified, 20-bit
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7.4.2.2 Interface Timing
Figure 24 and Figure 26 illustrate the interface timing in slave mode and master mode, respectively.
FORMAT 0: FMT[1:0] = 00
24-Bit, MSB-First, Left-Justified
FSYNC
Left-Channel
LRCK
Right-Channel
BCK
DOUT
1
2
3
22 23 24
MSB
1
LSB
2
3
22 23 24
MSB
1
LSB
FORMAT 1: FMT[1:0] = 01
24-Bit, MSB-First, I2S
FSYNC
LRCK
Left-Channel
Right-Channel
BCK
DOUT
1
2
3
22 23 24
1
LSB
MSB
2
3
22 23 24
LSB
MSB
FORMAT 2: FMT[1:0] = 10
24-Bit, MSB-First, Right-Justified
FSYNC
Left-Channel
LRCK
Right-Channel
BCK
DOUT
24
1
2
3
22 23 24
MSB
LSB
1
2
3
22 23 24
MSB
LSB
FORMAT 3: FMT[1:0] = 11
20-Bit, MSB-First, Right-Justified
FSYNC
LRCK
Left-Channel
Right-Channel
BCK
DOUT
20
1
2
3
MSB
18 19 20
LSB
1
2
MSB
3
18 19 20
LSB
T0016-12
Figure 23. Audio Data Format (Slave Mode: FSYNC, LRCK, and BCK Work as Inputs)
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1.4 V
FSYNC
t(FSSU)
t(FSHD)
t(LRCP)
1.4 V
LRCK
t(BCKL)
t(LRSU)
t(BCKH)
t(LRHD)
1.4 V
BCK
t(CKDO)
t(BCKP)
t(LRDO)
0.5 VDD
DOUT
T0017-01
Timing measurement reference level is (VIH + VIL) / 2. Rise and fall times are measured from 10% to 90% of IN to
OUT signal swing. Load capacitance of DOUT is 20 pF.
Figure 24. Audio Data Interface Timing (Slave Mode: FSYNC, LRCK, and BCK Work as Inputs)
Table 7. Audio Data Interface Timing: Slave Mode
PARAMETER
t(BCKP)
BCK period
t(BCKH)
t(BCKL)
MIN
MAX
UNIT
150
ns
BCK pulse duration, high
60
ns
BCK pulse duration, low
60
ns
t(LRSU)
LRCK setup time to BCK rising edge
40
ns
t(LRHD)
LRCK hold time to BCK rising edge
20
ns
t(LRCP)
LRCK period
10
µs
t(FSSU)
FSYNC setup time to BCK rising edge
20
ns
t(FSHD)
FSYNC hold time to BCK rising edge
20
ns
t(CKDO)
Delay time, BCK falling edge to DOUT valid
–10
20
ns
t(LRDO)
Delay time, LRCK edge to DOUT valid
–10
20
ns
tr
Rise time of all signals
10
ns
tf
Fall time of all signals
10
ns
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FORMAT 0: FMT[1:0] = 00
24-Bit, MSB-First, Left-Justified
FSYNC
Left-Channel
LRCK
Right-Channel
BCK
DOUT
1
2
3
22 23 24
MSB
1
LSB
2
3
22 23 24
MSB
1
LSB
FORMAT 1: FMT[1:0] = 01
24-Bit, MSB-First, I2S
FSYNC
LRCK
Left-Channel
Right-Channel
BCK
DOUT
1
2
3
22 23 24
1
LSB
MSB
2
3
22 23 24
LSB
MSB
FORMAT 2: FMT[1:0] = 10
24-Bit, MSB-First, Right-Justified
FSYNC
Left-Channel
LRCK
Right-Channel
BCK
DOUT
24
1
2
3
22 23 24
MSB
LSB
1
2
3
22 23 24
MSB
LSB
FORMAT 3: FMT[1:0] = 11
20-Bit, MSB-First, Right-Justified
FSYNC
Left-Channel
LRCK
Right-Channel
BCK
DOUT
20
1
2
3
MSB
18 19 20
LSB
1
2
MSB
3
18 19 20
LSB
T0016-13
Figure 25. Audio Data Format (Master Mode: FSYNC, LRCK, and BCK Work as Outputs)
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t(FSYP)
0.5 VDD
FSYNC
t(CKFS)
t(LRCP)
0.5 VDD
LRCK
t(BCKL)
t(BCKH)
t(CKLR)
0.5 VDD
BCK
t(CKDO)
t(BCKP)
t(LRDO)
0.5 VDD
DOUT
T0018-01
Timing measurement reference level is (VIH + VIL) / 2. Rise and fall times are measured from 10% to 90% of IN to
OUT signal swing. Load capacitance of all signals is 20 pF.
Figure 26. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, and BCK Work as Outputs)
Table 8. Audio Data Interface Timing: Master Mode
PARAMETER
MIN
TYP
MAX
UNIT
150 1 / (64 fS)
1200
ns
75
600
ns
75
600
ns
t(BCKP)
BCK period
t(BCKH)
BCK pulse duration, high
t(BCKL)
BCK pulse duration, low
t(CKLR)
Delay time, BCK falling edge to LRCK valid
t(LRCP)
LRCK period
t(CKFS)
Delay time, BCK falling edge to FSYNC valid
t(FSYP)
FSYNC period
t(CKDO)
Delay time, BCK falling edge to DOUT valid
–10
t(LRDO)
Delay time, LRCK edge to DOUT valid
–10
tr
tf
–10
20
ns
80
µs
20
ns
40
µs
20
ns
20
ns
Rise time of all signals
10
ns
Fall time of all signals
10
ns
10
1 / fS
–10
5
1 / (2 fS)
7.4.2.3 Synchronization With Digital Audio System
In slave mode, the PCM1802 operates under LRCK, synchronized with system clock SCKI. The PCM1802 does
not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK
and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 fS BCK (±5 BCKs for 48 fS BCK)
during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1 / fS and digital
output is forced into BPZ code until resynchronization between LRCK and SCKI is completed.
In the case of changes less than ±5 BCKs for 64 BCK per frame (±4 BCKs for 48 BCK per frame),
resynchronization does not occur.
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Figure 27 illustrates the digital output response for loss of synchronization and resynchronization. During
undefined data, some noise might be generated in the audio signal. The transition of normal to undefined data
and undefined or zero data to normal creates a data discontinuity in the digital output, which generates some
noise in the audio signal.
TI recommends setting PDWN low to achieve stable analog performance when the sampling rate, interface
mode, data format, or oversampling control is changed.
Synchronization Lost
State of Synchronization
SYNCHRONOUS
Resynchronization
ASYNCHRONOUS
SYNCHRONOUS
1/fS
DOUT
32/fS
UNDEFINED
DATA
NORMAL DATA
ZERO DATA
NORMAL DATA
T0020-05
Figure 27. ADC Digital Output for Loss of Synchronization and Resynchronization
7.4.3 Master Mode
In master mode, BCK, LRCK, and FSYNC work as output pins, and these pins are controlled by timing which is
generated in the clock circuit of the PCM1802. FSYNC is used to designate the valid data from the PCM1802.
The rising edge of FSYNC indicates the starting point of the converted audio data and the falling edge of this
signal indicates the ending point of the data. The frequency of this signal is fixed at 2 × LRCK. The duty cycle
ratio depends on data bit length. The frequency of BCK is fixed at 64 × LRCK. The 768-fS system clock is not
available in master mode.
7.4.4 Slave Mode
In slave mode, BCK, LRCK, and FSYNC work as input pins. FSYNC enables the BCK signal, and the device can
shift out the converted data while FSYNC is HIGH. The PCM1802 accepts the 64-fS BCK or the 48-fS BCK
format. The delay of FSYNC from the LRCK transition must be within 16 BCKs for the 64-fS BCK format and
within 12 BCKs for the 48-fS BCK format.
7.4.5 Interface Mode
The PCM1802 supports master mode and slave mode as interface modes, and they are selected by MODE1 and
MODE0 as shown in Table 9.
In master mode, the PCM1802 provides the timing for serial audio data communications between the PCM1802
and the digital audio processor or external circuit. In slave mode, the PCM1802 receives the timing for data
transfer from an external controller.
Table 9. Interface Mode
MODE1
MODE0
0
0
Slave mode (256 fS, 384 fS, 512 fS, 768 fS)
INTERFACE MODE
0
1
Master mode (512 fS)
1
0
Master mode (384 fS)
1
1
Master mode (256 fS)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The PCM1802 device is suitable for wide variety of cost-sensitive consumer applications requiring good
performance and operation with a 5-V analog supply and 3.3-V digital supply.
8.2 Typical Application
Figure 28 illustrates a typical circuit connection diagram in which the cutoff frequency of the input HPF is about
8 Hz.
L-Ch IN
R-Ch IN
C1(1)
+
C2(1)
+
VINL
MODE1
20
2
VINR
MODE0
19
3
VREF1
FMT1
18
Mode [1:0]
C5(3)
C6(4)
1
+
FMT0
17
OSR
16
Oversampling
AGND
SCKI
15
System Clock
7
PDWN
VDD
14
8
BYPAS
DGND
13
9
FSYNC
DOUT
12
Data Out
BCK
11
Data Clock
4
VREF2
5
VCC
6
Power Down
LCF Bypass
R1(5)
5V
+
0V
Control
Format [1:0]
+
C4(2)
PCM1802
+
Control
10 LRCK
3.3 V
C3(2)
0V
L/R Clock
Audio Data
Processor
Frame Sync.
S0026-02
Copyright © 2016, Texas Instruments Incorporated
(1)
C1, C2: A 1-µF capacitor gives a 8-Hz (τ = 1 µF × 20 kΩ) cutoff frequency for input HPF in normal operation and
requires a power-on settling time with a 20-ms time constant during the power-on initialization period.
(2)
C3, C4: Bypass capacitors, 0.1-µF ceramic and 10-µF tantalum, depending on layout and power supply
(3)
C5: TI recommends 0.1-µF ceramic and 10-µF tantalum capacitors.
(4)
C6: TI recommends 0.1-µF ceramic and 10-µF tantalum capacitors when using a noisy analog power supply. These
capacitor are not required for a clean analog supply.
(5)
R1: TI recommends a 1-kΩ resistor when using a noisy analog power supply. This resistor is shorted for a clean
analog supply.
Figure 28. Typical Circuit Connection
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 10 as the input parameters.
Table 10. Design Parameters
PARAMETER
VALUE
Analog input voltage
0 VP–P to 3 VP–P
Output
PCM audio data
System clock input frequency
2.048 MHz to 49.152 MHz
Output sampling frequency
8 kHz to 96 kHz
Power supply
3.3 V and 5 V
8.2.2 Detailed Design Procedure
8.2.2.1 Control Pins
The FMT, MODE, OSR, and BYPASS control pins are controlled by tying up to VDD, down to GND, or driven
with GPIO from the DSP or audio processor.
8.2.2.2 DSP or Audio Processor
In this application a DSP or audio processor acts as the audio master, and the PCM1802 acts as the audio
slave. This means the DSP or audio processor must be able to output audio clocks that the PCM1802 can use to
process audio signals.
8.2.2.3 Input Filters
For the analog input circuit an AC-coupling capacitor must be placed in series with the input. This removes the
DC component of the input signal. An RC filter can also be implemented to filter out of band noise to reduce
aliasing. Equation 1 calculates the cutoff frequency of the optional RC filter for the input.
1
fc =
2pRC
(1)
8.2.3 Application Curve
0
Input Level = −0.5 dB
Data Points = 8192
−20
Amplitude − dB
−40
−60
−80
−100
−120
−140
0
5
10
15
20
f − Frequency − kHz
G015
Figure 29. Amplitude vs Frequency
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9 Power Supply Recommendations
The PCM1802 requires a 5-V nominal supply and a 3.3-V nominal supply. The 5-V supply is for the analog
circuitry powered by the VCC pin. The 3.3-V supply is for the digital circuitry powered by the VDD pin. The
decoupling capacitors for the power supplies must be placed close to the device pins.
10 Layout
10.1 Layout Guidelines
10.1.1 VCC and VDD Pins
The digital and analog power supply lines to the PCM1802 must be bypassed to the corresponding ground pins
with 0.1-µF ceramic and 10-µF tantalum capacitors as close to the pins as possible to maximize the dynamic
performance of the ADC.
10.1.2 AGND and DGND Pins
To maximize the dynamic performance of the PCM1802, the analog and digital grounds are not connected
internally. These grounds must have low impedance to avoid digital noise feeding back into the analog ground.
They must be connected directly to each other under the parts to reduce the potential noise problem.
10.1.3 VIN Pins
TI recommends a 1-µF capacitor for AC-coupling, which gives an 8-Hz cutoff frequency. A higher full-scale input
voltage, if required, can be accommodated by adding only one series resistor to each VIN pin.
10.1.4 VREF1 Pin
TI recommends a ceramic capacitor of 0.1 µF and an electrolytic capacitor of 10 µF between VREF1 and AGND
to ensure low source impedance for the ADC references. These capacitors must be placed as close as possible
to the VREF1 pin to reduce dynamic errors on the ADC references.
10.1.5 VREF2 Pin
The differential voltage between VREF2 and AGND sets the analog input full-scale range. TI recommends a
ceramic capacitor of 0.1 µF and an electrolytic capacitor of 10 µF between VREF2 and AGND with the insertion
of a 1-kΩ resistor between VCC and VREF2 when using a noisy analog power supply. These capacitors and
resistor are not required for a clean analog supply. These capacitors must be placed as close as possible to the
VREF2 pin to reduce dynamic errors on the ADC references. Full-scale input level is affected by this 1-kΩ
resistor, decreasing by 3%.
10.1.6 DOUT Pin
The DOUT pin has enough load drive capability, but TI recommends placing a buffer near the PCM1802 and
minimizing load capacitance if the DOUT line is long, to minimize the digital-analog crosstalk and maximize the
dynamic performance of the ADC.
10.1.7 System Clock
The quality of the system clock can influence dynamic performance, as the PCM1802 operates based on the
system clock. In slave mode, it may be necessary to consider the system-clock duty cycle, jitter, and the time
difference between the system clock transition and the BCK or LRCK transition.
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10.2 Layout Example
It is recommended to place a top layer ground pour for
shielding around PCM1802 and connect to lower main PCB
ground plane by multiple vias
Option External RC
antialiasing circuit
1 F
R-ch IN
+
L-ch IN
VINL
MODE1
20
2
VINR
MODE0
19
3
VREF1
FMT1
18
4
VREF2
FMT0
17
5
VCC
OSR
16
6
AGND
SCKI
15
7
PDWN
VDD
14
+
1
1 F
+
Control
+
Make sure to have
ground pour separating
the Left and Right
channel traces to help
prevent crosstalk
Bypass Capacitors are
0.1 uF and 10 uF
5V
PCM1802
Make sure to have
ground pour separating
the clock signals from
surrounding traces
+
10 F
0.1 F
3.3V
+
Control
8
BYPAS
DGND
13
9
TEST
DOUT
12
10
LRCK
BCK
11
Top Layer Ground Pour
Top Layer Signal Traces
0.1 F
10 F
Clock signals to
DSP or Audio
Processor
Via to bottom Ground Plane
Pad to top layer ground pour
Figure 30. Layout Recommendation
Submit Documentation Feedback
Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: PCM1802
25
PCM1802
SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016
www.ti.com
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
System Two, Audio Precision are trademarks of Audio Precision.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
Submit Documentation Feedback
Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: PCM1802
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM1802DB
ACTIVE
SSOP
DB
20
65
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1802
PCM1802DBG4
ACTIVE
SSOP
DB
20
65
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 85
PCM1802
PCM1802DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1802
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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