PCM3008T/2KG4

PCM3008 SLAS332 – APRIL 2001 LOW POWER AND LOW VOLTAGE 16-BIT, SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODEC FEATURES D 16-Bit Delta-Sigma ADC and DAC D Stereo ADC: D D D D D D D D – Single-Ended Voltage Input – Anti-Aliasing Filter Included – High Performance – THD+N: –84 dB – SNR: 88 dB – Dynamic Range: 88 dB – 1/64× Decimation Digital Filter – Passband Ripple: ±0.05 dB – Stopband Attenuation: –65 dB – Digital HPF Included Stereo DAC: – Single-Ended Voltage Output – Analog LPF and FIR Filter Included – High Performance – THD+N: –88 dB – SNR: 92 dB – Dynamic Range: 92 dB – 8× Oversampling Digital Filter – Passband Ripple: ±0.1 dB – Stopband Attenuation: –43 dB Audio Data Format: – ADC: 16-bit, Left-Justified – DAC: 16-bit, Right-Justified Special Built-In Functions: – Digital De-Emphasis: 32, 44.1, 48 kHz – ADC/DAC Independent Power Down With Pop-Noise Free Muting Sampling Rate: 8 kHz to 48 kHz System Clock: 256fS, 384fS, 512fS Low Voltage Power Supply: – 2.4 V TYP, 2.1 V MIN to 3.6 V MAX Low Power Dissipation: – 32 mW at VCC = 2.4 V Package: 16-Pin TSSOP APPLICATIONS D Digital Video Camera D Portable MD Player D Other Portable System DESCRIPTION The PCM3008 is a low cost single chip 16-bit stereo audio codec with single-ended analog voltage input and output. Both ADCs and DACs employ delta-sigma modulation with 64-times oversampling. ADCs include a digital decimation filter and digital high pass filter. DACs include an 8-times oversampling digital interpolation filter, digital de-emphasis filter and pop-noise free muting which works during the power down ON/OFF sequence. The PCM3008 accepts left-justified format for ADC, and right-justified format for DAC. Independent power-down modes for ADC and DAC are provided. The PCM3008 is suitable for a wide variety of cost-sensitive consumer applications where good performance is required. It is fabricated using a highly advanced CMOS process and is available in a small 16-pin TSSOP package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 PCM3008 SLAS332 – APRIL 2001 PCM3008 PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 VCOM VINR VINL GND VCC DEM0 DEM1 DOUT 16 15 14 13 12 11 10 9 VOUTR VOUTL PDDA PDAD BCK SYSCK LRCK DIN PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER OPERATION TEMPERATURE RANGE PACKAGE MARKING PCM3008T TSSOP–16 ZZ363{ –25 °C ° to +85 °C ° PCM3008T ORDERING NUMBER(1) TRANSPORT MEDIA PCM3008T Rails PCM3008T/2K Tape and Reel † TI equivalent no. 4040064. NOTE: Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of PCM3008T/2K will get a single 2000-piece tape and reel. block diagram VINL Analog Front-End Circuit + Decimation and High Pass Filter Delta-Sigma Modulator – LRCK Serial Interface VCOM VINR VOUTL Reference DIN Analog Front-End Circuit Analog Low-Pass Filter + Delta-Sigma Modulator Decimation and High Pass Filter Delta-Sigma Modulator Interpolation Filter 8× Oversampling – DOUT DEM0 De-Emphasis Control DAC VOUTR Analog Low-Pass Filter DEM1 Interpolation Filter 8× Oversampling Delta-Sigma Modulator Power Down Control Clock Power Supply VCC 2 BCK ADC GND www.ti.com SYSCK PDDA PDAD PCM3008 SLAS332 – APRIL 2001 0.47 µF V R IN 2 + 30 kΩ _ _ + + + – VCOM 1 + 1 µF Delta Sigma Modulator Reference Figure 1. Analog Front-End (right-channel) Terminal Assignments TERMINAL NAME NO. I/O DESCRIPTION VCOM VINR 1 – ADC/DAC common decouple (see Note 1) 2 I ADC analog input, R-channel. VINL GND 3 I ADC analog input, L-channel. 4 – Ground. VCC DEM0 5 – Power supply. 6 I De-emphasis control 0 (see Note 2) DEM1 7 I De-emphasis control 1 (see Note 2) DOUT 8 O Data output DIN 9 I Data input (see Note 2) LRCK 10 I Sampling clock input (see Note 2) SYSCK 11 I System clock input (see Note 2) BCK 12 I Bit clock input (see Note 2) PDAD 13 I ADC power down, active low (see Note 2) PDDA 14 I DAC power down, active low (see Note 2) VOUTL VOUTR 15 O DAC analog output, L-channel. 16 O DAC analog output, R-channel. NOTES: 1. Connect decouple capacitor to GND. 2. Schmitt trigger input, open state can not be allowed because of no internal pullup or pulldown. www.ti.com 3 PCM3008 SLAS332 – APRIL 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Digital input voltage: DEM0, DEM1, DIN, LRCK, SYSCK, BCK, PDAL, PDDA . . . . . . . . . . . . . . –0.3 V to 4 V DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC +0.3 V Analog input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC +0.3 V Input current (any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 s Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 s † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4 www.ti.com PCM3008 SLAS332 – APRIL 2001 electrical characteristics, all specifications at TA = 25°C, VCC = 2.4 V, fs = 44.1 kHz, system clock = 384fs, fIN = 1 kHz, 16-bit data, (unless otherwise noted) PCM3008T PARAMETER DIGITAL INPUT/OUTPUT VIH(3) Input logic level VIL(3) IIN(3) Input logic current VOH(4) Output logic level VOL(4) CLOCK FREQUENCY TEST CONDITIONS System clock frequency TYP MAX 0.7 VCC IO = –400 µA IO = 400 µA VCC–0.2 0.2 8 UNIT 3.6 0.3VCC ±10 Sampling frequency fs MIN 44.1 48 256 fs 2.0480 11.2896 12.2880 384 fs 3.0720 16.9344 18.4320 512 fs 4.0960 22.5792 24.5760 VDC µA VDC kHz MHz ADC CHARACTERISTICS Resolution 16 Bits DC ACCURACY Gain mismatch channel to channel ±1 ±5 Gain error ±2 ±10 Bipolar zero error DYNAMIC PERFORMANCE(5) ±0 THD+N VIN = –0.5 dB VIN = –60 dB Dynamic range A-weighted 82 88 S/N ratio A-weighted 82 88 80 86 Channel separation –84 % of FSR –74 –26 dB ANALOG INPUT Input voltage 0.6 VCC Vp–p Center voltage 0.5 VCC V Input impedance –3 dB Antialiasing filter frequency response fIN = 20 kHz 30 kΩ 150 kHz –0.08 dB DIGITAL FILTER PERFORMANCE Passband 0.454 fs Stopband 0.583 fs ±0.05 Passband ripple Stopband attenuation –65 Delay time HPF frequency response –3 dB Hz dB 17.4 fs 0.078 fs mHz s 16 Bits DAC CHARACTERISTICS Resolution NOTES: 3. Pins 6, 7, 9, 10–14: DEM0, DEMI, DIN, LRCK, SYSCK, BCK, PDAD, PDDA, (Schmitt trigger input, 3.3 V tolerant. 4. Pin 8: DOUT 5. fIN = 1 kHz, using audio precision system II, RMS mode with 20 kHz LPF, 400 Hz HPF in calculation. www.ti.com 5 PCM3008 SLAS332 – APRIL 2001 electrical characteristics, all specifications at TA = 25°C, VCC = 2.4 V, fs = 44.1 kHz, system clock = 384fs, fIN = 1 kHz, 16-bit data, (unless otherwise noted) (continued) PCM3008T PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC ACCURACY Gain mismatch channel to channel ±1 ±5 Gain error ±2 ±10 Bipolar zero error ±2 %of FSR DYNAMIC PERFORMANCE(6) THD+N VOUT = 0 dB VOUT = –60 dB –88 Dynamic range EIAJ, A-weighted 86 92 S/N ratio EIAJ, A-weighted 86 92 84 90 –78 –30 Channel separation dB ANALOG OUTPUT Output voltage 0.6 VCC Vp–p Center voltage 0.5 VCC V Load impedance AC coupling 10 –3 dB LPF frequency response fIN = 20 kHz kΩ 250 kHz –0.03 dB DIGITAL FILTER PERFORMANCE Passband 0.445 fs Stopband 0.555 fs ±0.1 Passband ripple Stopband attenuation –43 Delay time 14.3 fs Hz dB s POWER SUPPLY REQUIREMENTS VCC Voltage range 2.1 2.4 3.6 13.2 17 8.1 10.5 5.6 7.5 20 50 ADC, DAC operation, 31.7 40.8 ADC operation 19.4 25.2 13.4 18 48 120 ADC, DAC operation, ADC operation Supply current DAC operation VCC = 2.4 V ADC, DAC power down(7) Power dissipation DAC operation VCC = 2.4 V ADC, DAC power down(7) VDC mA µA mW µW TEMPERATURE RANGE θJA Operation temperature VCC = VMIN to VMAX Thermal resistance 16-pin TSSOP fs > 24 kHz fs < 24 kHz 6. fIN = 1 kHz, using audio precision system II, RMS mode with 20 kHz LPF, 400 Hz HPF. 7. SYSCK, BCK, LRCK are stopped. 6 www.ti.com –25 85 –25 70 150 ° °C °C/W PCM3008 SLAS332 – APRIL 2001 theory of operation ADC section The PCM3008 ADC consists of a reference circuit, a stereo single-to-differential converter, a stereo fully differential 5th-order delta-sigma modulator, a digital decimation filter with high pass filter function and a serial interface circuit. The block diagram in this data sheet illustrates the architecture of the ADC section and Figure 1 shows the single-to-differential converter. An internal reference circuit with one external capacitor provides all reference voltages required by the ADC and DAC. The internal single-to-differential voltage converter saves the design, space and extra parts needed for external circuitry required by many delta-sigma converters. The internal full-differential signal processing architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at 64× oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying anti-alias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators that use a switched-capacitor topology, a comparator and a feedback loop consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The 64fs one-bit data stream from the modulator is converted to 1fs 16-bit data words by the decimation filter, which also acts as a low pass filter to remove the shaped quantization noise. The dc components are removed by a high pass filter function contained within the decimation filter. DAC section The PCM3008 DAC consists of a serial interface circuit, a 8× digital interpolation filter with de-emphasis filter function, a stereo 5th-order delta-sigma modulator, and a stereo analog FIR filter with LPF and output buffer amplifier. The block diagram in this data sheet illustrates the architecture of the DAC section. 1fs 16-bit audio data is converted to 8fs 18-bit data by an 8× oversampling interpolation filter, and then converted to 64fs one-bit data by delta-sigma modulator. One-bit digital data is converted to an analog signal by a current source D to A, and then high frequency components of the shaped quantization noise out of band is reduced by the analog FIR filter and LPF. The fade in, fade out function in digital domain, and VOUT control circuit in analog domain provide a pop-noise free muting function that is required for the power down on/off control sequence. system clock The system clock for PCM3008 must be either 256fs, 384fs or 512fs, where fs is the audio sampling frequency. The system clock must be supplied on SYSCK (pin 11). PCM3008 also has a system clock detection circuit that automatically senses 256fs, 384fs or 512fs mode, and when 384fs or 512fs system clock is used, the clock is divided into 256fs automatically. The 256fs clock is used to operate the digital filter and the modulator. The system clock must be supplied whenever power is applied and either PDAD or PDDA is HIGH, as the PCM3008 uses dynamic circuits internally. Table 1 lists the relationship of typical sampling frequency and system clock frequency, and Figure 2 illustrates the system clock timing. tSCKH H 0.7 VCC L 0.3 VCC SYSCK tSCKL 1/256 fs, 1/384 fs or 1/512 fs SYMBOL tSCKH tSCKL MIN UNIT System clock pulse width HIGH DEFINITION 15 ns System clock pulse width LOW 15 ns Figure 2. System Clock Timing www.ti.com 7 PCM3008 SLAS332 – APRIL 2001 system clock (continued) Table 1. System Clock Frequencies SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz) 32.0 256fs 8.1920 384fs 12.2880 512fs 16.3840 44.1 11.2896 16.9340 22.5792 48.0 12.2880 18.4320 24.5760 reset The ADC and DAC portions of the PCM3008 can be reset simultaneously by the power down control pins, PDAD and PDDA. This external reset using PDAD and PDDA must be always done at least once after the power is applied. Internal state is kept in reset during PDAD = low and PDDA = low and for 1024 system clock counts after PDAD = high or PDDA = high, and then the initialization sequence for ADC and DAC is started. For the ADC, DOUT is kept in ZERO during the initialization sequence and DOUT outputs normal data corresponding to the input analog signal after tADCDLY1. In the case of the DAC, the fade-in function is started, the signal level on VOUT increases gradually and reaches to full level corresponding to the input digital signal after tDACDLY1. The following figure illustrates the reset timing for power-on and the ADC/DAC output response for the power-on and reset sequence. 8 www.ti.com PCM3008 SLAS332 – APRIL 2001 PCM audio interface Digital audio data is interfaced to the PCM3008 on LRCK (pin 10), BCK (pin 12), DIN (pin 9), and DOUT (pin 8). PCM3008 can accept 16-bit standard format, right-justified 16 bit for DAC and left-justified 16 bit for ADC. PCM3008 accepts 3 types of BCK and LRCK combination, with 64, 48 or 32 clocks of BCK in one clock of LRCK. The following figures illustrate audio data input/output format and timing. 2.1 V VCC 0V Ready 1 1024 1025 1 1024 1025 SYSCK 1024 SYSCK tRSTB 1024 SYSCK After Ready PDAD After Ready PDDA Reset Release Reset Reset Release Reset Internal Reset tADCDLY1 tADCDLY1 ADC DOUT ZERO tDACDLY1 tDACDLY1 tDACDLY1 VCOM (0.5 VDD) DAC VO SYMBOL DEFINITION MIN TYP MAX 40 UNIT tRSTB tADCDLY1 PDAD = LOW and PDDA = LOW pulse width ns Initial delay time 2240/fs s tDACDLY1 Fade in, fade out time 2080/fs s Figure 3. Power-On Reset Timing DAC: 16-Bit, MSB-First, Right-Justified LRCK Left-Channel Right-Channel BCK DIN 16 1 2 3 MSB 14 15 16 LSB 1 2 3 MSB ADC: 16-Bit, MSB-First, Left-Justified LRCK Left-Channel 14 15 16 LSB Right-Channel BCK DOUT 1 2 3 MSB 14 15 16 LSB 1 2 3 MSB 14 15 16 1 LSB Figure 4. Audio Data Input/Output Format www.ti.com 9 PCM3008 SLAS332 – APRIL 2001 PCM audio interface (continued) tLRP 0.5 VCC LRCK tBL tBCH tLB tBCL 0.5 VCC BCK tBCY tDIS tDIH 0.5 VCC DIN tBDO tLDO 0.5 VCC DOUT SYMBOL DEFINITION MIN TYP MAX UNITS tBCY tBCH BCK pulse cycle time 300 ns BCK pulse width high 120 ns tBCL tBL BCK pulse width low 120 ns 40 ns tLB tLRP LRCK edge to BCK rising edge 40 ns tDIS tDIH DIN setup time tBCY 40 ns tBDO tLDO DOUT delay time to BCK falling edge 40 ns DOUT delay time to LRCK edge 40 ns tR tF Rising time of all signals 20 ns Falling time of all signals 20 ns BCK rising edge to LRCK edge LRCK pulse width DIN hold time 40 ns Figure 5. Audio Data Input/Output Timing synchronization with digital audio system PCM3008 operates with LRCK synchronized to the system clock. PCM3008 does not need a specific phase relationship between LRCK and system clock, but does require the synchronization of LRCK and system clock. If the relationship between system clock and LRCK changes more than ±4 BCK during one sample period, internal operation of DAC halts within 1/fs, and analog output is held at the last data until re-synchronization between system clock and LRCK is completed, and tDACDLY2 has elapsed. Internal operation of ADC also halts within 1/fs, and digital output is forced into ZERO code until re-synchronization between system clock and LRCK is completed and tADCDLY2 has elapsed. In case of changes less than ±4 BCK, re-synchronization does not occur and the above analog/digital output control and discontinuity do not occur. The following figure illustrates the DAC analog output and ADC digital output for loss of synchronization. During undefined data periods, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined data to normal makes a discontinuity of data on analog and digital output, which also may generate some noise in the audio signal. 10 www.ti.com PCM3008 SLAS332 – APRIL 2001 synchronization with digital audio system (continued) State of Synchronization Synchronous Asynchronous tADCDLY2 Within 1/fs ADC DOUT Normal Synchronous Zero Normal Undefined Data tDACDLY2 DAC VO Normal Last Data Normal Undefined Data SYMBOL DEFINITION MIN TYP MAX UNIT tADCDLY2 Delay time from synchronization 32/fs s tDACDLY2 Delay time from synchronization 32/fs s Figure 6. ADC and DAC Output for Loss of Synchronization SYSCK Can be stopped during PDAD = LOW and PDDA = LOW. SYSCK PDAD Zero PDDA tADCDLY1 ADC DOUT tDACDLY1 1024 SYSCK tDACDLY1 VCOM (0.5 VCC) DAC VO SYMBOL DEFINITION MIN TYP MAX UNIT tADCDLY1 Initial delay time 2240/fs s tDACDLY1 Fade in, fade out time 2080/fs s Figure 7. ADC and DAC Output for Power Down Control www.ti.com 11 PCM3008 SLAS332 – APRIL 2001 function control The PCM3008 has the following functions which are controlled by PDAD (pin 13), PDDA (pin 14), DEM0 (pin 6) and DEM1 (pin 7). power-down control PDAD: ADC power-down control pin places the ADC portion in the lowest power consumption mode. The ADC operation is stopped by disabling the clock and bias to the ADC portion, and DOUT is forced to zero during ADC power-down mode. Figure 7 illustrates the ADC DOUT response for ADC power-down ON/OFF. This does not affect the DAC operation. PDAD ADC OPERATION MODE Low ADC power down mode enable High ADC power down mode disable PDDA: DAC power-down control pin places the DAC portion in the lowest power consumption mode. The DAC operation is stopped by disabling the clock and bias to the DAC portion, and VOUT is forced to VCOM (0.5 VCC) during DAC power-down mode. Figure 7 illustrates the DAC VOUT response for DAC power-down ON/OFF. This does not affect the ADC operation. PDDA DAC OPERATION MODE Low DAC power down mode enable High DAC power down mode disable PDAD = low and PDDA = low places PCM3008 into reset state and either PDAD = high or PDDA = high returns PCM3008 to operational state. de-emphasis control DEM1, DEM0: DAC de-emphasis control pins select the de-emphasis mode as shown below. 12 DEM1 DEM0 Low Low De-emphasis 44.1 kHz ON DE-EMPHASIS MODE Low High De-emphasis OFF High Low De-emphasis 48 kHz ON High High De-emphasis 32 kHz ON www.ti.com PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS typical circuit connection The following figure illustrates a typical PCM3008 circuit connection. PCM3008 + 1 C2(see Note B) + 2 C3(see Note B) + 3 C1(see Note A) Right Channel IN A/D IN Left Channel IN 4 C4(see Note C) 2.4 V De-Emp0 Control De-Emp1 + 5 6 7 8 VCOM VOUTR VINR VOUTL VINL PDDA GND VCC PDAD BCK DEM0 SYSCK DEM1 LRCK DOUT DIN 16 + C6 (see Note D) 15 + C5 (see Note D) 14 13 12 11 10 9 POST LPF (see Note E) Right Channel OUT POST LPF (see Note E) Left Channel OUT D/A OUT D/A ON/OFF 2.4 V A/D ON/OFF PDDA Bit Clock PDAD (see Note F) System Clock L/R Clock Digital IN/OUT D/A IN A/D OUT NOTES: A. C1: 0.1 µF ceramic and 1 µF chemical typical, gives settling time with 15 ms (1 µF × 15 kΩ) time constant in power on period. B. C2, C3: 0.47 µF typical, gives 11 Hz cutoff frequency of input HPF in normal operation and gives settling time with 14 ms (0.47 µF × 30 kΩ) time constant in power on and power down off period. C. C4: 0.1 µF ceramic and 10 µF chemical typical, depending on power supply quality and pattern layout. D. C5, C6: 1 µF typical, gives 16 Hz cut-off frequency of output HPF in normal operation and gives settling time with 10 ms (1 µF × 10 kΩ) time constant in power on period. E. Post low pass filter with RIN > 10 kΩ, depending on requirement of system performance. F. Power on reset circuit in case of no power-down control requirement. board design and layout considerations power supply and grounding (VCC, GND) The analog and digital power supply lines are internally tied, and the analog and digital grounds are internally tied due to pin count limitation. The power supply VCC pin must be bypassed to the GND pin with 0.1 µF ceramic and 10 µF chemical capacitors as close to the pins as possible to maximize the dynamic performance of ADC and DAC. VIN pins A chemical capacitor from 0.47 µF to 4.7 µF is recommended as an ac coupling capacitor. Capacitance of 0.47 µF gives 11 Hz cut-off frequency at input HPF. If higher full scale input voltage is required, it can be adjusted by adding only one series resistor to VIN pins. VCOM input A 0.1 µF ceramic and a 1 µF or larger chemical capacitor are recommended between VCOM and GND to ensure low source impedance of ADC and DAC common voltage. This capacitor should be located as close as possible to the VCOM pin to reduce dynamic errors on the ADC and DAC common voltage. www.ti.com 13 PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS system clock Dynamic performance may be influenced by the quality of SYSCK. Therefore the duty cycle, jitter and threshold voltage at the SYSCK pin must be carefully managed. The SYSCK and BCK, LRCK must be supplied whenever the power is applied and either PDAD or ODDA is HIGH, as the PCM3008 uses dynamic circuits internally. reset control The PCM3008 does not have an internal power-on reset circuit. Therefore external reset control by PDAD and PDDA must always done at least once after the power is turned on. If neither PDAD nor PDDA is needed in the application, the standard reset circuit which consists of one resistor, one capacitor and one diode is recommended on PDAD and PDDA pins. external mute control Although the PCM3008 has an internal muting function for power-down ON/OFF control, if external muting control is required, the recommended control sequence is described by External Mute ON, CODEC Power Down ON, SYSCK stop and resume if necessary, CODEC Power Down OFF and External Mute OFF. 14 www.ti.com PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION PLUS NOISE AT –0.5 dB vs FREE-AIR TEMPERATURE DYNAMIC RANGE AND SNR vs FREE-AIR TEMPERATURE –78 92 –80 90 Dynamic Range And SNR – dB THD+N – Total Harmonic Distortion Plus Noise at –0.5 dB – dB ADC –82 –84 –86 –88 –50 –25 25 50 75 0 TA – Free-Air Temperature – °C SNR 88 Dynamic Range 86 84 82 –50 100 DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE TOTAL HARMONIC DISTORTION PLUS NOISE AT –0.5 dB vs SUPPLY VOLTAGE –78 92 –80 90 –82 –84 –86 –88 SNR 88 Dynamic Range 86 84 82 2 2.5 3 3.5 VCC – Supply Voltage – V 100 Figure 9 Dynamic Range And SNR – dB THD+N – Total Harmonic Distortion Plus Noise at –0.5 dB – dB Figure 8 –25 0 25 50 75 TA – Free-Air Temperature – °C 4 Figure 10 2 2.5 3 3.5 VCC – Supply Voltage – V 4 Figure 11 www.ti.com 15 PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION PLUS NOISE AT –0.5 dB vs SAMPLING FREQUENCY DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY –78 92 –80 90 Dynamic Range And SNR – dB THD+N – Total Harmonic Distortion Plus Noise at –0.5 dB – dB ADC –82 –84 –86 –88 30 35 40 45 fs – Sampling Frequency – kHz SNR 88 Dynamic Range 86 84 82 30 50 Figure 12 35 40 45 fs – Sampling Frequency – kHz 50 Figure 13 TOTAL HARMONIC DISTORTION PLUS NOISE AT 0 dB vs FREE-AIR TEMPERATURE DYNAMIC RANGE AND SNR vs FREE-AIR TEMPERATURE –82 96 –84 94 Dynamic Range And SNR – dB THD+N – Total Harmonic Distortion Plus Noise at 0 dB – dB DAC –86 –88 –90 –92 –50 –25 0 25 50 75 100 TA – Free-Air Temperature – °C Figure 14 16 SNR Dynamic Range 92 90 88 86 –50 –25 0 25 50 75 TA – Free-Air Temperature – °C Figure 15 www.ti.com 100 PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION PLUS NOISE AT 0 dB vs SUPPLY VOLTAGE DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE –82 96 SNR –84 Dynamic Range And SNR – dB THD+N – Total Harmonic Distortion Plus Noise at 0 dB – dB DAC –86 –88 –90 –92 2 2.5 3 3.5 VCC – Supply Voltage – V 94 Dynamic Range 92 90 88 86 4 2 TOTAL HARMONIC DISTORTION PLUS NOISE AT 0 dB vs SAMPLING FREQUENCY DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY –82 96 –84 94 –86 –88 –90 –92 30 35 40 45 fs – Sampling Frequency – kHz 4 Figure 17 Dynamic Range And SNR – dB THD+N – Total Harmonic Distortion Plus Noise at 0 dB – dB Figure 16 2.5 3 3.5 VCC – Supply Voltage – V 50 Figure 18 SNR 92 Dynamic Range 90 88 86 30 35 40 45 fs – Sampling Frequency – kHz 50 Figure 19 www.ti.com 17 PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS ADC DAC OUTPUT SPECTRUM OUTPUT SPECTRUM 0 0 dB, N = 8192 –0.5 dB, N = 8192 –20 –20 –40 –40 Amplitude – dB Amplitude – dB 0 –60 –80 –60 –80 –100 –100 –120 –120 –140 –140 0 5 10 15 f – Frequency – kHz 0 20 5 10 15 f – Frequency – kHz Figure 20 Figure 21 OUTPUT SPECTRUM OUTPUT SPECTRUM 0 –60 dB, N = 8192 –60 dB, N = 8192 –20 –20 –40 –40 Amplitude – dB Amplitude – dB 0 –60 –80 –60 –80 –100 –100 –120 –120 –140 –140 0 5 10 15 f – Frequency – kHz 20 Figure 22 18 20 0 5 10 15 f – Frequency – kHz Figure 23 www.ti.com 20 PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS ADC DAC THD+N – Total Harmonic Distortion Plus Noise – dB TOTAL HARMONIC DISTORTION PLUS NOISE vs SIGNAL LEVEL 0 –20 –40 –60 –80 –80 –60 –40 –20 0 0 –20 –40 –60 –80 –100 –100 –80 –60 –40 Signal Level – dB Signal Level – dB Figure 24 –20 0 Figure 25 SUPPLY CURRENT vs SUPPLY VOLTAGE 2 20 ADC+DAC 16 1.6 12 1.2 ADC 8 0.8 DAC 0.4 4 I D– Power Down Supply Current – mA –100 –100 I CC– Supply Current – mA THD+N – Total Harmonic Distortion Plus Noise – dB TOTAL HARMONIC DISTORTION PLUS NOISE vs SIGNAL LEVEL Power Down 0 0 2 2.5 3 3.5 VCC – Supply Voltage – V 4 Figure 26 www.ti.com 19 PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS 20 2 16 1.6 ADC+DAC 1.2 12 ADC 8 0.8 DAC 0.4 4 Power Down 0 0 10 20 30 40 fs – Sampling Frequency – kHz 0 50 Figure 27 DAC OUTBAND NOISE SPECTRUM 0 BPZ, N = 8192 –20 Amplitude – dB –40 –60 –80 –100 –120 –140 0 20 40 60 f – Frequency – kHz Figure 28 20 www.ti.com 80 100 I D– Power Down Supply Current – mA I CC– Supply Current – mA SUPPLY CURRENT vs SAMPLING FREQUENCY PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS ADC digital decimation filter frequency response STOPBAND ATTENUATION OVERALL CHARACTERISTIC 0 0 x fs x fs –20 Amplitude – dB Amplitude – dB –40 –80 –40 –60 –120 –80 –100 –160 0 8 16 24 Normalized Frequency – Hz 0 32 Figure 29 0.2 0.4 0.6 0.8 Normalized Frequency – Hz Figure 30 PASSBAND RIPPLE TRANSIENT BAND RESPONSE 0.2 0 x fs x fs –4 Amplitude – dB Amplitude – dB 0 –0.2 –0.4 –0.6 –0.8 1 –8 –12 –16 0 0.1 0.2 0.3 0.4 Normalized Frequency – Hz 0.5 Figure 31 –20 0.46 0.48 0.50 0.52 Normalized Frequency – Hz 0.54 Figure 32 www.ti.com 21 PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS digital high pass filter frequency response STOPBAND CHARACTERISTIC PASSBAND CHARACTERISTIC 0 0 x fs/1000 x fs/1000 –0.2 Amplitude – dB Amplitude – dB –20 –40 –60 –0.6 –0.8 –80 –100 –0.4 –1 0 0.1 0.2 0.3 Normalized Frequency – Hz 0.4 0 1 2 3 Normalized Frequency – Hz Figure 33 4 Figure 34 analog antialiasing filter frequency response PASSBAND CHARACTERISTIC 0 0 –10 –0.2 Amplitude – dB Amplitude – dB STOPBAND CHARACTERISTIC –20 –30 –40 –50 1 –0.6 –0.8 10 100 1k f – Frequency – kHz 10 k Figure 35 22 –0.4 –1 0.01 0.1 10 1 f – Frequency – kHz Figure 36 www.ti.com 100 PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS DAC digital interpolation and de-emphasis filter frequency response STOPBAND ATTENUATION DE-EMPHASIS CHARACTERISTIC (32 kHz) 0 0 x fs x fs Amplitude – dB Amplitude – dB –20 –40 –60 –4 –8 –80 –12 –100 0 1 2 3 Normalized Frequency – Hz 0 4 Figure 37 0.1 0.2 0.3 0.4 Normalized Frequency – Hz 0.5 Figure 38 PASSBAND RIPPLE DE-EMPHASIS CHARACTERISTIC (44.1 kHz) 0 0.2 x fs x fs Amplitude – dB Amplitude – dB 0 –0.2 –0.4 –4 –8 –0.6 –0.8 –12 0 0.1 0.2 0.3 0.4 Normalized Frequency – Hz 0.5 Figure 39 0 0.1 0.2 0.3 0.4 Normalized Frequency – Hz 0.5 Figure 40 www.ti.com 23 PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS DAC digital interpolation and de-emphasis filter frequency response (continued) DE-EMPHASIS CHARACTERISTIC (48 kHz) TRANSIENT BAND RESPONSE 0 0 x fs x fs Amplitude – dB Amplitude – dB –4 –8 –12 –4 –8 –16 –20 0.46 0.48 0.50 0.52 Normalized Frequency – Hz –12 0.54 0 0.1 0.2 0.3 0.4 Normalized Frequency – Hz Figure 41 0.5 Figure 42 analog FIR filter frequency response PASSBAND CHARACTERISTIC STOPBAND CHARACTERISTIC 0 0.2 x fs x fs 0 Amplitude – dB Amplitude – dB –10 –20 –30 –40 –0.4 –0.6 –50 –0.8 0 16 24 8 Normalized Frequency – Hz 32 Figure 43 24 –0.2 0 0.1 0.2 0.3 0.4 Normalized Frequency – Hz Figure 44 www.ti.com 0.5 PCM3008 SLAS332 – APRIL 2001 TYPICAL CHARACTERISTICS analog low pass filter frequency response PASSBAND CHARACTERISTIC 0 –10 –0.2 Amplitude – dB Amplitude – dB STOPBAND CHARACTERISTIC 0 –20 –30 –0.4 –0.6 –0.8 –40 –50 1 10 1k 100 f – Frequency – kHz 10 k Figure 45 –1 0.01 0.1 10 1 f – Frequency – kHz 100 Figure 46 www.ti.com 25 ® PACKAGE DRAWINGS MPDS090 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) PCM3008T/2K ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 PCM 3008T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of