PCM3794A

Burr Brown Products from Texas Instruments PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 16-Bit, Low-Power Stereo Audio CODEC With Microphone Bias, Headphone, and Digital Speaker Amplifier FEATURES • Analog Front End: – Stereo Single-Ended Input With Multiplexer – Mono Differential Input – Stereo Programmable Gain Amplifier – Microphone Amplifier (20 dB) and Bias Analog Back End: – Stereo/Mono Line Output With Volume – Stereo/Mono Headphone Amplifier With Volume and Capless Mode – Stereo/Mono Digital Speaker Amplifier (BTL) With Volume Analog Performance: – Dynamic Range: 93 dB (DAC) – Dynamic Range: 90 dB (ADC) – 40-mW + 40-mW Headphone Output at RL = 16 Ω – 700-mW + 700-mW Speaker Output at RL = 8 Ω Power Supply Voltage – 1.71 V to 3.6 V for Digital I/O Section – 1.71 V to 3.6 V for Digital Core Section – 2.4 V to 3.6 V for Analog Section – 2.4 V to 3.6 V for Power Amplifier Section Low Power Dissipation: – 7 mW in Playback, 1.8 V/2.4 V, 48 kHz – 13 mW in Record, 1.8 V/2.4 V, 48 kHz – 3.3 µW in Power Down Sampling Frequency: 5 kHz to 50 kHz Automatic Level Control for Recording Operation From a Single Clock Input Without PLL System Clock: – Common-Audio Clock (256 fS/384 fS), 12/24, 13/26, 13.5/27, 19.2/38.4, 19.68/39.36 MHz Headphone Plug Insert Detection • • 2 (I2C) or 3 (SPI) Wire Serial Control Programmable Function by Register Control: – Digital Attenuation of DAC: 0 dB to –62 dB – Digital Gain of DAC: 0, 6, 12, 18 dB – Power Up/Down Control for Each Module – 6-dB to –70-dB Gain for Analog Outputs – 30-dB to –12-dB Gain for Analog Inputs – 0/20 dB Selectable for Microphone Input – 0-dB to –21-dB Gain for Analog Mixing – Parameter Settings for ALC – Three-Band Tone Control and 3D Sound – High-Pass Filter: 4-, 120-, 240-Hz – Two-Stage Programmable Notch Filter – Analog Mixing Control Pop-Noise Reduction Circuit Short and Thermal Protection Circuit Package: 5-mm × 5-mm QFN Pacakge Operation Temperature Range: –40°C to 85°C • • • • • • • • • • APPLICATIONS Portable Audio Player, Cellular Phone Video Camcorder, Digital Movie/Still Camera PMP/DMB • DESCRIPTION The PCM3793A/94A is a low-power stereo CODEC designed for portable digital audio applications. The device integrates stereo digital speaker amplifier, headphone amplifier, line amplifier, line input, boost amplifier, microphone bias, programmable gain control, analog mixing, sound effects, and automatic level control (ALC). It is available in a small-footprint, 5-mm × 5-mm QFN package. The PCM3793A/94A supports right-justified, left-justified, I2S, and DSP formats, providing easy interfacing to audio DSP and decoder/encoder chips. Sampling rates up to 50 kHz are supported. The user-programmable functions are accessible through a two- or three-wire serial control port. • • • • • Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) MAX Supply voltage Input voltage Input current (any pins except supplies and SPK out) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (reflow, peak) (1) VDD, VIO, VCC, VPA –0.3 to 4 ±0.1 –0.3 to 4 ±10 –40 to 110 –55 to 150 150 260 260 Ground voltage differences: DGND, AGND, PGND UNIT V V V mA °C °C °C °C, 5 s °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VCC, VPA VDD, VIO Analog supply voltage Digital supply voltage Digital input logic family Digital input clock frequency SCKI system clock LRCK sampling clock LOL and LOR Analog output load resistance Analog output load capacitance Digital output load capacitance TA Operating free-air temperature –40 HPOL and HPOR SPOLP, SPOLN, SPORP and SPORN 3.072 8 10 16 8 30 10 85 2.4 1.71 NOM 3.3 3.3 CMOS 18.432 48 MHz kHz kΩ Ω Ω pF pF °C MAX 3.6 3.6 UNIT V V 2 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data (unless otherwise noted). PARAMETER Audio Data Characteristics DATA FORMAT Resolution Audio data interface format Audio data bit length Audio data format Sampling frequency (fS) System clock Digital Input/Output Logic family VIH VIL IIH IIL VOH VOL Input logic level Input logic current Output logic level VIN = 3.3 V VIN = 0 V IOH = –2 mA IOL = 2 mA 0.75 VIO 0.25 VIO 0.7 VIO 0.3 VIO 10 –10 CMOS compatible VDC µA VDC VDD < 2 V VDD > 2 V 5 16 I2S, left-, rightjustified, DSP 16 MSB first, 2s complement 50 27 40 kHz MHz Bits Bits TEST CONDITIONS PCM3793ARHB, PCM3794ARHB MIN TYP MAX UNIT Digital Input to Line Output Through DAC (LOL, LOR, and MONO) RL = 10 kΩ, ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = disabled DYNAMIC PERFORMANCE Full-scale output voltage Dynamic range SNR Signal-to-noise ratio Channel separation THD+N Total harmonic distortion + noise 0 dB Load resistance Line Input to Line Output Through Mixing Path (LOL, LOR, and MONO) RL = 10 kΩ, ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = enabled DYNAMIC PERFORMANCE Full-scale input and output voltage SNR Signal-to-noise ratio 0 dB EIAJ, A-weighted 84 2.828 1 93 Vp-p Vrms dB 10 0 dB EIAJ, A-weighted EIAJ, A-weighted 86 2.828 1 93 93 91 0.008% kΩ Vp-p Vrms dB dB dB Submit Documentation Feedback 3 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data (unless otherwise noted). PARAMETER TEST CONDITIONS PCM3793ARHB, PCM3794ARHB MIN TYP MAX UNIT Digital Input to Headphone Output Through DAC (HPOL and HPOR) RL = 16 Ω or 32 Ω, ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = disabled, not capless mode DYNAMIC PERFORMANCE Full-scale output voltage SNR Signal-to-noise ratio 0 dB EIAJ, A-weighted 30 mW, RL = 32 Ω, volume = 0 dB 40 mW, RL = 16 Ω, volume = –1 dB 16 200 Hz, 140 mVp-p PSRR Power-supply rejection ratio 1 kHz, 140 mVp-p 20 kHz, 140 mVp-p Line Input to Headphone Output Through Mixing Path (HPOL and HPOR) RL = 16 Ω or 32 Ω, ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = enabled, not capless mode DYNAMIC PERFORMANCE Full-scale output voltage SNR Signal-to-noise ratio Load resistance RL = 8 Ω, ALC = OFF, volume = 0 dB, headphone = powered down, analog mixing = disabled DYNAMIC PERFORMANCE Full-scale output voltage SNR Signal-to-noise ratio Load resistance 200 Hz, 140 mVp-p PSRR Power-supply rejection ratio 1 kHz, 140 mVp-p 20 kHz, 140 mVp-p RL = 8Ω, ALC = OFF, volume = 0 dB, headphone = powered down, analog mixing = enabled DYNAMIC PERFORMANCE Full-scale output voltage SNR Signal-to-noise ratio 0 dB EIAJ, A-Weighted 84 2.52 0.9 93 Vp-p Vrms dB 0 dB EIAJ, A-weighted 84 8 –50 –45 –25 dB 2.52 0.9 93 0.3% Ω Vp-p Vrms dB 0 dB EIAJ, A-weighted 84 16 2.828 1 93 Vp-p Vrms dB Ω –40 –45 –32 dB 84 2.828 1 93 0.1% 0.03% Ω Vp-p Vrms dB THD+N Total harmonic distortion + noise Load resistance Digital Input to Speaker Output Through DAC (SPOLP, SPOLN, SPORP, and SPORN): PCM3793A THD+N Total harmonic distortion + noise 400 mW, RL = 8Ω, volume = 0 dB Line Input to Speaker Output Through Mixing Path (SPOLP, SPOLN, SPORP, and SPORN): PCM3793A 4 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data (unless otherwise noted). PARAMETER TEST CONDITIONS PCM3793ARHB, PCM3794ARHB MIN TYP MAX UNIT Line Input to Digital Output Through ADC (AIN1L/R, AIN2L/R, AIN3L, and AIN3L/R) ALC = OFF, microphone boost = 0 dB, PGA = 0 dB, speaker and headphone = powered down, analog mixing = disabled DYNAMIC PERFORMANCE Full-scale input voltage Dynamic range SNR Signal-to-noise ratio Channel separation THD+N Total harmonic distortion + noise –1 dB ANALOG INPUT Center voltage Input impedance Microphone Bias ALC = OFF, microphone boost = 0 dB, PGA = 0 dB, speaker and headphone = powered down, analog mixing = disabled Bias voltage Bias source current Output noise Filter Characteristics INTERPOLATION FILTER FOR DAC Pass band Stop band Pass-band ripple Stop-band attenuation Group delay De-emphasis error ANALOG FILTER FOR DAC Frequency response DECIMATION FILTER FOR ADC Pass band Stop band Pass-band ripple Stop-band attenuation Group delay HIGH-PASS FILTER FOR ADC –3 dB, fc = 4 Hz –0.5 dB, fc = 4 Hz Frequency response –0.1 dB, fc = 4 Hz –3 dB, fc = 240 Hz –0.5 dB, fc = 240 Hz –0.1 dB, fc = 240 Hz 3.74 10.66 24.2 235.68 609.95 2601.2 Hz f < 3.268 fS –60 17/fS 0.591 fS ±0.02 dB dB s 0.408 fS f = 20 kHz ±0.2 dB –50 19/fs ±0.1 0.546 fS ±0.04 dB dB s dB 0.454 fS 0.75 VCC 2 6.5 V mA µV 10 0.5 VCC 20 V kΩ 0 dB EIAJ, A-weighted EIAJ, A-weighted 83 2.828 1 90 90 87 0.009% Vp-p Vrms dB dB dB Submit Documentation Feedback 5 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data (unless otherwise noted). PARAMETER Power Supply and Supply Current VIO VDD VCC VPA Supply current Power dissipation Temperature Condition Operation temperature θJA Thermal resistance –40 30 85 °C °C/W BPZ input, all active, no load All inputs are held static BPZ input All inputs are held static Voltage range 1.71 1.71 2.4 2.4 3.3 3.3 3.3 3.3 24.3 1 80.2 3.3 3.6 3.6 3.6 3.6 35 10 115.5 33 mA µA mW µW VDC TEST CONDITIONS PCM3793ARHB, PCM3794ARHB MIN TYP MAX UNIT 6 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 PIN ASSIGNMENTS PCM3793ARHB (TOP VIEW) AIN2L AIN1R AIN1L MODE MS/ADR MD/SDA MC/SCL LRCK 24 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 HPOL/LOL AIN2R AIN3R AGND AIN3L MICB VCOM VCC HPOR/LOR SPOLP SPOLN PGND VPA SPORP SPORN HPCOM/MONO 2 3 4 5 6 7 8 DOUT VDD DGND SCKI HDTI BCK DIN VIO P0048-05 PCM3794ARHB (TOP VIEW) AIN2L AIN1R AIN1L MODE MS/ADR MD/SDA MC/SCL LRCK 24 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 HPOL/LOL AIN2R AIN3R AGND AIN3L MICB VCOM VCC HPOR/LOR NC NC PGND VPA NC NC HPCOM/MONO 2 3 4 5 6 7 8 DOUT VDD DGND SCKI HDTI BCK DIN VIO P0048-06 Submit Documentation Feedback 7 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Table 1. TERMINAL FUNCTIONS TERMINAL NAME AGND AIN1L AIN1R AIN2L AIN2R AIN3L AIN3R BCK DGND DIN DOUT HDTI HPCOM/MONO HPOL/LOL HPOR/LOR LRCK MC/SCL MD/SDA MICB MODE MS/ADR PGND SCKI SPOLN SPOLP SPORN SPORP VCC VCOM VDD VIO VPA PCM3793ARHB 19 27 26 25 24 23 22 1 6 2 3 8 9 17 16 32 31 30 21 28 29 13 7 14 15 10 11 20 18 5 4 12 PCM3794ARHB 19 27 26 25 24 23 22 1 6 2 3 8 9 17 16 32 31 30 21 28 29 13 7 – – – – 20 18 5 4 12 I/O – I I I I I I I/O – I O I O O O I/O I I/O O I I – I O O O O – – – – – Ground for analog Analog input 1 for L-channel Analog input 1 for R-channel Analog input 2 for L-channel Analog input 2 for R-channel Analog input 3 for L-channel Analog input 3 for R-channel Serial bit clock Digital ground Serial audio data input Serial audio data output Headphone plug insertion detection Headphone common/mono line output Headphone/lineout for R-channel Headphone/lineout for L-channel Left and right channel clock Mode control clock for three-wire/two-wire interface Mode control data for three-wire/two-wire interface Microphone bias source output Two- or three-wire interface selection (LOW: SPI, HIGH: I2C) Mode control select for three-wire/two-wire interface Ground for speaker power amplifier System clock Speaker output L-channel for negative (PCM3793A) Speaker output L-channel for positive (PCM3793A) Speaker output R-channel for negative (PCM3793A) Speaker output R-channel for positive (PCM3793A) Analog power supply Analog common voltage Power supply for digital core Power supply for digital I/O Power supply for power amplifier DESCRIPTION 8 Submit Documentation Feedback www.ti.com Possible for Power Up/Down SCKI LRCK DIN DOUT BCK MD/SDA MC/SCL MS/ADR MODE PCM3794 has no Speaker Output Power On Reset Audio Interface Serial Interface (SPI/I C) DGC 0, +6, +12, +18 dB PG1 PG5 Analog Input L-ch 2 Power Up/Down Manager Clock Manager SPL SPOLP SPOLN +6 to –70 dB FUNCTIONAL BLOCK DIAGRAM ATR Mute ATP 0 to –62 dB, Mute SPR SPORP SPORN +6 to –70 dB AIN3L AIN2L AIN1L 0/+20 dB 0 to –21 dB ADL DAL Digital Filter DAR Digital Filter (1) (1) MUX1 MUX3 SW1 MXL SW2 SW3 SW6 MXR SW5 SW4 ROUT MONO HPL LOUT +6 to –70 dB PG3 Digital Filter ADR PG4 +30 to –12 dB Digital Filter (1) (1) D2S +30 to –12 dB DS ADC DS DAC HPOL/ LOL MUX2 AIN1R AIN2R AIN3R MUX4 Submit Documentation Feedback DS ADC DS DAC PG6 Analog Input R-ch 0/+20 dB 0 to –21 dB (1) HPR HPOR/ LOR +6 to –70 dB PG2 HPC MONO COM HPOL HPOR HDTI Decimation Filter Interpolation Filter 3-D Enhancement 3-Band Tone Control Notch Filter HPCOM /MONO MCB MICB Mic Bias VCOM VCOM COM VIO VDD DGND VPA PGND VCC AGND B0181-02 SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 PCM3793A PCM3794A 9 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 8 to 48 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted. INTERPOLATION FILTER, STOP BAND 0 0.2 INTERPOLATION FILTER, PASS BAND –20 0.1 Amplitude – dB –60 Amplitude – dB 0 1 2 Frequency [´ fS ] 3 4 G001 –40 0 –80 –0.1 –100 –120 –0.2 0 0.1 0.2 0.3 Frequency [´ fS ] 0.4 0.5 G002 Figure 1. DECIMATION FILTER, STOP BAND 0 0.2 Figure 2. DECIMATION FILTER, PASS BAND –20 0.1 Amplitude – dB –60 Amplitude – dB 0 1 2 Frequency [´ fS ] 3 4 G003 –40 0 –80 –0.1 –100 –120 –0.2 0 0.1 0.2 0.3 Frequency [´ fS ] 0.4 0.5 G004 Figure 3. Figure 4. 10 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 8 to 48 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted. HIGH-PASS FILTER PASS-BAND CHARACTERISTICS (fC = 4 Hz at fS = 48 kHz) 5 HIGH-PASS FILTER PASS-BAND CHARACTERISTICS (fC = 120 Hz at fS = 48 kHz) 5 0 0 Amplitude – dB –5 Amplitude – dB 0 0.0005 0.001 0.0015 Frequency [´ fS ] 0.002 G005 –5 –10 –10 –15 –15 –20 –20 0 0.005 0.01 Frequency [´ fS ] 0.015 0.02 G025 Figure 5. HIGH-PASS FILTER PASS-BAND CHARACTERISTICS (fC = 240 Hz at fS = 48 kHz) 5 Figure 6. 0 Amplitude – dB –5 –10 –15 –20 0 0.01 0.02 Frequency [´ fS ] 0.03 0.04 G006 Figure 7. Submit Documentation Feedback 11 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted. THREE-BAND TONE CONTROL (BASS, MIDRANGE, TREBLE) 15 15 THREE-BAND TONE CONTROL (BASS) 10 10 Amplitude – dB 0 Amplitude – dB 100k G007 5 5 0 –5 –5 –10 –10 –15 0.01 –15 0.1 1 10 100 Frequency – Hz 1k 10k 0 200 400 600 Frequency – Hz 800 1k G008 Figure 8. THREE-BAND TONE CONTROL (MIDRANGE) 15 15 Figure 9. THREE-BAND TONE CONTROL (TREBLE) 10 10 0 Amplitude – dB 0 5k G009 Amplitude – dB 5 5 0 –5 –5 –10 –10 –15 1k 2k 3k Frequency – Hz 4k –15 2k 4k 6k 8k 10k Frequency – Hz 12k 14k G010 Figure 10. Figure 11. 12 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted. ADC SNR AT HIGH GAIN (PG1/PG2 = 0 dB) 100 90 85 90 Single Input 85 80 75 Single Input Differential Input 70 fIN = 1 kHz ADC SNR AT HIGH GAIN (PG1/PG2 = 20 dB) SNR – dB SNR – dB 70 65 60 Differential Input 55 50 60 50 fIN = 1 kHz 40 0 5 10 15 20 PG3/PG4 Gain – dB 25 30 G011 45 40 0 5 10 15 20 PG3/PG4 Gain – dB 25 30 G012 Figure 12. THD+N/SNR vs POWER SUPPLY DAC TO SPEAKER OUTPUT, 8-Ω 1 fIN = 1 kHz 0.8 94 95 Figure 13. THD+N/SNR vs POWER SUPPLY DAC TO HEADPHONE OUTPUT, 16-Ω 0.05 fIN = 1 kHz 0.04 THD+N 94 95 THD+N – % SNR – dB THD+N 0.4 SNR 0.2 92 0.02 SNR 92 91 0.01 91 0 2 2.5 3 Power Supply – V 3.5 4 90 0 2 G013 90 2.5 3 Power Supply – V 3.5 4 G014 Figure 14. Figure 15. Submit Documentation Feedback SNR – dB 0.6 93 THD+N – % 0.03 93 13 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted. THD+N/SNR vs POWER SUPPLY DAC TO LINE OUTPUT, 10-kΩ 0.012 fIN = 1 kHz 0.011 SNR 94 0.011 THD+N 95 0.012 fIN = 1 kHz 91 THD+N/SNR vs POWER SUPPLY ADC TO DIGITAL OUTPUT 92 THD+N – % SNR – dB 0.009 THD+N 92 0.009 SNR 89 0.008 91 0.008 88 0.007 2 2.5 3 Power Supply – V 3.5 4 90 0.007 2 G015 87 2.5 3 Power Supply – V 3.5 4 G016 Figure 16. OUTPUT POWER vs POWER SUPPLY (HEADPHONE, 16-Ω) 120 fIN = 1 kHz 100 700 900 800 fIN = 1 kHz Figure 17. OUTPUT POWER vs POWER SUPPLY (SPEAKER, 8-Ω) Output Power – mW 80 Output Power – mW Vol = +6 dB 600 500 400 300 200 Vol = 0 dB Vol = 6 dB 60 Vol = 0 dB 40 20 100 0 2 2.5 3 Power Supply – V 3.5 4 G017 0 2 2.5 3 Power Supply – V 3.5 4 G018 Figure 18. Figure 19. 14 Submit Documentation Feedback SNR – dB 0.010 93 THD+N – % 0.010 90 www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted. THD+N vs OUTPUT POWER (HEADPHONE, 16-Ω, VOLUME = 6 dB) 100 fIN = 1 kHz 10 2.4 V 1 fIN = 1 kHz THD+N vs OUTPUT POWER (HEADPHONE, 16-Ω, VOLUME = 0 dB) 3.3 V THD+N – % THD+N – % 2.4 V 0.1 1 2.7 V 3.6 V 2.7 V 3.3 V 3.6 V 0.1 0.01 0 20 40 60 80 Output Power – mW 100 120 G019 0.01 0 20 40 60 Output Power – mW 80 G020 Figure 20. THD+N vs OUTPUT POWER (SPEAKER, 8-Ω, VOLUME = 6 dB) 100 fIN = 1 kHz 10 1 fIN = 1 kHz 2.4 V 2.4 V 3.3 V Figure 21. THD+N vs OUTPUT POWER (SPEAKER, 8-Ω, VOLUME = 0 dB) 2.7 V 3.6 V THD+N – % THD+N – % 3.3 V 0.1 1 2.7 V 3.6 V 0.1 0.01 0 200 400 600 Output Power – mW 800 1000 G021 0.01 0 100 400 200 300 Output Power – mW 500 600 G022 Figure 22. Figure 23. Submit Documentation Feedback 15 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted. OUTPUT SPECTRUM (DAC TO HEADPHONE OUTPUT, 16-Ω) 0 fIN = 1 kHz/–60 dB –20 –40 –20 –40 OUTPUT SPECTRUM (DAC TO SPEAKER OUTPUT, 8-Ω) 0 fIN = 1 kHz/–60 dB Amplitude – dB –60 –80 –100 –120 –140 0 5 10 Frequency – kHz 15 20 G023 Amplitude – dB –60 –80 –100 –120 –140 0 5 10 Frequency – kHz 15 20 G024 Figure 24. Figure 25. 16 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 PCM3793A/94A DESCRIPTION Analog Input The AIN1L, AIN1R, AIN2L, AIN2R, AIN3L, and AIN3R pins can be used as microphone or line inputs with selectable 0- or 20-dB boost and 1-Vrms input. All of these analog inputs have high input impedance (20 kΩ), which is not changed by gain settings. One pair of inputs is selected by register 87 (AIL[1:0], AIR[1:0]). AIN1L and AIN1R can be used as a monaural differential input. Gain Settings for Analog Input The gain of the analog signals can be adjusted from 30 dB to –12 dB in 1-dB steps following the 0- or 20-dB boost amplifier. The gain level can be set for each channel by registers 79 and 80 (ALV[5:0], ARV[5:0]). A/D Converter The ADC includes a multilevel delta-sigma modulator, aliasing filter, decimation filter, high-pass filter, and notch filter and can accept a 1-Vrms full-scale voltage input. The decimation filter has a digital soft mute controlled by register 81 (RMUL, RMUR). The high-pass filter can be disabled by register 81 (HPF[1:0]), and the notch filter can be disabled by registers 96 to 104 if it is not necessary to cancel a dc offset or compensate for wind noise. D/A Converter The DAC includes a multilevel delta-sigma modulator and an interpolation filter. These can be used to obtain high PSRR, low jitter sensitivity, and low out-of-band noise quickly and easily. The interpolation filter includes digital attenuator, digital soft mute, three-band tone control (bass, midrange and treble), and 3-D sound controlled by registers 92 to 95. The de-emphasis filter (32, 44.1 and 48 kHz) is controlled by registers 68 to 70 (ATL[5:0], ATR[5:0], PMUL, PMUR, DEM[1:0]). Oversampling rate control can reduce out-of-band noise when operating at low sampling rates by using register 70 (OVER). Common Voltage The VCOM pin is normally biased to 0.5 VCC, and it provides the common voltage to internal circuitry. It is recommended that a 4.7-µF capacitor be connected between this pin and AGND to provide clean voltage and avoid pop noise. The PCM3793A/94A may have a little pop noise on each analog output if a capacitor smaller than 4.7 µF is used. Line Output The HPOL/LOL, HPOR/LOR, and HPCOM/MONO pins can drive a 10-kΩ load and be configured by register 74 (HPS[1:0]) as a monaural single-ended, monaural differential, or stereo single-line output with 1-Vrms output. These outputs, except for the HPCOM/MONO pin, include an analog volume amplifier that can be set from 6 dB to –70 dB and mute in steps of 0.5-, 1-, 2- or 4-dB. Each output is controlled by registers 64 and 65 (HLV[5:0], HRV[5:0], HMUL, HMUR). No dc blocking capacitor is required when connecting an external speaker amplifier with monaural differential input. The center voltage is 0.5 VCC with zero data input. Headphone Output The HPOL/LOL, HPOR/LOR, and HPCOM/MONO pins can be configured as a stereo, monaural, or monaural differential headphone output by register 74 (HPS[1:0]). These pins have more than 30 or 40 mWrms output power into a 32- or 16-Ω load, either through a dc blocking capacitor or without a capacitor. These outputs, except for the HPCOM/MONO pin, include an analog volume amplifier that can be set from 6 dB to –70 dB in steps of 0.5, 1, 2, or 4 dB. Each is controlled by registers 64 and 65 (HLV[5:0], HRV[5:0], HMUL, HMUR). The center voltage is 0.5 VCC with zero data input. Headphone Plug Insertion Detection The HDTI pin detects the insertion status of headphone plug and writes the status to register 77 (HPDS), which can be read by the I2C interface. The polarity of the status indication can be inverted by register 75 (HPDP). The headphone and speaker amplifiers are disabled or enabled automatically by headphone plug insertion/extractrion if register 75, HPDE = 1. They follow the register settings if register 75, HPDE = 0. HPCOM/MONO is not affected by the status when register 74, CMS[0] = 1. 17 Submit Documentation Feedback PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Speaker Output (Class-D, PCM3793A) The SPOLP/SPOLN and SPORP/SPORN pins are stereo or mono speaker differential outputs (BTL) pairs with a maximum of 700 mWrms (VPA = 3.6 V, volume = 6 dB) into an 8-Ω load. The digital speaker amplifier offers maximum battery life, minimum heat, and elimination of LC low-pass filtering. The speaker amplifier includes an analog volume control with 6 dB to –70 dB in steps of 0.5, 1, 2 or 4 dB steps for each output, which can be set by registers 66 (SLV[5:0] and 67 SRV[5:0]). Spectrum spreading technology and selectable switching frequency to reduce EMI noise are controlled by register 71 (DFQ[2:0], SPS[1:0] and SPSE). This digital amplifier has a thermal shutdown circuit that detects when the device temperature reaches approximately 150°C; then the speaker amplifier is shut down. Analog Mixing and Bypass Mixing amplifiers (MXL, MXR) mix inputs from the AIN pins. The analog inputs are selected by register 87 (AD2S, AIR[1:0],AIL[1:0]) and can bypass the ADC/DAC and connect the mixed signal to the headphone or speaker outputs by register 88 (MXR[2:0], MXL[2:0]). The gain of the analog inputs is controlled by register 89 (GMR[2:0], GML[2:0]). These functions are suitable for FM radio, headset, and other analog sources without an ADC. Microphone Bias The MICB pin is the microphone bias source for an external microphone. MICB can provide 2 mA (typical) of bias current. Digital Gain Control A portable application with small speakers may be require a high sound level when playing back audio data recorded at low level. Digital gain control (DGC) can be used to amplify the digital input data by 0, 6, 12 or 18 dB by setting register 70 (SPX[1:0]). Automatic Level Control (ALC) for Recording The sound for microphone recording should be expanded to a suitable level without saturation. The digitally controlled automatic level control (ALC) provides automatic expansion for small input signals and compression for large input signals while recording. The expansion level, compression level, attack time, and recovery time can be selected by register 83. The register 83 description explains the details of these settings. 3-D Sound A 3-D sound effect is provided by mixing L-channel and R-channel data with a band-pass filter with two parameters, mixing ratio and band pass filter characteristic, that can be controlled by register 95 (3DP[3:0], 3FLO). The 3-D sound effect uses the DAC digital input or ADC digital output selected by register 95 (SDAS). Three-Band Tone Control Tone control has bass, midrange, and treble controls that can be adjusted from 12 dB to –12 dB in 1-dB steps by registers 92 to 94 (LGA[4:0], MGA[4:0] and HGA[4:0]). Register 92 (LPAE) attenuates the digital input signal automatically to prevent clipping of the output signal at settings above 0 dB for bass control. LPAE has no effect on midrange and treble controls. High-Pass Filter and Two-Stage Programmable Notch Filter The high-pass filter eliminates the dc offset of the ADC analog signal and can be set for a cutoff frequency of 4 Hz, 120 Hz, or 240 Hz at the 48-kHz sampling frequency by register 81 (HPF[1:0]). A register 95 (SDAS) selection applies the filter to either the DAC digital input or the ADC digital output. Notch filters are provided to remove noise of a particular frequency, such as CCD noise, motor noise, or other mechanical noise in a particualr application. The PCM3793A/94A has two notch filters for which the center frequency and frequency bandwidth can be programmed by registers 96 to 104. A register 95 (SDAS) selection applies the filter to either the DAC digital input or the ADC digital output. 18 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Digital Monaural Mixing The audio data can be converted from stereo digital data to mixed monaural digital data. The conversion occurs in the internal audio interface section and is controlled by register 96 (MXEN). Zero-Cross Detection Zero-cross detection minimizes audible zipper noise while changing analog volume and digital attenuation. This function applies to the digital input or digital output as defined by register 86 (ZCRS). Short Protection The short-circuit protection on each headphone output prevents damage to the device while an output is shorted to VPA, an output is shorted to PGND, or any two outputs are shorted together. When the short circuit is detected on the outputs, the PCM3793A/94A powers down the shorted amplifier immediately. The short-protection status can be monitored by reading register 77 (STHC, STHL, SCHR) through the I2C interface. Short-circuit protection operates in any enabled headphone amplifier. Thermal Protection The thermal protection on the speaker amplifier prevents damage to the device when the internal die temperature exceeds approximately 150°C. Once the die temperature exceeds the thermal set point, all analog outputs are powered down. This status can be reset by setting register 76 (RLSR, RLSL) and can be watched by reading register 77 (STSR, STSL) through the two-wire (I2C) interface. Thermal protection operates in any enabled speaker amplifier. Pop-Noise Reduction Circuit The pop-noise reduction circuit prevents audible noise when turning the power supply on/off and powering the device up/down in portable applications. It is recommended to establish the register settings in the sequence that is shown in Table 3 and Table 4. No particular external parts are required. Power Up/Down for Each Module Using register 72 (PMXL, PMXR), register 73 (PBIS, PDAR, PDAL, PHPC, PHPR, PHPL, PSPR, PSPL), register 82 (PAIR, PAIL, PADS, PMCB, PADR, PADL), and register 90 (PCOM), unused modules can be powered down to minimize power consumption (7 mW during playback only and 13 mW when recording only). Digital Audio Interface The PCM3793A/94A can receive I2S, right-justified, left-justified, and DSP formats in both master and slave modes. These options can be selected in register 70 (PFM[1:0]), register 81 (RFM[1:0]) and register 84 (MSTR). Digital Interface All digital I/O pins can interface at various power supply voltages. VIO pin can be connected to a 1.71-V to 3.6-V power supply. Power Supply The VCC pin and the VPA pin can be connected to 2.4 V to 3.6 V. The same voltage must be applied to both pins. The VDD pin and the VIO pin can be connected to 1.71 V to 3.6 V. A different voltage can be applied to each of these pins (for example, VDD = 1.8 V, VIO = 3.3 V). Submit Documentation Feedback 19 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com DESCRIPTION OF OPERATION System Clock Input The PCM3793A/94A can accept clocks of various frequencies without a PLL. They are used for clocking the digital filters and automatic level control and delta-sigma modulators and are classified as common-audio and application-specific clocks. Table 2 shows frequencies of the common-audio clock and application-specific clock. Figure 26 shows the timing requirements for system clock inputs. The sampling rate and frequency of the system clocks are determined by the settings of register 86 (MSR[2:0]) and register 85 (NPR[5:0]). Note that the sampling rate of the application-specific clock has a little sampling error. The details are shown in Table 12. Table 2. System Clock Frequencies CLOCK Common-audio clock Application-specific clock FREQUENCIES 11.2896, 12.288, 16.9344, 18.432 MHz 12, 13, 13.5, 24, 26, 27, 19.2, 19.68, 38.4, 39.36 MHz tw(SCKH) 0.7 VIO SCKI 0.3 VIO tw(SCKL) T0005-12 PARAMETERS System-clock pulse duration, high System-clock pulse duration, low SYMBOL tw(SCKH) tw(SCKL) MIN 7 7 UNITS ns ns Figure 26. System Clock Timing Power-On Reset and System Reset The power-on-reset circuit outputs a reset signal, typically at VDD = 1.2 V, and this circuit does not depend on the voltage of other power supplies (VCC, VPA, and VIO). Internal circuits are cleared to default status, then signals are removed from all analog and digital outputs. The PCM3793A/94A does not require any power supply sequencing. Register data must be written after turning all power supplies on. System reset is enabled by setting register 85 (SRST = 1). After the reset sequence, the register data is reset to SRST = 0 automatically. All circuits are cleared to their default status at once by the system reset. Note that the PCM3793A/94A has audible pop noise on the analog outputs when enabling SRST. Power On/Off Sequence To reduce audible pop noise, a sequence of register settings is required after turning all power supplies on when powering up, or before turning the power supplies off when powering down. If some modules are not required for a particular application or operation, they should be placed in the power-down state after performing the power-on sequence. The recommended power-on and power-off sequences are shown in Table 3 and Table 4, respectively. 20 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Table 3. Recommended Power-On Sequence STEP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (1) (2) (3) (4) (5) REGISTER SETTINGS – 4027h 4127h 4227h 4327h 4427h 4527h 4620h 4BC0h 5102h 5A10h 49E0h 5601h 4803h 5811h 49FCh 4C03h 4A01h 523Fh 5711h 4F0Ch 500Ch – 49FFh Turn on all power supplies (1) Headphone amplifier L-ch volume (–6 dB) (2) Headphone amplifier R-ch volume (–6 dB) (2) Speaker amplifier L-ch volume (–6 dB) (2) Speaker amplifier R-ch volume (–6 dB) (2) Digital attenuator L-ch (–24 dB) (2) Digital attenuator R-ch (–24 dB) (2) DAC audio interface format (left-justified) (3) Headphone detection enable and inverting polarity. Short and thermal detection enable ADC audio interface format (left-justified) (3) VCOM ramp up/down time control. PG1, PG2 gain control (0 dB) DAC (DAL, DAR) and analog bias power up Zero-cross detection enable Analog mixer (MXL, MXR) power up Analog mixer input (SW2, SW5) select Headphone amplifier (HPL, HPR, HPC) power up Speaker amplifier shut down release VCOM power up Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power up Analog input (MUX3, MUX4) select. Analog input (MUX1, MUX2) select Analog input L-ch (PG3) volume (0 dB) (2) Analog input R-ch (PG4) volume (0 dB) (2) Any settings for other devices or wait time, 450 ms (4) (5) Speaker amplifier (SPL, SPR) power up (5) NOTE VDD should be turn on prior to or simultaneously with the other power supplies. It is recommended to set register data with the system clock input after turning all power supplies on. Any level is acceptable for volume or attenuation. Level should be resumed by register data recorded when system power off. Audio interface format should be set to match the DSP or decoder being used. The PCM3793A requires time for VCOM to reach the common level from GND level. The delay depends on the capacitor value for VCOM and the setting of register 125 PTM[1:0], RES[4:0]. The default setting is 450 ms at VCOM = 4.7 µs. The PCM3794A does not require this setting because it has no speaker output. Submit Documentation Feedback 21 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Table 4. Recommended Power-Off Sequence STEP 1 2 3 4 5 6 7 8 9 10 11 12 13 (1) (2) (3) (4) (5) (6) REGISTER SETTINGS 447Fh 457Fh 5132h 5811h 49FCh 5200h 5A00h 4A00h – 49E0h 4800h 4900h – DAC L-ch digital soft-mute enable (1) DAC R-ch digital soft-mute enable (1) ADC L-ch/R-ch digital soft-mute enable, ADC audio interface format (left-justified) (2) Analog mixer input (SW2, SW5) select Headphone amplifier (HPL, HPR, HPC) power up PG1, PG2 gain control (0 dB) VCOM power down Wait time (750 ms) (5) (3) (4) NOTE Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power down Headphone amplifier (HPL, HPR, HPC) power down, speaker amplifier (SPL, SPR) power down Analog mixer (MXL, MXR) power down DAC (DAL, DAR) and analog bias power down Turn off all power supplies. (6) Any level is acceptable for volume or attenuation. Audio interface format should be set to match the DSP or decoder in the application. The PCM3794A has no speaker amplifier. The headphone amplifier must be operating during the power-off sequence. PCM3793A requires time for VCOM to reach the ground level from the common level. The wait time allowed depends on the settings of register 125 PTM[1:0], RES[4:0]. The default setting is 750 ms for VCOM = 4.7 µF. Power supply sequencing is not required. It is recommended to turn off all power supplies after setting the registers with the system clock input. Power-Supply Current The current consumption of the PCM3793A/94A depends on power up/down status of each circuit module. In order to reduce the power consumption, disabling each module is recommended when it is not used in an application or operation. Table 5 shows the current consumption in some states. 22 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Table 5. Power Consumption Table OPERATION MODE VDD (1.8 V) All Power Down All Active PLAYBACK WITH DIGITAL INPUT Line output and headphone output Headphone output with sound effect Capless headphone output Headphone output with line input (AIN2L/AIN2R) Headphone output with mono microphone input (AIN1L, 20 dB) Headphone output with mono differential microphone input (AIN1L/AIN1R, 20 dB) Stereo speaker output Mono speaker output Speaker output with line input (AIN2L/AIN2R) Speaker output with mono microphone input (AIN1L, 20 dB) Speaker output with mono differential microphone input (AIN1L/AIN1R, 20 dB) PLAYBACK WITHOUT DIGITAL INPUT Line input (AIN2L/AIN2R) to headphone output Mono line input (AIN2L) to headphone output Mono microphone Input (AIN1L, 20 dB) to headphone output Mono differential microphone input (AIN1L/AIN1R, 20 dB) to headphone output Mono microphone input (AIN1L, 20 dB) to speaker output RECORDING Line input (AIN3L/AIN3R) Microphone input (AIN1L/AIN1R, 20 dB) Microphone input (AIN1L/AIN1R, 20 dB) with ALC Mono microphone input (AIN1L, 20 dB) Mono microphone input (AIN1L, 20 dB) with ALC Mono differential microphone input (AIN1L/AIN1R, 20 dB) Mono differential microphone input (AIN1L/AIN1R, 20 dB) with ALC Conditions: 48 kHz/256 fS, 16 bits, slave mode, zero data input, no load 1.86 1.86 2.78 1.4 2.2 1.4 2.2 3.89 3.91 5.77 2.93 4.74 2.94 4.74 4.58 5.14 5.14 3.6 3.6 3.96 3.96 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.1 0.1 0.1 0.1 0.1 0.1 0.1 19.1 21.1 22.7 15.2 16.6 16.3 17.8 28.7 30.6 36.8 22.3 28.3 23.5 29.5 0 0 0 0 0 0 0 0 0 0 0.76 0.61 1.18 1.48 1.57 0.53 0.53 0.53 0.53 10.92 0 0 0 0 0 4.3 3.8 5.6 6.6 41.2 4.3 3.8 5.6 6.6 41.2 1.18 1.81 1.18 1.18 1.18 1.18 1.21 1.2 1.21 1.21 1.2 2.51 3.84 2.51 2.52 2.52 2.52 2.58 2.57 2.57 2.58 2.58 1.79 1.79 1.8 2.09 2.5 2.8 2.18 2.01 2.48 2.89 3.2 0.54 0.54 0.75 0.54 0.54 0.54 10.94 5.61 10.95 10.96 10.98 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 10.1 11.2 10.8 11.1 12.5 13.4 45.8 27.6 46.8 48.2 49.3 16.3 20.7 17.0 17.3 18.6 19.6 52.1 33.9 53.1 54.5 55.6 0 2.5 POWER SUPPLY CURRENT [mA] VDD (3.3 V) 0 5.1 VCC (3.3 V) 0.007 7.5 VPA (3.3 V) 0.002 11.6 VIO (3.3 V) 0 0.1 PD [mW] TOTAL (VDD = 1.8 V) 0.03 67.7 PD [mW] TOTAL (VDD = 3.3 V) 0.03 80.2 Audio Serial Interface The audio serial interface for the PCM3793A/94A comprises LRCK, BCK, DIN, and DOUT. Sampling rate (fS), left and right channel are present on LRCK. DIN receives the serial data for the DAC interpolation filter, and DOUT transmits the serial data from the ADC decimation filter. BCK clocks the transfer of serial audio data on DIN and DOUT in its high-to-low transition. BCK and LRCK should be synchronized with audio system clock. Ideally, it is recommended that they be derived from it. The PCM3793A/94A requires LRCK to be synchronized with the system clock. The PCM3793A/94A does not require a specific phase relationship between LRCK and the system clock. The PCM3793A/94A has both master mode and slave mode interface formats, which can be selected by register 84 (MSTR). In master mode, the PCM3793A/94A generates LRCK and BCK from the system clock. Audio Data Formats and Timing The PCM3793A/94A supports I2S, right-justified, left-justified, and DSP formats. The data formats are shown in Figure 29 and are selected using registers 70 and 81 (RFM[1:0], PFM[1:0]). All formats require binary 2s-complement, MSB-first audio data. The default format is I2S. Figure 27 shows a detailed timing diagram. Submit Documentation Feedback 23 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com LRCK tw(BCL) 50% of VIO tw(BCH) BCK t(LB) 50% of VIO t(BL) t(BCY) DIN t(DH) t(DS) DOUT t(CKDO) t(LRDO) 50% of VIO T0010-09 50% of VIO PARAMETERS t(BCY) tw(BCH) tw(BCL) t(BL) t(LB) t(DS) t(DH) t(CKDO) t(LRDO) tr tf (1) BCK pulse cycle time (I2S, left- and right-justified formats) BCK pulse cycle time (DSP format) BCK high-level time BCK low-level time BCK rising edge to LRCK edge LRCK edge to BCK rising edge DIN set up time DIN hold time DOUT delay time from BCK falling edge DOUT delay time from LRCK falling edge Rising time of all signals Falling time of all signals fS is the sampling frequency. MIN 1/(64 fS) (1) 1/(256 fS) (1) 35 35 10 10 10 10 MAX UNITS ns ns ns ns ns ns 15 15 10 10 ns ns ns ns Figure 27. Audio Interface Timing (Slave Mode) 24 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 t(SCY) SCKI 50% of VIO t(DL) LRCK (Output) tw(BCL) tw(BCH) BCK (Output) 50% of VIO t(DB) t(DB) 50% of VIO t(BCY) DIN DOUT 50% of VIO t(DS) t(DH) T0011-04 PARAMETERS t(SCY) t(DL) t(DB) t(BCY) tw(BCH) tw(BCL) t(DS) t(DH) (1) SCKI pulse cycle time LRCK edge from SCKI rising edge BCK edge from SCKI rising edge BCK pulse cycle time BCK high level time BCK low level time DATA setup time DATA hold time fS is up to 48 kHz. fS is the sampling frequency. MIN 1/(256 fS) (1) 0 0 1/(64 fS) (1) 146 146 10 10 MAX 40 40 UNIT ns ns ns ns ns ns Figure 28. Audio Interface Timing (Master Mode) Submit Documentation Feedback 25 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com (a) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) 16-Bit Right-Justified DIN/DOUT 14 15 16 1 2 3 14 15 16 LSB 1 2 3 14 15 16 LSB MSB MSB (b) I2S Data Format; L-Channel = LOW, R-Channel = HIGH 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS or 64 fS) DIN/DOUT 1 2 3 14 15 16 LSB 1 2 3 14 15 16 LSB 1 2 MSB MSB (c) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) DIN/DOUT 1 2 3 14 15 16 LSB 1 2 3 14 15 16 LSB 1 2 MSB MSB (d) Burst BCK Interface Format at Master Mode; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) DIN/DOUT 1 2 3 14 15 16 LSB 1 2 3 14 15 16 LSB 1 2 MSB MSB (e) DSP Format 1/fS LRCK BCK (= 32 fS, 48 fS, 64 fS , 128 fS or 256 fS) DIN/DOUT 1 2 3 14 15 16 LSB 1 2 3 14 15 16 LSB 1 2 MSB MSB T0009-07 NOTE: All audio interface formats support BCK = 64 fS in master mode (register 69, MSTR = 1). When setting the multisampling rate, the fS of BCK is set to half the rate of the DSP operation frequency. Figure 29. Audio Data Input and Output Formats 26 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 THREE-WIRE INTERFACE (SPI, MODE (PIN 28) = LOW) All write operations for the serial control port use 16-bit data words. Figure 30 shows the control data word format. The most-significant bit must be 0. There are seven bits, labeled IDX[6:0], that set the register address for the write operation. The least-significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Figure 31 shows the functional timing diagram for writing to the serial control port. To write the data into the mode register, the data is clocked into an internal shift register on the rising edge of the MC clock. The serial data should change on the falling edge of the MC clock, and MS should be LOW during write mode. The rising edge of MS should be aligned with the falling edge of the last MC clock pulse in the 16-bit frame. MC can run continuously between transactions while MS is in the LOW state. MSB 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 LSB D0 Register Index (or Address) Register Data R0001-01 Figure 30. Control Data Word Format for MD (1) Single Write Operation 16 Bits MS MC MD MSB LSB MSB (2) Continuous Write Operation 8 Bits x N Frames MS MC MD MSB LSB MSB LSB MSB LSB MSB LSB Register Index 8 Bits Register (N) Data Register (N+1) Data Register (N+2) Data N Frames T0012-03 Figure 31. Register Write Operation Submit Documentation Feedback 27 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Three-Wire Interface (SPI) Timing Requirements Figure 32 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper control port operation. tw(MHH) MS t(MLS) tw(MCH) MC t(MCY) MD t(MDS) t(MDH) T0013-08 50% of VIO tw(MCL) t(MLH) 50% of VIO LSB 50% of VIO PARAMETERS t(MCY) tw(MCL) tw(MCH) tw(MHH) t(MLS) t(MLH) t(MDH) t(MDS) (1) MC pulse cycle time MC low level time MC high level time MS high level time MS falling edge to MC rising edge MS hold time MD hold time MD setup time MIN 500 (1) 50 50 (1) TYP MAX UNIT ns ns ns ns ns ns ns ns 20 20 15 20 3/(128 fS) s (min), where fS is sampling rate. Figure 32. SPI Interface Timing TWO-WIRE INTERFACE [I2C, MODE (PIN 28) = HIGH] The PCM3793A/94A supports the I2C serial bus and the data transmission protocol for the I2C standard as a slave device. This protocol is explained in I2C specification 2.0. In I2C mode, the control terminals are changed as follows. TERMINAL NAME MS/ADR MD/SDA MC/SCL PROPERTY Input Input/output Input DESCRIPTION I2C address I2C data I2C clock SLAVE ADDRESS MSB 1 0 0 0 1 1 ADR LSB R/W The PCM3793A/94A has its own 7-bit slave address. The first six bits (MSBs) of the slave address are factory preset to 100011. The last bit of the address byte is the device select bit, which can be user-defined by the ADR terminal. A maximum of two PCM3793A/94As can be connected on the same bus at one time. Each PCM3793A/94A responds when it receives its own slave address. 28 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Packet Protocol The master device must control packet protocol, which consists of start condition, slave address with read/write bit, data (if write) or acknowledgement (if read), and stop condition. The PCM3793A/94A supports only slave receiver and slave transmitter. SDA SCL St 1−7 Slave Address 8 R/W 9 ACK 1−8 DATA 9 ACK 1−8 DATA 9 ACK Sp Start Condition R/W: Read Operation if 1; Otherwise, Write Operation ACK: Acknowledgement of a Byte if 0 DATA: 8 Bits (Byte) Stop Condition Write Operation Transmitter Data Type M St M Slave Address M R/W S ACK M DATA S ACK M DATA S ACK M Sp Read Operation Transmitter Data Type M St M: Master Device St: Start Condition M Slave Address S: Slave Device Sp: Stop Condition M R/W S ACK S DATA M ACK S DATA M NACK M Sp T0049-03 Figure 33. Basic I2C Framework WRITE OPERATION The master can write any PCM3793A/94A registers in a single access. The master sends a PCM3793A/94A slave address with a write bit, a register address, and data. When undefined registers are accessed, the PCM3793A/94A does not send any acknowledgement. Figure 34 shows a diagram of the write operation. Transmitter Data Type M St M Slave Address M W S ACK M Reg Address S ACK M Write Data S ACK M Sp M: Master Device S: Slave Device St: Start Condition W: Write ACK: Acknowledge Sp: Stop Condition R0002-01 Figure 34. Framework for Write Operation READ OPERATION The master can read PCM3793A/94A register. The value of the register address is stored in an indirect index register in advance. The master sends a PCM3793A/94A slave address with a read bit after storing the register address. Then the PCM3793A/94A transfers the data which the index register specifies. Figure 35 shows a diagram of the read operation. Submit Documentation Feedback 29 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Transmitter Data Type M St M Slave Address M W S ACK M Reg Address S ACK M Sr M Slave Address M R S ACK S M M Read Data NACK Sp M: Master Device S: Slave Device St: Start Condition Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge W: Write R: Read R0002-02 NOTE: The slave address after the repeated start condition must be the same as the previous slave address. Figure 35. Read Operation Timing Diagram Start t(D-HD) t(BUF) t(D-SU) t(SDA-R) t(SDA-F) t(P-SU) Stop SDA t(SCL-R) t(LOW) SCL t(RS-HD) t(SP) t(S-HD) t(SCL-F) t(HI) t(RS-SU) T0050-03 PARAMETERS fSCL t(BUF) t(LOW) t(HI) t(RS-SU) t(S-HD) t(D-SU) t(D-HD) t(SCL-R) t(SCL-R1) t(SCL-F) t(SDA-R) t(SDA-F) t(P-SU) CB t(SP) SCL clock frequency Bus free time between a STOP and START condition Low period of the SCL clock High period of the SCL clock Setup time for START condition Hold time for START condition Data setup time Data hold time Rise time of SCL signal Rise time of SCL signal after a repeated START condition and after an acknowledge bit Fall time of SCL signal Rise time of SDA signal Fall time of SDA signal Setup time for STOP condition Capacitive load for SDA and SCL line Pulse duration of suppressed spike CONDITIONS Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard MIN 4.7 4.7 4 4.7 4 250 0 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 4 MAX 100 UNIT kHz µs µs µs µs µs ns 900 1000 1000 1000 1000 1000 400 25 ns ns ns ns ns ns µs pF ns Figure 36. I2C Interface Timing 30 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 USER-PROGRAMMABLE MODE CONTROLS Register Map The mode control register map is shown in Table 6. Each register includes an index (or address) indicated by the IDX[6:0] bits. Table 6. Mode Control Register Map REGISTER Register 64 Register 65 Register 66 Register 67 Register 68 Register 69 Register 70 Register 71 Register 72 Register 73 Register 74 Register 75 Register 76 Register 77 Register 79 Register 80 Register 81 Register 82 Register 83 Register 84 Register 85 Register 86 Register 87 Register 88 Register 89 Register 90 Register 92 Register 93 Register 94 Register 95 Register 96 Register 97 Register 98 Register 99 Register 100 Register 101 Register 102 Register 103 Register 104 Register 125 IDX[6:0] (B14–B8) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 7Dh Volume for HPA (L-ch) Volume for HPA (R-ch) Volume for SPA (L-ch) Volume for SPA (R-ch) DAC digital attenuation and soft mute (L-ch) DAC digital attenuation and soft mute (R-ch) DAC over sampling, de-emphasis, audio interface SPA (class-D) switching frequency Analog mixer power up/down DAC, SPA and HPA power up/down Analog output configuration select HPA insertion detection, short/thermal protection SPA shutdown release Shut down status read back Volume for ADC input (L-ch) Volume for ADC input (R-ch) ADC high-pass filter, soft mute, audio interface ADC, MCB, PG1, 2, 5, 6, D2S power up/down Automatic level control for recording Master mode System reset, sampling rate control BCK configuration, sampling rate control, zero-cross Analog input select (MUX1, 2, 3, 4) Analog mixing switch (SW1, 2, 3, 4, 5, 6) Analog to analog path (PG5, 6) gain Microphone boost Bass boost gain level Middle boost gain level Treble boost gain level Sound effect source select, 3D sound 2-stage notch filter, digital monaural mixing 1st stage notch filter lower coefficient (a1) 1st stage notch filter upper coefficient (a1) 1st stage notch filter lower coefficient (a2) 1st stage notch filter upper coefficient (a2) 2nd stage notch filter lower coefficient (a1) 2nd stage notch filter upper coefficient (a1) 2nd stage notch filter lower coefficient (a2) 2nd stage notch filter upper coefficient (a2) Power up/down time control SPA: Speaker amplifier DAC: D/A converter ADC: A/D converter DESCRIPTION B7 RSV RSV RSV RSV RSV RSV DEM1 RSV RSV PBIS RSV HPDP RSV HPDS RSV RSV HPF1 RSV RALC RSV SRST MBST AD2S RSV RSV RSV LPAE RSV RSV SDAS NEN2 F107 F115 F207 F215 S107 S115 S207 S215 RSV B6 HMUL HMUR SMUL SMUR PMUL PMUR DEM0 RSV RSV PDAR CMS2 HPDE RSV RSV RSV RSV HPF0 RSV RSV RSV RSV MSR2 RSV MXR2 GMR2 RSV RSV RSV RSV 3DEN NEN1 F106 F114 F206 F214 S106 S114 S206 S214 PTM1 B5 HLV5 HRV5 SLV5 SRV5 ATL5 ATR5 PFM1 RSV RSV PDAL CMS1 RSV RSV RSV ALV5 ARV5 RMUL PAIR RRTC RSV NPR5 MSR1 AIR1 MXR1 GMR1 RSV RSV RSV RSV RSV NUP2 F105 F113 F205 F213 S105 S113 S205 S213 PTM0 B4 HLV4 HRV4 SLV4 SRV4 ATL4 ATR4 PFM0 SPSE RSV PHPC CMS0 SDHC RSV STHC ALV4 ARV4 RMUR PAIL RATC RSV NPR4 MSR0 AIR0 MXR0 GMR0 RSV LGA4 MGA4 HGA4 3FL0 NUP1 F104 F112 F204 F212 S104 S112 S204 S212 RES4 B3 HLV3 HRV3 SLV3 SRV3 ATL3 ATR3 SPX1 SPS1 RSV PHPR HPS1 SDHR RSV STHR ALV3 ARV3 RSV PADS RCP1 RSV NPR3 ATOD RSV RSV RSV RSV LGA3 MGA3 HGA3 3DP3 RSV F103 F111 F203 F211 S103 S111 S203 S211 RES3 B2 HLV2 HRV2 SLV2 SRV2 ATL2 ATR2 SPX0 SPS0 RSV PHPL HPS0 SDHL RSV STHL ALV2 ARV2 DSMC PMCB RCP0 MSTR NPR2 RSV RSV MXL2 GML2 RSV LGA2 MGA2 HGA2 3DP2 RSV F102 F110 F202 F210 S102 S110 S202 S210 RES2 B1 HLV1 HRV1 SLV1 SRV1 ATL1 ATR1 RSV DFQ1 PMXR PSPR SPKS SDSR RLSR STSR ALV1 ARV1 RFM1 PADR RLV1 RSV NPR1 RSV AIL1 MXL1 GML1 G20R LGA1 MGA1 HGA1 3DP1 RSV F101 F109 F201 F209 S101 S109 S201 S209 RES1 B0 HLV0 HRV0 SLV0 SRV0 ATL0 ATR0 OVER DFQ0 PMXL PSPL PCOM SDSL RLSL STSL ALV0 ARV0 RFM0 PADL RLV0 BIT0 NPR0 ZCRS AIL0 MXL0 GML0 G20L LGA0 MGA0 HGA0 3DP0 MXEN F100 F108 F200 F208 S100 S108 S200 S208 RES0 HPA: Headphone amplifier single-ended amplifier MCB: Microphone bias PGx: Analog input buffer D2S: Differential to Submit Documentation Feedback 31 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Register Definitions Registers 64 and 65 B15 Register 64 Register 65 0 0 B14 IDX6 IDX6 B13 IDX5 IDX5 B12 IDX4 IDX4 B11 IDX3 IDX3 B10 IDX2 IDX2 B9 IDX1 IDX1 B8 IDX0 IDX0 B7 RSV RSV B6 HMUL HMUR B5 HLV5 HRV5 B4 HLV4 HRV4 B3 HLV3 HRV3 B2 HLV2 HRV2 B1 HLV1 HRV1 B0 HLV0 HRV0 IDX[6:0]: 100 0000b (40h): Register 64 IDX[6:0]: 100 0001b (41h): Register 65 HMUL: Analog Mute Control for HPL (Line or Headphone L-Channel) HMUR: Analog Mute Control for HPR (Line or Headphone R-Channel) Default value: 1 HPOL/LOL and HPOR/LOR can be independently muted to zero level when HMUL and HMUR = 1. These settings take precedence over analog volume level settings. HMUL, HMUR = 0 HMUL, HMUR = 1 Mute disabled Mute enabled (default) HLV[5:0]: Analog Volume for HPL (Headphone L-Channel) HRV[5:0]: Analog Volume for HPR (Headphone R-Channel) Default value: 00 0000. HPOL/LOL and HPOR/LOR can be independently controlled between 6 dB and –70 dB, with step size depending on the gain level as shown in Table 7. Outputs may have zipper noise while changing levels. This noise can be reduced by selecting zero-cross detection (register 86, ZCRS). Table 7. Headphone Gain Level Setting HLV[5:0], HRV[5:0] 11 1111 11 1110 11 1101 11 1100 11 1011 11 1010 11 1001 11 1000 11 0111 11 0110 11 0101 11 0100 11 0011 11 0010 11 0001 11 0000 10 1111 10 1110 10 1101 10 1100 10 1011 10 1010 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 0.5 dB STEP GAIN LEVEL SETTING 6 dB 5.5 dB 5 dB 4.5 dB 4 dB 3.5 dB 3 dB 2.5 dB 2 dB 1.5 dB 1 dB 0.5 dB 0 dB –0.5 dB –1 dB –1.5 dB –2 dB –2.5 dB –3 dB –3.5 dB –4 dB – 4.5 dB HLV[5:0], HRV[5:0] 10 1001 10 1000 10 0111 10 0110 10 0101 10 0100 10 0011 10 0010 10 0001 10 0000 01 1111 01 1110 01 1101 01 1100 01 1011 01 1010 01 1001 01 1000 01 0111 01 0110 01 0101 01 0100 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 1 dB 0.5 dB STEP GAIN LEVEL SETTING –5 dB –5.5 dB –6 dB –6.5 dB –7 dB –7.5 dB –8 dB –8.5 dB –9 dB –9.5 dB –10 dB –10.5 dB –11 dB –12 dB –13 dB –14 dB –15 dB –16 dB –17 dB –18 dB –19 dB –20 dB HLV[5:0], HRV[5:0] 01 0011 01 0010 01 0001 01 0000 00 1111 00 1110 00 1101 00 1100 00 1011 00 1010 00 1001 00 1000 00 0111 00 0110 00 0101 00 0100 00 0011 00 0010 00 0001 00 0000 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 4 dB 2 dB 1 dB STEP GAIN LEVEL SETTING –21 dB –22 dB –23 dB –24 dB –26 dB –28 dB –30 dB –32 dB –34 dB –36 dB –38 dB –40 dB –42 dB –46 dB –50 dB –54 dB –58 dB –62 dB –66 dB –70 dB 32 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Registers 66 and 67 B15 Register 66 Register 67 0 0 B14 IDX6 IDX6 B13 IDX5 IDX5 B12 IDX4 IDX4 B11 IDX3 IDX3 B10 IDX2 IDX2 B9 IDX1 IDX1 B8 IDX0 IDX0 B7 RSV RSV B6 SMUL SMUR B5 SLV5 SRV5 B4 SLV4 SRV4 B3 SLV3 SRV3 B2 SLV2 SRV2 B1 SLV1 SRV1 B0 SLV0 SRV0 IDX[6:0]: 100 0010b (42h): Register 66 IDX[6:0]: 100 0011b (43h): Register 67 SMUL: Digital Soft Mute Control for SPL (Speaker Output, L-Channel) SMUR: Digital Soft Mute Control for SPR (Speaker Output R-Channel) Default value: 1 SPOLP/SPOLN and SPORP/SPORN can be independently muted to the zero level when SMUL and SMUR = 1. These settings have precedence over analog volume level settings. SMUL, SMUR = 0 SMUL, SMUR = 1 Mute disabled Mute enabled (default) SLV[5:0]: Gain Setting for SPL (Speaker Output L-Channel) SRV[5:0]: Gain Setting for SPR (Speaker Output R-Channel) Default value: 00 0000. SPOLP/SPOLN and SPORP/SPORN can be independently controlled between 6 dB and –70 dB, with step size depending on the gain level as shown in Table 8. Outputs may have zipper noise while changing levels. This noise can be reduced by selecting zero-cross detection (register 86, ZCRS). Table 8. Speaker Gain Level Setting SLV[5:0], SRV[5:0] 11 1111 11 1110 11 1101 11 1100 11 1011 11 1010 11 1001 11 1000 11 0111 11 0110 11 0101 11 0100 11 0011 11 0010 11 0001 11 0000 10 1111 10 1110 10 1101 10 1100 10 1011 10 1010 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 0.5 dB STEP GAIN LEVEL SETTING 6 dB 5.5 dB 5 dB 4.5 dB 4 dB 3.5 dB 3 dB 2.5 dB 2 dB 1.5 dB 1 dB 0.5 dB 0 dB –0.5 dB –1 dB –1.5 dB –2 dB –2.5 dB –3 dB –3.5 dB –4 dB – 4.5 dB SLV[5:0], SRV[5:0] 10 1001 10 1000 10 0111 10 0110 10 0101 10 0100 10 0011 10 0010 10 0001 10 0000 01 1111 01 1110 01 1101 01 1100 01 1011 01 1010 01 1001 01 1000 01 0111 01 0110 01 0101 01 0100 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 1 dB 0.5 dB STEP GAIN LEVEL SETTING –5 dB –5.5 dB –6 dB –6.5 dB –7 dB –7.5 dB –8 dB –8.5 dB –9 dB –9.5 dB –10 dB –10.5 dB –11 dB –12 dB –13 dB –14 dB –15 dB –16 dB –17 dB –18 dB –19 dB –20 dB SLV[5:0], SRV[5:0] 01 0011 01 0010 01 0001 01 0000 00 1111 00 1110 00 1101 00 1100 00 1011 00 1010 00 1001 00 1000 00 0111 00 0110 00 0101 00 0100 00 0011 00 0010 00 0001 00 0000 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 4 dB 2 dB 1 dB STEP GAIN LEVEL SETTING –21 dB –22 dB –23 dB –24 dB –26 dB –28 dB –30 dB –32 dB –34 dB –36 dB –38 dB –40 dB –42 dB –46 dB –50 dB –54 dB –58 dB –62 dB –66 dB –70 dB Submit Documentation Feedback 33 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Registers 68 and 69 B15 Register 68 Register 69 0 0 B14 IDX6 IDX6 B13 IDX5 IDX5 B12 IDX4 IDX4 B11 IDX3 IDX3 B10 IDX2 IDX2 B9 IDX1 IDX1 B8 IDX0 IDX0 B7 RSV RSV B6 PMUL PMUR B5 ATL5 ATR5 B4 ATL4 ATR4 B3 ATL3 ATR3 B2 ATL2 ATR2 B1 ATL1 ATR1 B0 ATL0 ATR0 IDX[6:0]: 100 0100b (44h): Register 68 IDX[6:0]: 100 0101b (45h): Register 69 PMUL: Digital Soft Mute Control for DAL (DAC, L-Channel) PMUR: Digital Soft Mute Control for DAR (DAC R-Channel) Default value: 0 The digital inputs of the DAC can be independently muted by setting PMUL and PMUR = 1. The digital data is changed from the current attenuation level to mute level by a 1-dB step for every 8/fS time period. When PMUL and PMUR are set to 0, the digital data is changed from the mute level to the current attenuation level by a 1-dB step for every 8/fS time period. In the PCM3793A/94A, audible zipper noise can be reduced by selecting zero-cross detection (register 86, ZCRS). PMUL, PMUR = 0 PMUL, PMUR = 1 Mute disabled (default) Mute enabled ATL[5:0]: Digital Attenuation Setting for DAL (L-Channel DAC) ATR[5:0]: Digital Attenuation Setting for DAR (R-Channel DAC) Default value: 11 1111b The digital inputs of the DAC can be independently attenuated. The attenuation of the digital input is changed by a 1-dB step for every 8/fS time period. Audible zipper noise in the PCM3793A/94A can be reduced by selecting zero-cross detection (register 86, ZCRS). Table 9. Digital Attenuation Setting ATL[5:0], ATR[5:0] 11 1111 11 1110 11 1101 11 1100 11 1011 11 1010 11 1001 11 1000 11 0111 11 0110 11 0101 11 0100 11 0011 11 0010 11 0001 11 0000 10 1111 10 1110 10 1101 10 1100 10 1011 10 1010 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A ATTENUATION LEVEL SETTING 0 dB (default) –1 dB –2 dB –3 dB –4 dB –5 dB –6 dB –7 dB –8 dB –9 dB –10 dB –11 dB –12 dB –13 dB –14 dB –15 dB –16 dB –17 dB –18 dB –19 dB –20 dB –21 dB ATL[5:0], ATR[5:0] 10 1001 10 1000 10 0111 10 0110 10 0101 10 0100 10 0011 10 0010 10 0001 10 0000 01 1111 01 1110 01 1101 01 1100 01 1011 01 1010 01 1001 01 1000 01 0111 01 0110 01 0101 01 0100 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 ATTENUATION LEVEL SETTING –22 dB –23 dB –24 dB –25 dB –26 dB –27 dB –28 dB –29 dB –30 dB –31 dB –32 dB –33 dB –34 dB –35 dB –36 dB –37 dB –38 dB –39 dB –40 dB –41 dB –42 dB –43 dB ATL[5:0], ATR[5:0] 01 0011 01 0010 01 0001 01 0000 00 1111 00 1110 00 1101 00 1100 00 1011 00 1010 00 1001 00 1000 00 0111 00 0110 00 0101 00 0100 00 0011 00 0010 00 0001 00 0000 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 ATTENUATION LEVEL SETTING –44 dB –45 dB –46 dB –47 dB –48 dB –49 dB –50 dB –51 dB –52 dB –53 dB –54 dB –55 dB –56 dB –57 dB –58 dB –59 dB –60 dB –61 dB –62 dB Mute 34 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Register 70 B15 Register 70 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 DEM1 B6 DEM0 B5 PFM1 B4 PFM0 B3 SPX1 B2 SPX0 B1 RSV B0 OVER IDX[6:0]: 100 0110b (46h): Register 70 DEM[1:0]: De-Emphasis Filter Selection Default value: 00 A digital de-emphasis filter is in front of the interpolation filter. One of three de-emphasis filters can be selected corresponding to thesampling rate, 32 kHz, 44.1 kHz, or 48 kHz. DEM[1:0] 00 01 10 11 De-Emphasis Filter Selection OFF (default) 32 kHz 44.1 kHz 48 kHz PFM[1:0]: Audio Interface Selection for DAC (Digital Input) Default value: 00 The audio interface for the DAC digital input has I2S, right-justified, left-justified, and DSP formats. PFM[1:0] 00 01 10 11 Audio Interface Selection for DAC Digital Input I2S format (default) Right-justified format Left-justified format DSP format SPX[1:0]: Digital Gain Control for DAC Input Default value: 00 These bits are used to gain up the digital input data. SPX[1:0] 00 01 10 11 Digital Gain Control for DAC input 0 dB (default) 6 dB 12 dB 18 dB OVER: Oversampling Control for Delta-Sigma DAC Default value: 0 This bit is used to control the oversampling rate of delta-sigma DAC. When the PCM3793A/94A operates at low sampling rates (less than 24 kHz) and the SCKI frequency is less than 12.5 MHz, OVER = 1 is recommended. OVER = 0 OVER = 1 128 fS (default) 192 fS, 256 fS, 384 fS Submit Documentation Feedback 35 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Register 71 B15 Register 71 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 RSV B5 RSV B4 SPSE B3 SPS1 B2 SPS0 B1 DFQ1 B0 DFQ0 IDX[6:0]: 100 0111b (47h): Register 71 SPSE: Enable of Spectrum Spreading Default value: 0 The class-D speaker amplifier output can cause RF interference due to switching noise. The PCM3793A can reduce peak noise by the use of spectrum spreading technology when SPSE = 1. SPSE = 0 SPSE = 1 Disable (default) Enable SPS[1:0]: Spectrum Spreading Efficiency Default value: 00 The spectrum-spreading efficiency of can be selected from low, medium, and high. SPS[1:0] 00 01 10 11 Spectrum Spreading Efficiency Low (default) Medium High Reserved DFQ[1:0]: Switching Frequency for Speaker Amplifier (Class-D) Default value: 00 The switching frequency of the class-D speaker amplifier can be selected to avoid interference with other equipment. DFQ[1:0] 00 01 10 11 Class D Amplifier Switching Frequency 1.5 MHz (default) 2.25 MHz 2.65 MHz 3 MHz Register 72 B15 Register 72 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 RSV B5 RSV B4 RSV B3 RSV B2 RSV B1 PMXR B0 PMXL IDX[6:0]: 100 1000b (48h) Register 72 PMXR: Power Up/Down for MXR (Mixer R-Channel) PMXL: Power Up/Down for MXL (Mixer L-Channel) Default value: 0 These bits are used to control power up/down for the analog mixer. PMXL, PMXR = 0 PMXL, PMXR = 1 Power down (default) Power up 36 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Register 73 B15 Register 73 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 PBIS B6 PDAR B5 PDAL B4 PHPC B3 PHPR B2 PHPL B1 PSPR B0 PSPL IDX[6:0]: 100 1001b (49h): Register 73 PBIS: Power Up/Down Control for Bias Default value: 0 This bit is used to control power up/down for the analog bias circuit. PBIS = 0 PBIS = 1 Power down (default) Power up PDAR: Power Up/Down Control for DAR (DAC and R-Channel Digital Filter) PDAL: Power Up/Down Control for DAL (DAC and L-Channel Digital Filter) Default value: 0 These bits are used to control power up/down for the DAC and interpolation filter. PDAR, PDAL = 0 PDAR, PDAL = 1 Power down (default) Power up PHPC: Power Up/Down Control for HPC (Headphone COM/Monaural Output) Default value: 0 This bit is used to control power up/down for the headphone COM or monaural line amplifier. PHPC = 0 PHPC = 1 Power down (default) Power up PHPR: Power Up/Down Control for HPR (Line or R-Channel Headphone Output) PHPL: Power Up/Down Control for HPL (Line or L-Channel Headphone Output) Default value: 0 These bits are used to control power up/down for the headphone amplifier. PHPR, PHPL = 0 PHPR, PHPL = 1 Power down (default) Power up PSPR: Power Up/Down Control for SPR (R-Channel Speaker Output, PCM3793A) PSPL: Power Up/Down Control for SPL (L-Channel Speaker Output, PCM3793A) Default value: 0 These bits are used to control power up/down for the PCM3793A speaker amplifier. These bits should be set to 0 for the PCM3794A, because it has no speaker outputs. PSPR, PSPL = 0 PSPR, PSPL = 1 Power down (default) Power up Submit Documentation Feedback 37 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Register 74 B15 Register 74 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 CMS2 B5 CMS1 B4 CMS0 B3 HPS1 B2 HPS0 B1 SPKS B0 PCOM IDX[6:0]: 100 1010b (4Ah): Register 74 CMS[2:0]: Output Selection for HPC (Headphone COM/Monaural Output) Default value: 000 The HPCOM/MONO output can be selected from several input analog sources, including inverted HPOR output, inverted HPOL output, and monaural output. CMS[2:0] 000 001 010 100 Others HPCOM/MONO Output Selection Common voltage (0.5 VCC) output for capless mode (default) Monaural output Inverted HPOL output Inverted HPOR output Reserved HPS[1:0]: Line or Headphone Output Configuration Default value: 00 HPOL/LOL and HPOR/LOR can be configured selected as follows. HPS[1:0] 00 01 10 11 Line or Headphone Output Configuration Stereo output (default) Single monaural output Differential monaural output Reserved SPKS: Speaker Output Configuration Default value: 00 SPOLP/SPOLN and SPORP/SPORN can be configured as follows. SPKS = 0 SPKS = 1 Stereo output (default) Monaural output PCOM: Power Up/Down Control for VCOM Default value: 0 This bit is used to control power up/down for VCOM. PCOM = 0 PCOM = 1 Power down (default) Power up 38 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Register 75 B15 Register 75 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 HPDP B6 HPDE B5 RSV B4 SDHC B3 SDHR B2 SDHL B1 SDSR B0 SDSL IDX[6:0]: 1001011b (4Bh): Register 75 HPDP: Headphone Insertion Detection Polarity HPDE: Enable for Headphone Insertion Detection Default value: 0 Table 10. Headphone Insertion Detection HPDE 1 1 1 1 0 HPDP 0 0 1 1 X HDTI (PIN 8) 0 1 0 1 X HP OUTPUT Down Up Up Down SP OUTPUT Up Down Down Up Headphone insertion detection disabled SDHC: Short Protection Disable for HPC (Headphone COM/Monaural Output) SDHR: Short Protection Disable for HPR (R-Channel Headphone) SDHL: Short Protection Disable for HPL (L-Channel Headphone) Default value: 0 Short-circuit protection can be disabled if this function is not needed in an application. SDHC, SDHR, SDHL = 0 SDHC, SDHR, SDHL = 1 Enabled (default) Disabled SDSR: Thermal Protection Disable for SPR (Speaker Amplifier R-Channel) SDSL: Thermal Protection Disable for SPL (Speaker Amplifier L-Channel) Default value: 0 The thermal protection circuit can be disabled if this function is not needed in an application. SDSR, SDSL = 0 SDSR, SDSL = 1 Enabled (default) Disabled Register 76 B15 Register 76 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 RSV B5 RSV B4 RSV B3 RSV B2 RSV B1 RLSR B0 RLSL IDX[6:0]: 100 1100b (4Ch): Register 76 RLSR: Reset Thermal Protection Circuit for SPR (R-Channel Speaker Amplifier) RLSL: Reset Thermal Protection Circuit for SPL (L-Channel Speaker Amplifier) Default value: 0 A thermal protection circuit puts the device in power-down status after it detects a temperature of approximately 150°C on the die. These bits must be set to 1 to restore power to the speaker amplifier. RLSR, RLSL = 0 RLSR, RLSL = 1 Operation (default) Reset (set to 0 automatically after being set to 1) Submit Documentation Feedback 39 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Register 77 B15 Register 77 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 HPDS B6 RSV B5 RSV B4 STHC B3 STHR B2 STHL B1 STSR B0 STSL IDX[6:0]: 100 1101b (4Dh): Register 77 HPDS: Headphone Detection Status Default value: 0 The HPDS bit shows the status of insertion detection for the headphone. This is a read-only bit. The polarity depends on the register 75 (HPDP) setting. HPDS = 0 HPDS = 1 HDTI input (when HPDP = 0) (default) Inverted HDTI input (When HPDP = 1) STHC: Short Protection Status for HPC (Headphone COM/Monaural Output) STHR: Short Protection Status for HPR (R-Channel Headphone) STHL: Short Protection Status for HPL (L-Channel Headphone) These bits can be used to read short protection status through the I2C interface. STHC, STHR, STHL = 0 STHC, STHR, STHL = 1 Detect short circuit Not detect short circuit STSR: Thermal Protection Status for SPR (R-Channel Speaker) STSL: Thermal Protection Status for SPL (L-Channel Speaker) These bits can be used to read thermal protection status through the I2C interface. STSR, STSL = 0 STSR, STSL = 1 Detect thermal protection Not detect thermal protection 40 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Registers 79 and 80 B15 Register 79 Register 80 0 0 B14 IDX6 IDX6 B13 IDX5 IDX5 B12 IDX4 IDX4 B11 IDX3 IDX3 B10 IDX2 IDX2 B9 IDX1 IDX1 B8 IDX0 IDX0 B7 RSV RSV B6 RSV RSV B5 ALV5 ARV5 B4 ALV4 ARV4 B3 ALV3 ARV3 B2 ALV2 ARV2 B1 ALV1 ARV1 B0 ALV0 ARV0 IDX[6:0]: 100 1111b (4Fh): Register 79 IDX[6:0]: 101 0000b (50h): Register 80 ALV[5:0]: Gain Control for PG3 (R-Channel ADC Analog Input) ARV[5:0]: Gain Control for PG4 (L-Channel ADC Analog Input) Default value: 00 The gain of the PG3 and PG4 inputs to the ADC can be independently controlled from 30 dB to –12 dB in 1-dB steps. The ADC output may have zipper noise while changing the level. This noise can be reduced by using zero-cross detection (register 86, ZCRS). Table 11. Gain Level Setting ALV[5:0], ARV[5:0] 10 1010 10 1001 10 1000 10 0111 10 0110 10 0101 10 0100 10 0011 10 0010 10 0001 10 0000 01 1111 01 1110 01 1101 01 1100 01 1011 01 1010 01 1001 01 1000 01 0111 01 0110 01 0101 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 GAIN LEVEL SETTING 30 dB 29 dB 28 dB 27 dB 26 dB 25 dB 24 dB 23 dB 22 dB 21 dB 20 dB 19 dB 18 dB 17 dB 16 dB 15 dB 14 dB 13 dB 12 dB 11 dB 10 dB 9 dB ALV[5:0], ARV[5:0] 01 0100 01 0011 01 0010 01 0001 01 0000 00 1111 00 1110 00 1101 00 1100 00 1011 00 1010 00 1001 00 1000 00 0111 00 0110 00 0101 00 0100 00 0011 00 0010 00 0001 00 0000 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 GAIN LEVEL SETTING 8 dB 7 dB 6 dB 5 dB 4 dB 3 dB 2 dB 1 dB 0 dB –1 dB –2 dB –3 dB –4 dB –5 dB –6 dB –7 dB –8 dB –9 dB –10 dB –11 dB –12 dB (default) Submit Documentation Feedback 41 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Register 81 B15 Register 81 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 HPF1 B6 HPF0 B5 RMUL B4 RMUR B3 RSV B2 DSMC B1 RFM1 B0 RFM0 IDX[6:0]: 101 0001b (51h): Register 81 HPF[1:0]: High-Pass Filter Selection Default value: 00 The PCM3793A/94A has a digital high-pass filter to remove dc voltage at the input of the ADC. The cutoff frequency of the high-pass filter can be selected. HPF [1:0] 00 01 10 11 High-Pass Filter Selection fC = 4 Hz at 48 kHz (default) fC = 240 Hz at 48 kHz fC = 120 Hz at 48 kHz High-pass filter disabled RMUL: Digital Soft Mute Control for L-Channel ADC RMUR: Digital Soft Mute Control for R-Channel ADC Default value: 1 The digital output of the ADC can be independently muted by setting RMUL and RMUR = 1. The digital data is changed from the current attenuation level to mute level by a 1-dB step for every 8/fS time period. When PMUL and PMUR are set to 0, the digital data is changed from the mute level to the current attenuation level by a 1-dB step for every 8/fS time period. In the PCM3793A/94A, audible zipper noise can be reduced by selecting zero-cross detection (register 86, ZCRS). RMUL, RMUR = 0 RMUL, RMUR = 1 Mute disabled Mute enabled (default) DSMC: Waiting Time for ADC Mute Off at Power Up Default value: 0 The ADC digital output has an optional delay after power up when DSMC = 0. It is recommended to set DSMC = 0. DSMC = 0 DSMC = 1 10 ms at 48 kHz (default) No delay RFM[1:0]: Audio Interface Selection for ADC (Digital Output) Default value: 00 The audio interface for the ADC digital input supports I2S, right-justified, left-justified, and DSP formats. RFM [1:0] 00 01 10 11 Audio Interface Selection for ADC Digital Output I2S format (default) Right-justified format Left-justified format DSP format 42 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Register 82 B15 Register 82 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 RSV B5 PAIR B4 PAIL B3 PADS B2 PMCB B1 PADR B0 PADL IDX[6:0]: 101 0010b (52h): Register 82 PAIR: Power Up/Down for PG2 and PG6 (Gain Amplifier for R-Channel Analog Input) PAIL: Power Up/Down for PG1 and PG5 (Gain Amplifier for L-Channel Analog Input) Default value: 0 These bits are used to control power up/down for PG2 and PG6 (gain amplifier for analog input). PAIR, PAIL = 0 PAIR, PAIL = 1 Power down (default) Power up PADS: Power Up/Down for D2S (Differential Amplifier) of AIN1L and AIN1R Default value: 0 This bit is used to control power up/down for D2S (differential-to-single amplifier). PADS = 0 PADS = 1 Power down (default) Power up PMCB: Power Up/Down Control for Microphone Bias Source Default value: 0 This bit is used to control power up/down for the microphone bias source. PMCB = 0 PMCB = 1 Power down (default) Power up PADR: Power Up/Down Control for ADR (ADC and R-Channel Digital Filter) PADL: Power Up/Down Control for ADL (ADC and L-Channel Digital Filter) Default value: 0 These bits are used to control power up/down for the ADC and decimation filter. PADR, PADL = 0 PADR, PADL = 1 Power down (default) Power up Submit Documentation Feedback 43 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Register 83 B15 Register 83 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RALC B6 RSV B5 RRTC B4 RATC B3 RCP1 B2 RCP0 B1 RLV1 B0 RLV0 IDX[6:0]: 101 0011b (53h): Register 83 RALC: Automatic Level Control (ALC) Enable for Recording Default value: 0 Automatic level control can be enabled with some parameters for microphone input or lower analog source level. RALC = 0 RALC = 1 Disable (default) Enable RRTC: ALC Recovery Time Control for Recording Default value: 0 This bit is used to select the recovery time for the ALC. The response is shown in Figure 37. RRTC = 0 RRTC = 1 3.4 s (default) 13.6 s RATC: ALC Attack Time Control for Recording Default value: 0 This bit is used to select the attack time for the ALC. The response is shown in Figure 37. RATC = 0 RATC = 1 Attack +FS Input Data 1 ms (default) 2 ms Recovery +FS Input Data –FS Output Data +FS Attack Time –FS Output Data +FS Recovery Time –FS –FS T0166-01 Figure 37. Attack and Recovery Time Response 44 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 RCP[1:0]: ALC Compression Level Control for Recording Default value: 00 These bits are used to set the compression level for the ALC. The characteristic is shown in Figure 38. RCP[1:0] 00 01 10 11 ALC Compression Level Control for Recording –2 dB (default) –6 dB –12 dB Reserved RLV[1:0]: ALC Expansion Level Control for Recording Default value: 00 These bits are used to set the expansion level for the ALC. The characteristic is shown in Figure 38. RLV[1:0] 00 01 10 11 ALC Gain Level Control for Recording 0 dB (default) 6 dB 14 dB 24 dB 0 dB Compression –2, –6, –12 dB Output Amplitude Expansion (0, 6, 12, 24 dB) Input Amplitude 0 dB M0057-01 Figure 38. Compression and Expansion Characteristics Submit Documentation Feedback 45 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Registers 84–86 B15 Register 84 Register 85 Register 86 0 0 0 B14 IDX6 IDX6 IDX6 B13 IDX5 IDX5 IDX5 B12 IDX4 IDX4 IDX4 B11 IDX3 IDX3 IDX3 B10 IDX2 IDX2 IDX2 B9 IDX1 IDX1 IDX1 B8 IDX0 IDX0 IDX0 B7 RSV SRST MBST B6 RSV RSV MSR2 B5 RSV NPR5 MSR1 B4 RSV NPR4 MSR0 B3 RSV NPR3 ATOD B2 MSTR NPR2 RSV B1 RSV NPR1 RSV B0 BIT0 NPR0 ZCRS IDX[6:0]: 101 0100b (54h): Register 84 IDX[6:0]: 101 0101b (55h): Register 85 IDX[6:0]: 101 0110b (56h): Register 86 MSTR: Master or Slave Selection for Audio Interface Default value: 0 This bit is used to select either master or slave mode for the audio interface. In master mode, the PCM3793A/94A generates LRCK and BCK from the system clock. In slave mode, it receives LRCK and BCK from another device. MSTR = 0 MSTR = 1 Slave interface (default) Master interface BIT0: Bit Length Selection for Audio Interface Default value: 1 This bit is used to select the data bit length for DAC input. BIT0 = 0 BIT0 = 1 Reserved 16 bits (default) SRST: System Reset Default value: 0 This bit is used to enable system reset. All circuits are reset by setting SRST = 1. After completing the reset sequence, SRST is set to 0 automatically. SRST = 0 SRST = 1 Reset disabled (default) Reset enabled NPR[5:0]: System Clock Rate Selection Default value: 000000 MSR[2:0]: System Clock Dividing Rate Selection in Master Mode (Register 70) Default value: 000 These bits are used to select the system clock rate and the dividing rate of the input system clock. See Table 12 for the details. 46 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Table 12. System Clock Frequency for Common-Audio Clock SYSTEM CLOCK SCK (MHz) ADC SAMPLING RATE ADC fS (kHz) DAC SAMPLING RATE DAC fS (kHz) REGISTER SETTINGS (1) MSR[2:0] 010 011 100 101 110 111 010 100 110 010 011 100 101 110 111 011 101 111 010 011 100 101 110 111 010 011 100 101 110 111 NPR[5:0] 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 00 0000 BIT CLOCK BCK (fS) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 24 (SCK/256) 16 (SCK/384) 6.144 12 (SCK/512) 8 (SCK/768) 6 (SCK/1024) 4 (SCK/1536) 32 (SCK/256) 8.192 16 (SCK/512) 8 (SCK/1024) 48 (SCK/256) 32 (SCK/384) 12.288 24 (SCK/512) 16 (SCK/768) 12 (SCK/1024) 8 (SCK/1536) 48 (SCK/384) 18.432 24 (SCK/768) 12 (SCK/1536) 22.05 (SCK/256) 14.7 (SCK/384) 5.6448 11.025 (SCK/512) 7.35 (SCK/768) 5.5125 (SCK/1024) 3.675 (SCK/1536) 44.1 (SCK/256) 29.4 (SCK/384) 11.2896 22.05 (SCK/512) 14.7 (SCK/768) 11.025 (SCK/1024) 7.35 (SCK/1536) (1) Other settings are reserved. Submit Documentation Feedback 47 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Table 13. System Clock Frequency for Application-Specific Clock SYSTEM CLOCK SCK (MHz) ADC SAMPLING RATE ADC fS (kHz) DAC SAMPLING RATE DAC fS (kHz) REGISTER SETTINGS MSR[2:0] 010 010 010 100 100 100 110 110 010 010 010 100 100 100 110 110 010 010 010 100 100 100 110 110 010 010 010 100 100 100 110 110 011 011 011 101 101 101 111 111 NPR[5:0] 00 0010 00 0001 10 0010 00 0010 00 0001 10 0010 00 0010 10 0010 01 0010 01 0001 11 0010 01 0010 01 0001 11 0010 01 0010 11 0010 00 0100 00 0011 10 0100 00 0100 00 0011 10 0100 00 0100 10 0100 01 0100 01 0011 11 0100 01 0100 01 0011 11 0100 01 0100 11 0100 00 0110 00 0101 10 0110 00 0110 00 0101 10 0110 00 0110 10 0110 BIT CLOCK BCK (fS) 70 76 70 70 76 70 70 70 70 76 70 70 76 70 70 70 62 68 62 62 68 62 62 62 62 68 62 62 68 62 62 62 66 72 66 66 72 66 66 66 48.214 (SCK/280) 44.407 (SCK/304) 32.142 (SCK/420) 13.5 24.107 (SCK/560) 22.203 (SCK/608) 16.071 (SCK/840) 12.053 (SCK/1120) 8.035 (SCK/1680) 48.214 (SCK/560) 44.407 (SCK/608) 32.142 (SCK/840) 27 24.107 (SCK/1120) 22.203 (SCK/1216) 16.071 (SCK/1680) 12.053 (SCK/2240) 8.035 (SCK/3360) 48.387 (SCK/248) 44.117 (SCK/272) 32.258 (SCK/372) 12 24.193 (SCK/496) 22.058 (SCK/544) 16.129 (SCK/744) 12.096 (SCK/992) 8.064 (SCK/1488) 48.387 (SCK/496) 44.117 (SCK/544) 32.258 (SCK/744) 24 24.193 (SCK/992) 22.058 (SCK/1088) 16.129 (SCK/1488) 12.096 (SCK/1984) 8.064 (SCK/2976) 48.484 (SCK/396) 44.444 (SCK/432) 32.323 (SCK/594) 19.2 24.242 (SCK/792) 22.222 (SCK/864) 16.161 (SCK/1188) 12.121 (SCK/1584) 8.080 (SCK/2376) 48 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Table 13. System Clock Frequency for Application-Specific Clock (continued) SYSTEM CLOCK SCK (MHz) ADC SAMPLING RATE ADC fS (kHz) DAC SAMPLING RATE DAC fS (kHz) REGISTER SETTINGS MSR[2:0] 011 011 011 101 101 101 111 111 010 010 010 100 100 100 110 110 010 010 010 100 100 100 110 110 011 011 011 101 101 101 111 111 011 011 011 101 101 101 111 111 NPR[5:0] 01 0110 01 0101 11 0110 01 0110 01 0101 11 0110 01 0110 11 0110 00 1000 00 0111 10 1000 00 1000 00 0111 10 1000 00 1000 10 1000 01 1000 01 0111 11 1000 01 1000 01 0111 11 1000 01 1000 11 1000 00 1010 00 1001 10 1010 00 1010 00 1001 10 1010 00 1010 10 1010 01 1010 01 1001 11 1010 01 1010 01 1001 11 1010 01 1010 11 1010 BIT CLOCK BCK (fS) 66 72 66 66 72 66 66 66 68 74 68 68 74 68 68 68 68 74 68 68 74 68 68 68 68 74 68 68 74 68 68 68 68 74 68 68 74 68 68 68 48.484 (SCK/792) 44.444 (SCK/864) 32.323 (SCK/1188) 38.4 24.242 (SCK/1584) 22.222 (SCK/1728) 16.161 (SCK/2376) 12.121 (SCK/3168) 8.080 (SCK/4752) 47.794 (SCK/272) 43.918 (SCK/296) 31.862 (SCK/408) 13 23.897 (SCK/544) 21.959 (SCK/592) 15.931 (SCK/816) 11.948 (SCK/1088) 7.965 (SCK/1632) 47.794 (SCK/544) 43.918 (SCK/592) 31.862 (SCK/816) 26 23.897 (SCK/1088) 21.959 (SCK/1184) 15.931 (SCK/1632) 11.948 (SCK/2176) 7.965 (SCK/3264) 48.235 (SCK/408) 44.324 (SCK/444) 32.156 (SCK/612) 19.68 24.117 (SCK/816) 22.162 (SCK/888) 16.078 (SCK/1224) 12.058 (SCK/1632) 8.039 (SCK/2448) 48.235 (SCK/816) 44.324 (SCK/888) 32.156 (SCK/1224) 39.36 24.117 (SCK/1632) 22.162 (SCK/1776) 16.078 (SCK/2448) 12.058 (SCK/3264) 8.039 (SCK/4896) Submit Documentation Feedback 49 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com MBST: BCK Output Configuration in Master Mode Default value: 0 This bit is used to control the BCK output configuration in master mode. In master mode, this bit sets the BCK output configuration to normal mode or burst mode. In normal mode (MBST = 0), the BCK clock runs continuously. In burst mode (MBST = 1), the BCK clock runs intermittently, and the number of clock cycles per LRCK period is reduced to equal the number of bits of audio data being transmitted. Operating in burst mode reduces the power consumption of VIO (I/O cell power supply). This is effective in master mode (register 69 MSTR = 1). MBST = 0 MBST = 1 Normal mode (default) Burst mode ATOD: ADC Digital Output to DAC Digital Input (Loopback) Default value: 0 The ADC digital output is internally connected to the DAC digital input by setting ATOD = 1. This setting can be used to debug ADC functions or to monitor a recording. ATOD= 0 ATOD= 1 Disabled (default) Enabled ZCRS: Zero-Cross for Digital Attenuation/Mute and Analog Gain Setting Default value: 0 This bit is used to enablethe zero-cross detector, which reduces zipper noise while the digital soft mute, digital attenuation analog gain setting, or analog volume setting is being changed. If no zero-cross data is input for a 512/fS period (10.6 ms at a 48-kHz sampling rate), then a time-out occurs and the PCM3793A/94A starts changing the attenuation, gain, or volume level. The zero-cross detector cannot be used with continuous-zero and dc data. ZCRS = 0 ZCRS = 1 Zero-cross disabled (default) Zero-cross enabled 50 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Register 87 B15 Register 87 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 AD2S B6 RSV B5 AIR1 B4 AIR0 B3 RSV B2 RSV B1 AIL1 B0 AIL0 IDX[6:0]: 101 0111b (57h): Register 87 AD2S: Differential Amplifier Selector (MUX3 and MUX4) Default value: 0 The PCM3793A/94A has stereo single-input amplifiers (PG1, PG2) and a monaural differential-input amplifier (D2S) which can output signals to the ADC. MUX3 and MUX4 can be selected as the monaural differential input by setting AD2S = 1. AD2S = 0 AD2S = 1 Single-input amplifiers (default) Differential-input amplifier AIL[1:0]: AIN1L, AIN2L, and AIN3L Selector (MUX1) Default value: 00 These bits are used to select one of the three analog inputs, AIN1L, AIN2L, or AIN3L. AIL[1:0] 00 01 10 11 AIN L-channel Select Disconnect (default) AIN1L AIN2L AIN3L AIR[1:0]: AIN1R, AIN2R, and AIN3R Selector (MUX2) Default value: 00 These bits are used to select one of the three stereo analog inputs, AIN1R, AIN2R, or AIN3R. AIR[1:0] 00 01 10 11 AIN R-channel Select Disconnect (default) AIN1R AIN2R AIN3R Submit Documentation Feedback 51 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Register 88 B15 Register 88 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 MXR2 B5 MXR1 B4 MXR0 B3 RSV B2 MXL2 B1 MXL1 B0 MXL0 IDX[6:0]: 101 1000b (58h): Register 88 MXR2: Mixing SW6 to MXR (R-Channel Mixing Amplifier) From L-Channel Analog Input Default value: 0 This bit is used to mix the analog source into MXR (R-ch mixing amplifier) from the L-ch analog input. MXR2 = 0 MXR2 = 1 Disable (default) Enable MXR1: Mixing SW4 to MXR (R-Channel Mixing Amplifier) From R-Channel Analog Input Default value: 0 This bit is used to mix the analog source into MXR (R-ch mixing amplifier) from the R-ch analog input. MXR1 = 0 MXR1 = 1 Disable (default) Enable MXR0: Mixing SW5 to MXR (R-Channel Mixing Amplifier) From R-Channel DAC Default value: 0 This bit is used to mix the analog source into MXR (R-ch mixing amplifier) from the R-ch DAC. MXR0 = 0 MXR0 = 1 Disable (default) Enable MXL2: Mixing SW3 to MXL (L-Channel Mixing Amplifier) From R-Channel Analog Input Default value: 0 This bit is used to mix the analog source into MXL (L-ch mixing amplifier) from the R-ch analog input. MXL2 = 0 MXL2 = 1 Disable (default) Enable MXL1: Mixing SW1 to MXL (L-Channel Mixing Amplifier) From L-Channel Analog Input Default value: 0 This bit is used to mix the analog source into MXL (L-ch mixing amplifier) from the L-ch analog input. MXL1 = 0 MXL1 = 1 Disable (default) Enable MXL0: Mixing SW2 to MXL (L-Channel Mixing Amplifier) From L-Channel DAC Default value: 0 This bit is used to mix the analog source into MXL (L-ch mixing amplifier) from the L-ch DAC. MXL0 = 0 MXL0 = 1 Disable (default) Enable 52 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Register 89 B15 Register 89 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 GMR2 B5 GMR1 B4 GMR0 B3 RSV B2 GML2 B1 GML1 B0 GML0 IDX[6:0]: 101 1001b (59h): Register 89 GMR[2:0]: Gain Level Control for PG6 (Gain Amplifier for Analog Input or R-Channel Bypass) GML[2:0]: Gain Level Control for PG5 (Gain Amplifier for Analog Input or L-Channel Bypass) Default value: 111 These bits are used for setting the gain level of the analog source to the mixing amplifier. It is recommended to set the gain level to avoid saturation in the analog mixer. GMR[2:0] GML[2:0] 000 001 010 011 100 101 110 111 Gain Level Control for PG6 Gain Level Control for PG5 –21 dB –18 dB –15 dB –12 dB –9 dB –6 dB –3 dB 0 dB (default) Register 90 B15 Register 90 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 RSV B5 RSV B4 RSV B3 RSV B2 RSV B1 G20R B0 G20L IDX[6:0]: 1011010b (5Ah): Register 90 G20R: 20-dB Boost for PG2 (Gain Amplifier for AIN1R, AIN2R, and AIN3R) Default value: 0 This bit is used to boost the microphone signal when the analog input is small. G20R = 0 G20R = 1 0 dB (default) 20-dB boost G20L: 20-dB Boost for PG1 (Gain Amplifier for AIN1L, AIN2L, and AIN3L) Default value: 0 This bit is used to boost the microphone signal when the analog input is small. G20L = 0 G20L = 1 0 dB (default) 20-dB boost Submit Documentation Feedback 53 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Register 92 B15 Register 92 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 LPAE B6 RSV B5 RSV B4 LGA4 B3 LGA3 B2 LGA2 B1 LGA1 B0 LGA0 IDX[6:0]: 101 1100b (5Ch): Register 92 LPAE: Gain Adjustment for Bass Boost Gain Control Default value: 0 A gain setting for bass boost may cause digital data may saturation, depending on the input data level. Where this could occur, LPAE can be used to set the same attenuation level as the bass boost gain level for the digital input data. LPAE = 0 LPAE = 1 Disable (default) Enable LGA[4:0]: Bass Boost Gain Control Default value: 0 0000 These bits are used to set the bass boost gain level for the digital data. The detailed characteristics are shown in the Typical Performance Curves. LGA[4:0] 0 0000 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 TONE CONTROL GAIN (BASS) 0 dB (default) 12 dB 11 dB 10 dB 9 dB 8 dB 7 dB 6 dB 5 dB 4 dB 3 dB 2 dB 1 dB LGA[4:0] 0 1111 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 TONE CONTROL GAIN (BASS) 0 dB –1 dB –2 dB –3 dB –4 dB –5 dB –6 dB –7 dB –8 dB –9 dB –10 dB –11 dB –12 dB 54 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Register 93 B15 Register 93 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 RSV B5 RSV B4 MGA4 B3 MGA3 B2 MGA2 B1 MGA1 B0 MGA0 IDX[6:0]: 101 1101b (5Dh): Register 93 MGA[4:0]: Middle Boost Gain Control Default value: 0 0000 These bits are used to set the midrange boost gain level for the digital data. The detailed characteristics are shown in the Typical Performance Curves. MGA[4:0] 0 0000 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 TONE CONTROL GAIN (MIDRANGE) 0 dB (default) 12 dB 11 dB 10 dB 9 dB 8 dB 7 dB 6 dB 5 dB 4 dB 3 dB 2 dB 1 dB MGA[4:0] 0 1111 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 TONE CONTROL GAIN (MIDRANGE) 0 dB –1 dB –2 dB –3 dB –4 dB –5 dB –6 dB –7 dB –8 dB –9 dB –10 dB –11 dB –12 dB Register 94 B15 Register 94 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 RSV B5 RSV B4 HGA4 B3 HGA3 B2 HGA2 B1 HGA1 B0 HGA0 IDX[6:0]: 101 1110b (5Eh): Register 94 HGA[4:0]: Treble Boost Gain Control (fC = 5 kHz) Default value: 0 0000 These bits are used to set the treble boost gain level for the digital data. The detailed characteristics are shown in the Typical Performance Curves. HGA[4:0] 0 0000 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 TONE CONTROL GAIN (TREBLE) 0 dB (default) 12 dB 11 dB 10 dB 9 dB 8 dB 7 dB 6 dB 5 dB 4 dB 3 dB 2 dB 1 dB HGA[4:0] 0 1111 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 TONE CONTROL GAIN (TREBLE) 0 dB –1 dB –2 dB –3 dB –4 dB –5 dB –6 dB –7 dB –8 dB –9 dB –10 dB –11 dB –12 dB Submit Documentation Feedback 55 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Register 95 B15 Register 95 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 SDAS B6 3DEN B5 RSV B4 3FL0 B3 3DP3 B2 3DP2 B1 3DP1 B0 3DP0 IDX[6:0]: 101 1111b (5Fh): Register 95 SDAS: Source Select for Sound Effect (Tone Control, 3-D Sound, Notch Filter, Mono Mix) Default value: 0 The PCM3793A/94A includes sound effect circuits (tone control, 3-D sound, notch filter, mono mix) which can be used to filter either the digital input to the DAC or the digital output from the ADC. This bit selects the signal source of the sound effect circuit. SDAS = 0 SDAS = 1 DAC digital input (default) ADC digital output 3DEN: 3-D Sound Effect Enable Default value: 0 This bit is used for enabling the 3-D sound effect filter. This filter has two independently controlled parameters. 3DEN = 0 3DEN = 1 Disable (default) Enable 3FL0: Filter Selection for 3-D Sound Default value: 0 This bit is used for selecting from two types of filter, narrow and wide. These filters have a different 3-D performance effect. 3FL0 = 0 3FL0 = 1 Narrow (default) Wide 3DP[3:0]: Efficiency for 3-D Sound Effects Default value: 0000 These bits are used for adjusting the 3-D sound efficiency. Higher percentages have greater efficiency. 3DP[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 : 1111 3D Sound Effect Efficiency 0% (default) 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% Reserved : Reserved 56 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Register 96 B15 Register 96 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 NEN2 B6 NEN1 B5 NUP2 B4 NUP1 B3 RSV B2 RSV B1 RSV B0 MXEN IDX[6:0]: 110 0000b (60h): Register 96 NEN2: Second-Stage Notch Filter Enable Default value: 0 PCM3793A/94A has two notch filters with characteristics that can be set separately. This bit is used to enable the second stage. NEN2 = 0 NEN2 = 1 Disable (default) Enable NEN1: First-Stage Notch Filter Enable Default value: 0 PCM3793A/94A has two notch filters with characteristics that can be set separately. This bit is used to enable the first stage. NEN1 = 0 NEN1 = 1 Disable (default) Enable NUP2: Second-Stage Notch Filter Coefficients Update Default value: 0 This bit is used to update the coefficients for the second-stage notch filter. The coefficients set by registers 101, 102, 103, and 104 are updated when NUP2 = 1. NUP2 = 0 NUP2 = 1 No Update (default) Update (set to 0 automatically after set to 1) NUP1: First-Stage Notch Filter Coefficients Update Default value: 0 This bit is used to update the coefficients for the first-stage notch filter. The coefficients set by registers 97, 98, 99, and 100 are updated when NUP1 = 1. NUP1 = 0 NUP1 = 1 No Update (default) Update (set to 0 automatically after being set to 1) MXEN: Digital Monaural Mixing Default value: 0 This bit is used to enable or disable monaural mixing in the section that combines L-ch data and R-ch data. MXEN = 0 MXEN = 1 Stereo (default) Monaural Mixing Submit Documentation Feedback 57 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Registers 97–100 B15 Register 97 Register 98 Register 99 Register 100 0 0 0 0 B14 IDX6 IDX6 IDX6 IDX6 B13 IDX5 IDX5 IDX5 IDX5 B12 IDX4 IDX4 IDX4 IDX4 B11 IDX3 IDX3 IDX3 IDX3 B10 IDX2 IDX2 IDX2 IDX2 B9 IDX1 IDX1 IDX1 IDX1 B8 IDX0 IDX0 IDX0 IDX0 B7 F107 F115 F207 F215 B6 F106 F114 F206 F214 B5 F105 F113 F205 F213 B4 F104 F112 F204 F212 B3 F103 F111 F203 F211 B2 F102 F110 F202 F210 B1 F101 F109 F201 F209 B0 F100 F108 F200 F208 IDX[6:0]: 110 0001b (61h): Register 97 IDX[6:0]: 110 0010b (62h): Register 98 IDX[6:0]: 110 0011b (63h): Register 99 IDX[6:0]: 110 0100b (64h): Register 100 F[107:100]: Lower 8 Bits of Coefficient a1 for First-Stage Notch Filter F[115:108]: Upper 8 Bits of Coefficient a1 for First-Stage Notch Filter F[207:200]: Lower 8 Bits of Coefficient a2 for First-Stage Notch Filter F[215:208]: Upper 8 Bits of Coefficient a2 for First-Stage Notch Filter Default value: 0000 0000 These bits are used to change the characteristics of the first-stage notch filter. See Figure 39 for details. 58 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 Registers 101–104 B15 Register 101 Register 102 Register 103 Register 104 0 0 0 0 B14 IDX6 IDX6 IDX6 IDX6 B13 IDX5 IDX5 IDX5 IDX5 B12 IDX4 IDX4 IDX4 IDX4 B11 IDX3 IDX3 IDX3 IDX3 B10 IDX2 IDX2 IDX2 IDX2 B9 IDX1 IDX1 IDX1 IDX1 B8 IDX0 IDX0 IDX0 IDX0 B7 S107 S115 S207 S215 B6 S106 S114 S206 S214 B5 S105 S113 S205 S213 B4 S104 S112 S204 S212 B3 S103 S111 S203 S211 B2 S102 S110 S202 S210 B1 S101 S109 S201 S209 B0 S100 S108 S200 S208 IDX[6:0]: 110 0101b (65h): Register 101 IDX[6:0]: 110 0110b (66h): Register 102 IDX[6:0]: 110 0111b (67h): Register 103 IDX[6:0]: 110 1000b (68h): Register 104 S[107:100]: Lower 8 Bits of Coefficient a1 for Second-Stage Notch Filter S[115:108]: Upper 8 Bits of Coefficient a1 for Second-Stage Notch Filter S[207:200]: Lower 8 Bits of Coefficient a2 for Second-Stage Notch Filter S[215:208]: Upper 8 Bits of Coefficient a2 for Second-Stage Notch Filter Default value: 0000 0000 These bits are used to change the characteristics of the second-stage notch filter. See Figure 39 for details. The PCM3793A/94A provides two notch filters for the digital input to the DAC or the digital output from the ADC. The optional filter characteristics of each filter are programmable. The characteristics are given by calculating the coefficients for three parameters, sampling frequency, center frequency, and bandwidth, as shown in Figure 39. All coefficients must be written as 2s-complement binary data into registers 97, 98, 99, 100, 101, 102, 103, and 104. fS: Sampling Frequency [Hz] fC: Center Frequency [Hz] fb: Band Width [Hz] fC 0 dB –3 dB fb a1 = –(1 + a2) cos ç ç æ 2pfC ö ÷ ÷ è fS ø (Equation 1) 1 – tan ç ç a2 = æ 2pfb/fS ö ÷ ÷ è2ø æ 2pfb/fS ö ÷ 1 + tan ç ç2÷ è ø (Equation 2) Frequency – Hz M0058-01 Figure 39. Parameter Settings for Notch Filter The coefficients are calculated using Equation 1 and Equation 2 in Figure 39. An example follows: fS = 16 kHz, fC = 0.5 kHz, fb = 0.2 kHz a2 = 0.924390492 → Decimal to Hex → 3B29h a1 = –1.887413868 → Decimal to Hex → 8735h a2: F[215:208] = 3Bh, F[207:200] = 29h a1: F[115:108] = 87h, F[107:100] = 35h Amplitude – dB Submit Documentation Feedback 59 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Register 125 B15 Register 125 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 RSV B6 PTM1 B5 PTM0 B4 RES4 B3 RES3 B2 RES2 B1 RES1 B0 RES0 IDX[6:0]: 111 1101b (7Dh): Register 125 PTM[1:0]: Power-Up/Down Time Control Default value: 00 Table 14. Power Up/Down Time Control VCOM CAPACITOR [µF] RES[4:0] 1 1110 10 1 1100 1 1000 1 0000 1 1110 4.7 1 1100 1 1000 1 0000 1 1110 2.2 1 1100 1 1000 1 0000 1 1110 1 1 1100 1 1000 1 0000 PTM[1:0] 00 11 Do not set. Do not set. 01 00 11 Do not set. 10 01 00 11 Do not set. 10 01 00 POWER-UP TIME [ms] 450 900 – – 250 450 900 – 100 250 450 900 – 100 250 450 POWER-DOWN TIME [ms] 750 1500 – – 400 750 1500 – 300 400 750 1500 – 300 400 750 Default NOTE RES[4:0]: Resistor Value Control Default value: 1 1100 These bits are used to optimize audible pop noise and ramp-up time for the headphone output when powering the device on/off. Table 15. Resistor Value Control RES [4:0] 1 0000 1 1000 1 1100 1 1110 Others VCOM RESISTOR VALUE 60 kΩ 24 kΩ 12 kΩ 6 kΩ Reserved 60 Submit Documentation Feedback www.ti.com PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 CONNECTION DIAGRAMS To Regulator SCKI (7) BCK (1) LRCK (32) DIN (2) DOUT (3) MS/ADR (29) MD/SDA (30) MC/SCL (31) Low or High MODE (28) (12) VPA (13) PGND C11 (20) VCC (19) AGND C10 (4) VIO (5) VDD (6) DGND C9 C8 PCM3793A/94A R3 R1 R2 (8) HDTI MICB (21) (17) HPOL/LOL C1 C2 C3 C4 C5 C6 AIN1L (27) AIN1R (26) AIN2L (25) AIN2R (24) AIN3L (23) AIN3R (22) VCOM (18) C7 (15) SPOLP (14) SPOLN (11) SPORP (10) SPORN S0220-02 C12 (16) HPOR/LOR C13 (9) HPCOM/MONO C14 R4 Stereo Headphone Monaural Line Output Figure 40. Connection Diagram Table 16. Recommended External Parts C1–C6 C7 C8 C9, C10 C11 B1 1 µF 4.7 µF 0.1 µF 1 µF–4.7 µF 4.7 µF–10 µF C12, C13 C14 R1, R2 R3 R4 L1 10 µF–220 µF 1 µF–10 µF 2.2 kΩ 33 kΩ 10 kΩ SPOLP/ SPORP SPOLP/ SPORP C15 C17 SPOLN/ SPORN L2 SPOLN/ SPORN B2 C16 C18 S0221-01 NOTE: C15, C16 = 1 nF; C17, C18 = 1 µF; B1, B2: NEC/Tokin N2012ZPS121; L1, L2 = 22 µH to 33 µH Figure 41. Filter Consideration for Speaker Output Submit Documentation Feedback 61 PCM3793A PCM3794A SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com Conventional M ode VCC Capless Mode VCC HDTI HPOL HPOR + + HP Jack HDTI HPOL HPOR PGND HP Jack PGND HPCOM HPCOM S0222-01 Figure 42. Connection for Headphone Output and Insertion Detection HPOL + HPOL CL 16 W + CL 4.7 W 16 W 16 W HPOR HPOR + CR + CR 4.7 W 16 W CL, CR – mF 10 47 100 220 fC – Hz 995 212 100 45 CL, CR – mF 10 47 100 220 fC – Hz 770 163 77 35 S0223-01 Figure 43. High-Pass Filter for Headphone Output 62 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 18-May-2007 PACKAGING INFORMATION Orderable Device PCM3793ARHBR PCM3793ARHBRG4 PCM3793ARHBT PCM3793ARHBTG4 PCM3794ARHBR PCM3794ARHBT (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type QFN QFN QFN QFN QFN QFN Package Drawing RHB RHB RHB RHB RHB RHB Pins Package Eco Plan (2) Qty 32 32 32 32 32 32 1 1 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 3000 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Device Package Pins Site Reel Diameter (mm) 330 Reel Width (mm) 12 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8 W Pin1 (mm) Quadrant 12 PKGORN T2TR-MS P PKGORN T2TR-MS P PKGORN T2TR-MS P PKGORN T2TR-MS P PCM3793ARHBR RHB 32 MLA 5.3 5.3 1.5 PCM3793ARHBT RHB 32 MLA 180 12 5.3 5.3 1.5 8 12 PCM3794ARHBR RHB 32 MLA 330 12 5.3 5.3 1.5 8 12 PCM3794ARHBT RHB 32 MLA 180 12 5.3 5.3 1.5 8 12 TAPE AND REEL BOX INFORMATION Device PCM3793ARHBR PCM3793ARHBT PCM3794ARHBR PCM3794ARHBT Package RHB RHB RHB RHB Pins 32 32 32 32 Site MLA MLA MLA MLA Length (mm) 346.0 190.0 346.0 190.0 Width (mm) 346.0 212.7 346.0 212.7 Height (mm) 29.0 31.75 29.0 31.75 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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