PCM5102APWR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 PCM510xA 2.1 VRMS, 112/106/100 dB Audio Stereo DAC with PLL and 32-bit, 384 kHz PCM Interface 1 Features • • 1 • • • • • • • • • • • Ultra Low Out-of-Band Noise Integrated High-Performance Audio PLL with BCK Reference to Generate SCK Internally Direct Line Level 2.1-VRMS Output No DC Blocking Capacitors Required Line Level Output Down to 1KΩ Intelligent Muting System; Soft Up or Down Ramp and Analog Mute For 120-dB Mute SNR Accepts 16-, 24-, and 32-Bit Audio Data PCM Data Formats: I2S, Left-Justified Automatic Power-Save Mode When LRCK And BCK Are Deactivated 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs Simple Configuration Using Hardware Pins Single-Supply Operation: 14 – 3.3 V Analog, 1.8 V or 3.3 V Digital Qualified in Accordance with AEC-Q100 2 Applications • • • • Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with singlesupply line drivers. The integrated line driver surpasses all other chargepump based line drivers by supporting loads down to 1 kΩ per pin. The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI. Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for popfree performance. Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz). Table 1. Device Information(1) A/V Receivers, DVD, BD Players Automotive Infotainment and Telematics HDTV Receivers Aftermarket Automotive Amplifiers PART NUMBER PACKAGE BODY SIZE (NOM) PCM5102A PCM5101A TSSOP (20) 5.50 mm × 4.40 mm PCM5100A 3 Description The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digitalto-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segmentDAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified System Diagram 2 I S PCM1863/5 BCK LRCK IN AUX PCM510xA PLL 2ch Single Ended Charge Pump IN MIC 2ch Single Ended Analog Sensor - Light Intensity - Ultrasonic - Battery Level BT Module MSP430 OUT LINE WiLAN chip 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified System Diagram .................................. Revision History..................................................... Device Comparison ............................................... Pin Configuration and Functions ......................... Specifications......................................................... 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 9 1 1 1 1 2 4 5 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings ............................................................ 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Timing Requirements .............................................. 11 Timing Requirements, XSMT .................................. 11 Typical Characteristics ............................................ 12 Detailed Description ............................................ 14 9.1 Overview ................................................................. 14 9.2 Functional Block Diagram ....................................... 14 9.3 Feature Description................................................. 14 9.4 Device Functional Modes........................................ 25 10 Applications and Implementation...................... 26 10.1 Application Information.......................................... 26 11 Power Supply Recommendations ..................... 28 11.1 Power Supply Distribution and Requirements ...... 11.2 Recommended Powerdown Sequence................. 11.3 External Power Sense Undervoltage Protection Mode ........................................................................ 11.4 Power-On Reset Function..................................... 11.5 PCM510xA Power Modes ..................................... 28 28 30 32 33 12 Layout................................................................... 34 12.1 Layout Guidelines ................................................. 34 13 Device and Documentation Support ................. 35 13.1 13.2 13.3 13.4 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ 35 35 35 35 14 Mechanical, Packaging, and Orderable Information ........................................................... 35 14.1 Mechanical Data ................................................... 35 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2015) to Revision C Page • Changed the device number from "PCM510x" to "PCM510xA" in the Simplified System Diagram ..................................... 1 • Changed typical performance table to reflect part differences accurately ............................................................................ 4 • Changed "Storage temperatures, Tstg" to "Operating junction temperature range at –40°C to 130°C" ................................. 6 • Changed "Storage temperature (Q1 devices) –40°C to 125°C" to "Storage temperatures, Tstg –65°C to 150°C" ................ 6 • Changed the stereo line output load resistance MIN value in the Recommended Operating Conditions from "2 kΩ" to "1 kΩ".................................................................................................................................................................................. 6 • Changed the operating junction temperature range in the Recommended Operating Conditions from "MIN = –25°C MAX = 85°C" to "MIN = –40°C MAX = 130°C"....................................................................................................................... 6 • Added "Q1 Automotive grade devices..." and "Consumer grade (non-Q1) devices..." to the condition statement in the Electrical Characteristics .................................................................................................................................................. 7 • Added "Q1 Automotive grade devices..." and "Consumer grade (non-Q1) devices..." to the condition statement in the Typical Characteristics graphs section. .......................................................................................................................... 12 • Changed "MCK" to "SCK" at the PLL Clock in the Functional Block Diagram..................................................................... 14 • Added label "Mute Circuit" and ground symbols to pins DEMP and FMT in Figure 33 ...................................................... 26 Changes from Revision A (September 2012) to Revision B Page • Added ESD Rating table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information.............................................................................................................................................................................. 1 • Added items to show 1.8 V DVDD capability ......................................................................................................................... 1 • Changed the Features list. ..................................................................................................................................................... 1 • Changed "Operating temperature range " to "Operating junction temperature range" .......................................................... 6 • Deleted redundant PLL specification in the Recommended Operating Conditions .............................................................. 6 • Deleted "Intelligent clock error..." and "...for pop-free performance."................................................................................... 14 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 • Clarified clock generation explanation.................................................................................................................................. 24 • Clarified external SCK discussion. ....................................................................................................................................... 25 • Deleted "The PCM510xA disables the internal PLL when an external SCK is supplied." ................................................... 25 Changes from Original (May 2012) to Revision A Page • Changed layout of first two pages .......................................................................................................................................... 1 • Changed "VOUT = –1 dB" to "THD+N at –1 dBFS" in in the Dymamic Performance section of the Electrical Characteristics ........................................................................................................................................................................ 8 • Changed reference to correct footnote................................................................................................................................. 10 • Changed tSCKH and tSCKL values to 9ns................................................................................................................................. 11 • Removed 48kHz sample rate with PLL-generated clock...................................................................................................... 25 Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 3 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 6 Device Comparison Differences Between PCM510xA Devices PART NUMBER DYNAMIC RANGE SNR THD PCM5102A 112dB 112dB –93 dB PCM5101A 106 dB 106 dB –92 dB PCM5100A 100 dB 100 dB –90 dB Typical Performance (3.3 V Power Supply) PARAMETER SNR 112 / 106 / 100 dB Dynamic range 112 /106 / 100 dB THD+N at –1 dBFS –93/ –92 / –90 dB Full-scale single-ended output 2.1 VRMS (GND center) Normal 8× oversampling digital filter latency 20tS Low latency 8× oversampling digital filter latency 3.5tS Sampling frequency System clock multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072 4 PCM5102 / PCM5101 / PCM5100 Submit Documentation Feedback 8 kHz to 384 kHz Up to 50 MHz Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 7 Pin Configuration and Functions PW 20-Pin Package (Top View) Pin Functions PIN TYPE DESCRIPTION NAME NO. AGND 9 — Analog ground AVDD 8 P Analog power supply, 3.3 V BCK 13 I Audio data bit clock input (1) CAPM 4 O Charge pump flying capacitor terminal for negative rail CAPP 2 O Charge pump flying capacitor terminal for positive rail CPGND 3 — Charge pump ground CPVDD 1 P Charge pump power supply, 3.3 V DEMP 10 I De-emphasis control for 44.1-kHz sampling rate (1): Off (Low) / On (High) DGND 19 — DIN 14 I Audio data input (1) DVDD 20 P Digital power supply, 1.8 V or 3.3 V FLT 11 I Filter select : Normal latency (Low) / Low latency (High) FMT 16 I Audio format selection : I2S (Low) / Left-justified (High) LDOO 18 P Internal logic supply rail terminal for decoupling, or external 1.8 V supply terminal LRCK 15 I Audio data word clock input (1) OUTL 6 O Analog output from DAC left channel OUTR 7 O Analog output from DAC right channel SCK 12 I System clock input (1) VNEG 5 O Negative charge pump rail terminal for decoupling, –3.3 V XSMT 17 I Soft mute control (1): Soft mute (Low) / soft un-mute (High) (1) Digital ground Failsafe LVCMOS Schmitt trigger input Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 5 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Supply voltage Digital input voltage MIN MAX AVDD, CPVDD, DVDD –0.3 3.9 LDO with DVDD at 1.8 V –0.3 2.25 DVDD at 1.8 V –0.3 2.25 DVDD at 3.3 V –0.3 3.9 UNIT V Analog input voltage –0.3 3.9 Operating junction temperature range –40 130 °C Storage temperature, Tstg –65 150 °C 8.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±750 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions MIN NOM MAX AVDD Analog power supply voltage range Referenced to AGND (1) VCOM mode 3 3.3 3.46 VREF mode 3.2 3.3 3.46 DVDD Digital power supply voltage range Referenced to DGND (1) 1.8 V DVDD 1.65 1.8 1.95 3.3 V DVDD 3.1 3.3 3.46 CPVDD Charge pump supply voltage range Referenced to CPGND (1) 3.1 3.3 3.46 MCLK Master clock frequency LOL, LOR Stereo line output load resistance CLOUT Digital output load capacitance TJ Operating junction temperature range (1) 50 1 10 V V V MHz kΩ 10 –40 UNIT pF 130 °C All grounds on board are tied together; they must not differ in voltage by more than 0.2 V max, for any combination of ground signals. 8.4 Thermal Information THERMAL METRIC (1) PW 20 PINS RθJA Junction-to-ambient thermal resistance 91.2 RθJC(top) Junction-to-case (top) thermal resistance 25.3 RθJB Junction-to-board thermal resistance 42 ψJT Junction-to-top characterization parameter 1 ψJB Junction-to-board characterization parameter 41.5 RθJC(bot) Junction-to-case (bottom) thermal resistance — (1) 6 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 8.5 Electrical Characteristics Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS Resolution MIN TYP MAX 16 24 32 24 UNIT Bits Data Format (PCM Mode) Audio data bit length 16 fS (1) Sampling frequency 8 fSCK System clock frequency Clock multiples: 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072 32 Bits 384 kHz 50 MHz Digital Input/Output for non-Q1 Consumer Grade Devices Logic family: 3.3 V LVCMOS compatible VIH VIL IIH IIL VOH VOL 0.7×DVDD Input logic level Input logic current Output logic level 0.3×DVDD VIN = VDD 10 VIN = 0 V –10 IOH = –4 mA 0.8×DVDD IOL = 4 mA 0.22×DVDD V µA V Logic family 1.8 V LVCMOS compatible VIH VIL IIH IIL VOH VOL 0.7×DVDD Input logic level Input logic current Output logic level 0.3×DVDD VIN = VDD 10 VIN = 0 V –10 IOH = –2 mA 0.8×DVDD IOL = 2 mA 0.22×DVDD V µA V Digital Input/Output for Q1 Automotive Grade Devices Logic family: 3.3 V LVCMOS compatible VIH VIL IIH IIL VOH VOL 0.7×DVDD Input logic level Input logic current Output logic level 0.3×DVDD VIN = VDD 10 VIN = 0 V –10 IOH = –4 mA 0.8×DVDD IOL = 4 mA 0.22×DVDD V µA V Logic family 1.8 V LVCMOS compatible VIH VIL IIH IIL VOH VOL (1) 0.7×DVDD Input logic level Input logic current Output logic level 0.3×DVDD VIN = VDD 10 VIN = 0 V –10 IOH = –2 mA IOL = 2 mA 0.8×DVDD 0.3×DVDD V µA V One sample time is defined as the reciprocal of the sampling frequency. 1tS = 1/fS Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 7 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PCM5102A –93 –83 dB PCM5101A –92 –82 PCM5100A –90 –80 PCM5102A –93 PCM5101A –92 Dynamic Performance (PCM Mode) (2) (3) fS = 48 kHz THD+N at –1 dBFS (3) fS = 96 kHz and 192 kHz PCM5100A PCM5102A Dynamic range (3) EIAJ, A-weighted, fS = 48 PCM5101A kHz PCM5100A –90 106 112 100 106 95 100 PCM5102A 112 EIAJ, A-weighted, fS = 96 PCM5101A kHz and 192 kHz PCM5100A 106 100 PCM5102A Signal-to-noise ratio (3) 112 EIAJ, A-weighted, fS = 48 PCM5101A kHz PCM5100A 106 100 PCM5102A 112 EIAJ, A-weighted, fS = 96 PCM5101A kHz and 192 kHz PCM5100A Signal to noise ratio with analog mute (3) (4) EIAJ, A-weighted, fS = 48 kHz fS = 96 kHz fS = 192 kHz (2) (3) (4) 8 100 113 EIAJ, A-weighted, fS = 96 kHz and 192 kHz fS = 48 kHz Channel separation 106 123 123 PCM5102A 100 109 PCM5101A 95 103 PCM5100A 90 97 PCM5102A 109 PCM5101A 103 PCM5100A 97 PCM5102A 109 PCM5101A 103 PCM5100A 97 Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF; Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF; A-weighted signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF; A-weighted channel separation: 20-Hz HPF, 20-kHz AES17 LPF. Analog performance specifications are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode. Output load is 10 kΩ, with 470-Ω output resistor and a 2.2-nF shunt capacitor (see recommended output filter). Assert XSMT or both L-ch and R-ch PCM data are Bipolar Zero. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Output Output voltage 2.1 VRMS Gain error –6 ±2 6 % of FSR Gain error on Q1 Automotive Grade Devices –7 ±2 7 % of FSR Gain mismatch, channel-to-channel –6 ±2 6 % of FSR Gain mismatch, channel-to-channel on Q1 Devices –6 ±2 6 % of FSR PCM5100/1 bipolar zero error At bipolar zero –5 ±1 5 mV PCM5102 Bipolar zero error At bipolar zero –2 ±1 2 mV Load impedance 1 kΩ Filter Characteristics–1: Normal Pass band 0.45fS Stop band 0.55fS Stop band attenuation –60 Pass-band ripple ±0.02 Delay time 20tS dB s Filter Characteristics–2: Low Latency Pass band 0.47fS Stop band 0.55fS Stop band attenuation –52 Pass-band ripple ±0.0001 Delay time 3.5tS dB s Power Supply Requirements DVDD Digital supply voltage Target DVDD = 1.8 V 1.65 1.8 1.95 DVDD Digital supply voltage Target DVDD = 3.3 V 3 3.3 3.6 AVDD Analog supply voltage 3 3.3 3.6 CPVDD Charge-pump supply voltage 3 3.3 3.6 IDD DVDD supply current at 1.8 V (5) IDD IDD IDD DVDD supply current at 1.8 V (6) DVDD supply current at 1.8 V (7) DVDD supply current at 3.3 V (5) IDD DVDD supply current at 3.3 V (6) IDD DVDD supply current at 3.3 V (7) IDD (5) (6) (7) AVDD / CPVDD supply current (5) fS = 48 kHz 7 fS = 96 kHz 8 fS = 192 kHz 9 fS = 48 kHz 7 fS = 96 kHz 8 fS = 192 kHz 9 Standby 7 fS = 96 kHz 8 fS = 192 kHz 9 fS = 48 kHz 8 fS = 96 kHz 9 VDC mA mA 0.3 fS = 48 kHz VDC mA 12 mA 13 mA fS = 192 kHz 10 Standby 0.5 0.8 fS = 48 kHz 11 16 fS = 96 kHz 11 fS = 192 kHz 11 mA mA Input is Bipolar Zero data. Input is 1 kHz –1 dBFS data. Power Down Mode Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 9 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER IDD IDD AVDD / CPVDD supply current (6) AVDD / CPVDD supply current (7) Power dissipation, DVDD = 1.8 V (5) Power dissipation, DVDD = 1.8 V (6) Power dissipation, DVDD = 1.8 V (7) Power dissipation, DVDD = 3.3 V (5) Power dissipation, DVDD = 3.3 V (6) Power dissipation, DVDD = 3.3 V (7) 10 Submit Documentation Feedback TYP MAX fS = 48 kHz TEST CONDITIONS 22 32 fS = 96 kHz 22 fS = 192 kHz 22 fS = n/a 0.2 0.4 fS = 48 kHz 49 185 fS = 96 kHz 51 fS = 192 kHz 53 fS = 48 kHz 85 fS = 96 kHz 87 fS = 192 kHz 89 fS = n/a (Power Down Mode) MIN 60 fS = 96 kHz 63 fS = 192 kHz 66 fS = 48 kHz 99 fS = 96 kHz 102 fS = 192 kHz 106 fS = n/a (Power Down Mode) mA mA mW 187 mW 1 fS = 48 kHz UNIT mW 92.4 mW 148.5 2 mW 4 mW Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 8.6 Timing Requirements Figure 1 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise. MIN tSCY System clock pulse cycle time tSCKH System clock pulse width, High tSCKL System clock pulse width, Low TYP 20 DVDD = 1.8 V 8 DVDD = 3.3 V 9 DVDD = 1.8 V 8 DVDD = 3.3 V 9 MAX UNIT 1000 ns ns ns tSCKH "H" 0.7*DVDD System Clock (SCK) 0.3*DVDD "L" tS CK L tSCY Figure 1. Timing Requirements for SCK Input 8.7 Timing Requirements, XSMT MIN TYP MAX UNIT tr Rise time 20 ns tf Fall time 20 ns 0.9 * DVDD XSMT 0.1 * DVDD tr