PGA2311PAG4

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software PGA2311 SBOS218D – DECEMBER 2001 – REVISED MAY 2016 PGA2311 Stereo Audio Volume Control 1 Features 3 Description • The PGA2311 device is a high-performance, stereo audio volume control designed for professional and high-end consumer audio systems. The PGA2311 uses an internal high-performance operational amplifier to yield low noise and distortion. The PGA2311 also provides the capability to drive 660-Ω loads directly without buffering. The 3-wire serial control interface allows for connection to a wide variety of host controllers, in addition to support for daisy-chaining of multiple PGA2311 devices. 1 • • • • • • • Digitally-Controlled Analog Volume Control: – Two Independent Audio Channels – Serial Control Interface – Zero Crossing Detection – Mute Function Wide Gain and Attenuation Range: +31.5 dB to −95.5 dB with 0.5-dB Steps Low Noise and Distortion: – 120-dB Dynamic Range – 0.0004% THD+N at 1 kHz (U-Grade) – 0.0002% THD+N at 1 kHz (A-Grade) Noise-Free Level Transitions Low Interchannel Crosstalk: −130 dBFS Power Supplies: ±5-V Analog, +5-V Digital Available in PDIP-16 and SOIC-16 Packages Pin- and Software-Compatible With the Crystal CS3310 Device Information(1) PART NUMBER PGA2311 PACKAGE BODY SIZE (NOM) SOIC (16) 7.5 mm × 10.30 mm PDIP (16) 6.35 mm × 19.30 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • • • • • Audio Amplifiers Mixing Consoles Multi-Track Recorders Broadcast Studio Equipment Musical Instruments Effects Processors A/V Receivers Car Audio Systems Stereo Audio Volume Control Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. PGA2311 SBOS218D – DECEMBER 2001 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 12 7.5 Programming .......................................................... 12 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application ................................................. 13 9 Power Supply Recommendations...................... 14 10 Layout................................................................... 15 10.1 Layout Guidelines ................................................. 15 10.2 Layout Example .................................................... 15 11 Device and Documentation Support ................. 16 11.1 11.2 11.3 11.4 11.5 Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 16 16 16 16 16 12 Mechanical, Packaging, and Orderable Information ........................................................... 16 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (May 2016) to Revision D Page • Changed the values of Voltage range, PGA2311PA, UA (A−grade) To: (VA-) = + 1.25 V, and (VA-) = –1.25 V in the Electrical Characteristics table ............................................................................................................................................... 5 • Chnaged the Quiescent current Test Conditions To: VA = +5 V, and VA = –5 V in the Electrical Characteristics table ....... 6 Changes from Revision B (January 2016) to Revision C Page • Changed package family terms in second to last Features bullet ......................................................................................... 1 • Changed description of pin 7 in Pin Functions table ............................................................................................................. 3 • Deleted lead temperature and package temperature rows from Absolute Maximum Ratings table ...................................... 4 Changes from Revision A (June 2002) to Revision B • 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 PGA2311 www.ti.com SBOS218D – DECEMBER 2001 – REVISED MAY 2016 5 Pin Configuration and Functions N or DW Package 16-Pin PDIP or SOIC Top View Pin Functions PIN I/O DESCRIPTION NO. NAME 1 ZCEN I Zero-crossing enable input (active high) 2 CS I Chip-select input (active low) 3 SDI I Serial data input 4 VD+ I Digital power supply, +5 V 5 DGND — 6 SCLK I Serial clock input 7 SDO O Serial data output 8 MUTE I Mute control input (active low) 9 VINR I Analog input, right channel 10 AGNDR — Analog ground, right channel 11 VOUTR O Analog output, right channel 12 VA+ I Analog power supply, +5 V Digital ground 13 VA– I Analog power supply, –5 V 14 VOUTL O Analog output, left channel 15 AGNDL — Analog ground, left channel 16 VINL I Analog input, left channel Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 3 PGA2311 SBOS218D – DECEMBER 2001 – REVISED MAY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Supply voltage MAX VA+ 5.5 VA– –5.5 VD+ 5.5 VA+ to VD+ UNIT V < ±0.3 Analog input voltage 0 VA+, VA− Digital input voltage –0.3 VD+ V Operating temperature –40 85 °C 150 °C 150 °C Junction temperature Storage temperature, Tstg (1) –65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE UNIT PGA2311 in 16-Pin SOIC Package V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500 Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V PGA2311 in 16-Pin PDIP Package V(ESD) (1) (2) Electrostatic discharge V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VA+ Positive analog power supply 4.75 5 5.25 V VA– Negative analog power supply –4.75 –5 –5.25 V VD+ Digital power supply 4.75 5 5.25 V Operating temperature –40 25 85 °C 6.4 Thermal Information PGA2311 THERMAL METRIC (1) N (PDIP) DW (SOIC) 16 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 39.9 83 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26.2 44 °C/W RθJB Junction-to-board thermal resistance 20.1 40.5 °C/W ψJT Junction-to-top characterization parameter 10.7 11.5 °C/W ψJB Junction-to-board characterization parameter 19.9 40.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 PGA2311 www.ti.com SBOS218D – DECEMBER 2001 – REVISED MAY 2016 6.5 Electrical Characteristics At TA = +25°C, VA+ = +5 V, VA− = –5 V, VD+ = +5 V, RL = 100 kΩ, CL = 20 pF, BW measure = 10 Hz to 20 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS Step size Gain error Gain setting = 31.5 dB Gain matching Input resistance Input capacitance PGA2311P, U (U−grade) 0.5 dB ±0.05 dB ±0.05 dB 10 kΩ 3 PGA2311PA, UA (A−grade) pF 7 AC CHARACTERISTICS THD+N Dynamic range Voltage range, output VIN = 2 Vrms, f = 1 kHz PGA2311P, U (U−grade) 0.0004% 0.001% PGA2311PA, UA (A−grade) 0.0002% 0.0004% VIN = AGND, gain = 0 dB 116 PGA2311P, U (U−grade) (VA−) + 1.25 (VA+) –1.25 PGA2311PA, UA (A−grade) (VA−) + 1.25 (VA−) − 1.25 Voltage range, input (without clipping) 120 dB V 2.5 Output noise VIN = AGND, gain = 0 dB 2.5 Interchannel crosstalk f = 1 kHz –130 VIN = AGND, gain = 0 dB 0.25 Vrms 4 μVRMS dBFS OUTPUT BUFFER Offset voltage Load capacitance stability 0.5 100 mV pF Short-circuit current 50 mA Unity-gain bandwidth, small signal 10 MHz DIGITAL CHARACTERISTICS VIH High-level input voltage 2 VD+ V VIL Low-level input voltage –0.3 0.8 V VOH VOL High-level output voltage Low-level output voltage IO = 200 μA PGA2311P, U (U−grade) (VA+) − 1 PGA2311PA, UA (A−grade) (VD+) − 1 V IO = –3.2 mA Input leakage current 1 0.4 V 10 µA SWITCHING CHARACTERISTICS fSCLK Serial clock (SCLK) frequency 0 6.25 MHz tPL SCLK pulse duration low 80 tPH SCLK pulse duration high 80 ns tMI MUTE pulse duration low 2 ms ns INPUT TIMING tSDS SDI setup time 20 ns tSDH SDI hold time 20 ns tCSCR CS falling to SCLK rising 90 ns tCFCS SCLK falling to CS rising 35 ns OUTPUT TIMING tCSO CS low to SDO active tCFDO SCLK falling to SDO data valid tCSZ CS high to SDO high impedance 35 ns 60 ns 100 ns Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 5 PGA2311 SBOS218D – DECEMBER 2001 – REVISED MAY 2016 www.ti.com Electrical Characteristics (continued) At TA = +25°C, VA+ = +5 V, VA− = –5 V, VD+ = +5 V, RL = 100 kΩ, CL = 20 pF, BW measure = 10 Hz to 20 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY PSRR VA+ 4.75 5 5.25 Operating voltage VA– –4.75 –5 –5.25 VD+ 4.75 5 5.25 IA+ VA+ = +5 V 8 10 Quiescent current IA– VA– = –5 V 10 12 ID+ VD+ = +5 V 0.5 1 Power-supply rejection ratio (250 Hz) 100 V mA dB TEMPERATURE RANGE Operating range –40 85 °C Gain Byte Format is MSB First, Straight Binary R0 is the Least Significant Bit of the Right Channel Gain Byte R7 is the Most Significant Bit of the Right Channel Gain Byte L0 is the Least Significant Bit of the Left Channel Gain Byte L7 is the Most Significant Bit of the Left Channel Gain Byte SDI is latched on the rising edge of SCLK. SDO transitions on the falling edge of SCLK. Figure 1. Serial Interface Protocol 6 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 PGA2311 www.ti.com SBOS218D – DECEMBER 2001 – REVISED MAY 2016 Figure 2. Serial Interface Timing Requirements Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 7 PGA2311 SBOS218D – DECEMBER 2001 – REVISED MAY 2016 www.ti.com 6.6 Typical Characteristics At TA = +25°C, VA+ = +5 V, VA− = −5 V, VD+ = +5 V, RL = 100 kΩ, CL = 20 pF, BW measure = 10 Hz to 20 kHz, unless otherwise noted. All plots taken with PGA2311 A-grade. Gain = 0 dB, Load = 100 kΩ, VIN = 2 Vrms Gain = 0 dB, Freq = 1 kHz, Load = 100 kΩ Figure 3. Amplitude vs Frequency Gain = 0 dB, Freq = 1 kHz, Load = 600 Ω Figure 4. THD + N vs Amplitude Gain = 0 dB, VIN = 2 Vrms, Load = 100 kΩ Figure 5. THD + N vs Amplitude Figure 6. THD + N vs Frequency Gain = 0 dB, VIN = 2 Vrms, FIN = 1 kHz Gain = 0 dB, VIN = 2 Vrms, Load = 600 Ω Figure 7. THD + N vs Frequency 8 Figure 8. THD + N vs Input Source Impedance Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 PGA2311 www.ti.com SBOS218D – DECEMBER 2001 – REVISED MAY 2016 Typical Characteristics (continued) At TA = +25°C, VA+ = +5 V, VA− = −5 V, VD+ = +5 V, RL = 100 kΩ, CL = 20 pF, BW measure = 10 Hz to 20 kHz, unless otherwise noted. All plots taken with PGA2311 A-grade. Figure 9. Crosstalk With FIN = 1 kHz Figure 10. Crosstalk With FIN = 10 kHz Figure 11. Crosstalk With FIN = 20 kHz Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 9 PGA2311 SBOS218D – DECEMBER 2001 – REVISED MAY 2016 www.ti.com 7 Detailed Description 7.1 Overview The PGA2311 is a stereo audio volume control that can be used in a wide array of professional and consumer audio equipment. The PGA2311 is fabricated in a sub-micron CMOS process. The heart of the PGA2311 is a resistor network, an analog switch array, and a high-performance operational amplifier stage. The switches select taps in the resistor network that determine the gain of the amplifier stage. Switch selections are programmed using a serial control port. The serial port allows connection to a wide variety of host controllers. The Functional Block Diagram section shows a model diagram of the PGA2311. 7.2 Functional Block Diagram Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Analog Inputs and Outputs The PGA2311 includes two independent channels (referred to as the left and right channels). Each channel has a corresponding input and output pin. The input and output pins are unbalanced, or referenced to analog ground (either AGNDR or AGNDL). The inputs are VINR (pin 9) and VINL (pin 16), and the outputs are VOUTR (pin 11) and VOUTL (pin 14). The input and output pins can swing within 1.25 V of the analog power supplies, VA+ (pin 12) and VA− (pin 13). Given VA+ = +5 V and VA− = −5 V, the maximum input or output voltage range is 7.5 Vp-p. For optimal performance, drive the PGA2311 with a low source impedance. A source impedance of 600 Ω or less is recommended. Source impedances up to 2 kΩ cause minimal degradation of THD+N; see Figure 8 for more details. 10 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 PGA2311 www.ti.com SBOS218D – DECEMBER 2001 – REVISED MAY 2016 Feature Description (continued) 7.3.2 Gain Settings The gain for each channel is set by its corresponding 8-bit code, either R[7:0] or L[7:0] (see Figure 1). The gain code data is straight binary format. If N equals the decimal equivalent of R[7:0] or L[7:0], then the following relationships exist for the gain settings: • For N = 0: Mute Condition. The input multiplexer is connected to analog ground (AGNDR or AGNDL). • For N = 1 to 255: Gain (dB) = 31.5 − [0.5 w (255 − N)] This results in a gain range of +31.5 dB (with N = 255) to −95.5 dB (with N = 1). Changes in gain setting can be made with or without zero-crossing detection. The operation of the zero-crossing detector and timeout circuitry is discussed in the Zero-Crossing Detection section. 7.3.3 Daisy-Chaining Multiple PGA2311 Devices To reduce the number of control signals required to support multiple PGA2311 devices on a printed circuit board (PCB), the serial control port supports daisy-chaining of multiple PGA2311 devices. Figure 12 shows the connection requirements for daisy-chain operation. This arrangement allows a 3-wire serial interface to control many PGA2311 devices. As shown in Figure 12, the SDO pin from PGA2311 #1 is connected to the SDI input of PGA2311 #2, and is repeated for additional devices. This configuration in turn forms a large shift register, in which gain data can be written for all PGA2311s connected to the serial bus. The length of the shift register is 16 × N bits, where N is equal to the number of PGA2311 devices included in the chain. The CS input must remain LOW for 16 × N SCLK periods, where N is the number of devices connected in the chain, to allow enough SCLK cycles to load all devices. Figure 12. Daisy-Chaining Multiple PGA2311 Devices Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 11 PGA2311 SBOS218D – DECEMBER 2001 – REVISED MAY 2016 www.ti.com Feature Description (continued) 7.3.4 Zero-Crossing Detection The PGA2311 includes a zero-crossing detection function for noise-free level transitions. The concept is to change gain settings on a zero-crossing of the input signal, thus minimizing audible glitches. This function is enabled or disabled using the ZCEN input (pin 1). When ZCEN is LOW, zero-crossing detection is disabled. When ZCEN is HIGH, zero-crossing detection is enabled. The zero-crossing detection takes effect with a change in gain setting for a corresponding channel. The new gain setting is not implemented until either a positive slope zero crossing is detected, or a time-out period of 16 ms has elapsed. In the case of a time-out, the new gain setting takes effect with no attempt to minimize audible artifacts. 7.3.5 MUTE Function Muting can be achieved by either hardware or software control. Hardware muting is accomplished through the MUTE input, and software muting by loading all zeroes into the volume control register. MUTE disconnects the internal buffer amplifiers from the output pins and terminates AOUTL and AOUTR with 10-kΩ resistors to ground. The mute is activated with a zero-crossing detection (independent of the zero-cross enable status), or an 16-ms time-out to eliminate any audible clicks or pops. MUTE also initiates an internal offset calibration. A software mute is implemented by loading all zeroes into the volume control register. The internal amplifier is set to unity gain, with the amplifier input connected to AGND. 7.4 Device Functional Modes 7.4.1 Power-Up State On power-up, power-up reset is activated for approximately 100 ms, during which the circuit is in hardware MUTE state and all internal flip-flops are reset. At the end of this period, the offset calibration is initiated without any external signals. When this step is complete, the gain byte value for both the left and right channels are set to 00HEX, or the software MUTE condition. The gain remains at this setting until the host controller programs new settings for each channel via the serial control port. If the power-supply voltage drops below ±3.2 V during normal operation, the circuit enters a hardware MUTE state. A power-up sequence initiates if the power-supply voltage returns to greater than ±3.2 V. 7.5 Programming The serial control port is used to program the gain settings for the PGA2311. The serial control port includes three input pins and one output pin. The inputs include CS (pin 2), SDI (pin 3), and SCLK (pin 6). The sole output pin is SDO (pin 7). The CS pin functions as the chip-select input. Data can be written to the PGA2311 only when CS is LOW. SDI is the serial data input pin. Control data are provided as a 16-bit word at the SDI pin, 8 bits each for the left and right channel gain settings. Data are formatted as MSB first, in straight binary code. SCLK is the serial clock input. Data are clocked into SDI on the rising edge of SCLK. SDO is the serial data output pin, and used when daisy-chaining multiple PGA2311 devices. Daisy-chain operation is described in the Daisy-Chaining Multiple PGA2311 Devices section. SDO is a tri-state output, and assumes a high-impedance state when CS is HIGH. The protocol for the serial control port is illustrated in Figure 1; see Figure 2 for detailed timing specifications for the serial control port. 12 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 PGA2311 www.ti.com SBOS218D – DECEMBER 2001 – REVISED MAY 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The PGA2311 is commonly used as a digitally-controlled analog volume control. Analog volume is controlled through a serial interface in 0.5-dB steps, ranging from a gain of +31.5 dB down to an attenuation of −95.5 dB. 8.2 Typical Application Figure 13 shows the recommended connections for the PGA2311. Place power-supply bypass capacitors as close to the PGA2311 package as physically possible. Copyright © 2016, Texas Instruments Incorporated Figure 13. Recommended Connection Diagram 8.2.1 Design Requirements • • • Wide dynamic range, +35.5 dB to –95.5 dB Operate from a 5-V digital supply and ±5-V analog supplies Digitally-controlled analog volume 8.2.2 Detailed Design Procedure The PGA2311 is a complete digitally-controlled analog stereo volume controller system on a chip requiring only a controller to select the gain or attenuation through a serial interface. Figure 13 shows the basic connections to the PGA2311. Place power-supply bypass capacitors as close to the PGA2311 package as physically possible. Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 13 PGA2311 SBOS218D – DECEMBER 2001 – REVISED MAY 2016 www.ti.com Typical Application (continued) 8.2.3 Application Curve 3 0 dB -6 dB -12 dB Voltage (V) 1.5 0 -1.5 -3 0 0.0004 0.0008 0.0012 Time (s) 0.0016 0.002 Figure 14. PGA2311 Operating at 0 dB, –6 dB and –12 dB 9 Power Supply Recommendations The PGA2311 is specified for operation with its analog power supplies ranging from ±4.75 V to ±5.25 V and its digital power supply ranging from 4.75 V to 5.25 V. Place power-supply bypass capacitors as close to the PGA2311 package as physically possible. 14 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 PGA2311 www.ti.com SBOS218D – DECEMBER 2001 – REVISED MAY 2016 10 Layout 10.1 Layout Guidelines The ground planes for the digital and analog sections of the PCB must be separate from one another. The planes must be connected at a single point. Figure 15 shows the recommended PCB floor plan for the PGA2311. The PGA2311 is mounted so that the device straddles the split between the digital and analog ground planes. Pins 1 through 8 are oriented to the digital side of the board and pins 9 through 16 are on the analog side of the board. 10.2 Layout Example Figure 15. Typical PCB Layout Floor Plan Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 15 PGA2311 SBOS218D – DECEMBER 2001 – REVISED MAY 2016 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation, see the following: • Circuit Board Layout Techniques, SLOA089 • Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. E2E Audio Amplifier Forum TI's Engineer-to-Engineer (E2E) Community for Audio Amplifiers. Created to foster collaboration among engineers. Ask questions and receive answers in real-time. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Product Folder Links: PGA2311 PACKAGE OPTION ADDENDUM www.ti.com 13-Jul-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) PGA2311P ACTIVE PDIP N 16 25 RoHS & Green Call TI N / A for Pkg Type PGA2311P Samples PGA2311PA ACTIVE PDIP N 16 25 RoHS & Green Call TI N / A for Pkg Type PGA2311P A Samples PGA2311U ACTIVE SOIC DW 16 40 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 PGA2311U Samples PGA2311U/1K ACTIVE SOIC DW 16 1000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 PGA2311U Samples PGA2311UA ACTIVE SOIC DW 16 40 RoHS & Green Call TI Level-2-260C-1 YEAR PGA2311U A Samples PGA2311UA/1K ACTIVE SOIC DW 16 1000 RoHS & Green Call TI Level-2-260C-1 YEAR PGA2311U A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of