PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
www.ti.com
6-A, WIDE-INPUT ADJUSTABLE SWITCHING REGULATOR
Check for Samples: PTN78020W, PTN78020H
FEATURES
APPLICATIONS
•
•
•
1
•
•
•
•
•
•
•
•
6-A Output Current
Wide-Input Voltage
(7 V to 36 V) / (15 V to 36 V)
Wide-Output Voltage Adjust
(2.5 V to 12.6 V) / (11.85 V to 22 V)
High Efficiency (Up to 96%)
On/Off Inhibit
Undervoltage Lockout
Output Current Limit
Overtemperature Shutdown
Operating Temperature: -40°C to 85°C
Surface Mount Package Available
General-Purpose, Industrial Controls,
HVAC Systems, Test and Measurement,
Medical Instrumentation, AC/DC Adaptors,
Vehicles, Marine, and Avionics
DESCRIPTION
The PTN78020 is a series of high-efficiency, step-down integrated switching regulators (ISRs), that represent the
third generation in the evolution of high-performance power modules designed for industrial use. The wide-input
voltage range makes these modules suitable for a variety of applications that operate off 12–V, 24–V, and 28–V
dc power. In new designs they should be considered in place of the PT6620, PT6650, PT6680, and PT6880
series of single in-line pin (SIP) products. The PTN78020 is smaller and lighter than its predecessors, and has
either similar or improved electrical performance characteristics. The caseless, double-sided package has
excellent thermal characteristics, and is compatible with TI's roadmap for RoHS and lead-free compliance.
Operating from a wide-input voltage range, the PTN78020 provides high-efficiency, step-down voltage
conversion for loads of up to 6 A. The output voltage is set using a single, external resistor. The PTN78020W
may be set to any value within the range, 2.5 V to 12.6 V, and the PTN78020H from 11.85 V to 22 V. The output
voltage of the PTN78020W can be as little as 2 V lower than the input, allowing operation down to 7 V, with an
output voltage of 5 V. The output voltage of the PTN78020H can be as little as 3 V lower than the input, allowing
operation down to 15 V, with an output voltage of 12 V.
The PTN78020 has undervoltage lockout, an integral on/off inhibit, and includes an output current limit and
overtemperature protection.
STANDARD APPLICATION
VI
7
1
PTN78020
(Top View)
2
6
Inhibit
3
CI*
Ceramic
(Required)
GND
4
VO
VO Sense
5
RSET#
1%, 0.05 W
(Required)
CO*
330 mF
(Required)
L
O
A
D
GND
*See the Application Information section for capacitor recommendations. The minimum input capacitance
for is 2.2 mF for PTN78020W, and 18.8 mF (4 x 4.7 mF) for PTN78020H
#RSET is required to adjust the output voltage. See the Application Information section for values.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2011, Texas Instruments Incorporated
PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see
the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
all voltages with respect to GND
UNIT
TA
Over VI range
Wave solder temperature
Surface temperature of module body or pins
(5 seconds)
Solder reflow temperature
Surface temperature of module body or pins
Horizontal TH
(suffix AH & AD)
260°C
Horizontal SMD
(suffix AS)
235°C
Horizontal SMD
(suffix AZ)
260°C
–55°C to 125°C
TS
Storage temperature
VI
Input surge voltage, 10 ms maximum
VINH
Inhibit (pin 3) input voltage
PO
Output power
(1)
–40°C to 85°C
Operating free-air temperature
38 V
–0.3 V to 5 V
VI ≤ 24 V or VO ≥ 15 V
90 W
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
VI
Input voltage
TA
Operating free-air temperature
MIN
MAX
PTN78020W
7
36
PTN78020H
15
36
–40
85
UNIT
V
°C
PACKAGE SPECIFICATIONS
PTN78020x (Suffix AH, AS, & AZ)
Weight
7.3 grams
Flammability
Meets UL 94 V-O
Mechanical
shock
Per Mil-STD-883D, Method 2002.3, 1 ms, 1/2 sine,
mounted
Mechanical
vibration
(1)
2
Mil-STD-883D, Method 2007.2, 20-2000 Hz
Horizontal T/H (suffix AH and AD)
250 G
Horizontal SMD (suffix AS and AZ)
125 G
(1)
(1)
Horizontal T/H (suffix AH and AD)
20 G
(1)
Horizontal SMD (suffix AS and AZ)
10 G
(1)
Qualification limit.
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Copyright © 2004–2011, Texas Instruments Incorporated
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PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
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ELECTRICAL CHARACTERISTICS
operating at 25°C free-air temperature, VI = 20 V, VO = 5 V, IO = IO (max), CI = 2.2 µF, CO = 330 µF (unless otherwise noted)
PARAMETER
IO
Output current
VI
VO
VO (adj)
η
PTN78020W
TEST CONDITIONS
MIN
TA = 25°C, natural convection airflow
MAX
0.1
6
(1)
VI = 32 V
0.1
5
(1)
VI = 36 V
0.1
4.5
(1)
36
(3)
7
(2)
UNIT
A
Input voltage range
Over IO range
Set-point voltage tolerance
TA = 25°C
V
Temperature variation
–40°C to +85°C
Line regulation
Over VI range
±10
mV
Load regulation
Over IO range
±10
mV
Total output voltage variation
Includes set point, line, load
–40 < TA < 85°C
±2% (4)
±0.5%
±3%
(4)
VI < 12 V
2.5
VI – 2
12 V ≤ VI ≤ 15.1 V
2.5
VI – 2.5
15.1 V < VI ≤ 25 V
2.5
12.6
VI > 25 V
0.1 × VI
Output voltage adjust range
V
Efficiency
Output voltage ripple
20-MHz bandwith
Current limit threshold
ΔVO = –50 mV
12.6
VI = 24 V, RSET = 732 Ω, VO = 12 V
94%
VI = 15 V, RSET = 21 kΩ, VO = 5 V
88%
VI = 15 V, RSET = 78.7 kΩ, VO = 3.3 V
IO (LIM)
TYP
VI ≤24 V
85%
1% VO
V(PP)
8.5
A
1 A/µs load step from 50% to 100% IOmax
Transient response
Recovery time
200
VO over/undershoot
5
Input high voltage (VIH)
Inhibit control (pin 3)
Input low voltage (VIL)
1
Input standby current
mA
mA
VI increasing
5.5
VI decreasing
5.2
Switching frequency
Over VI and IO ranges
CI
External input capacitance
Ceramic and nonceramic
440
2.2
Nonceramic
Equiv. series resistance (nonceramic)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Per Telcordia SR-332, 50% stress,
TA = 40°C, ground benign
550
V
660
(6)
Ceramic
Calculated reliability
V
17
FS
MTBF
0.3
0.25
Undervoltage lockout
External output capacitance
(5)
Pin 3 connected to GND
UVLO
CO
Open
–0.1
Input low current (IIL)
II(stby)
µs
%VO
µF
300
330
(7)
10
(8)
kHz
2,000
5.6
µF
mΩ
106 Hr
Above an input voltage of 24 V, the maximum output current must be derated by 125 mA per volt above 24 V.
For output voltages less than 10 V, the minimum input voltage is 7 V or (VO + 2) V, whichever is greater. For output voltages of 10 V
and higher, the minimum input voltage is (VO + 2.5 V). See the Application Information section for further guidance.
For output voltages less than 3.6 V, the maximum input voltage is 10 × VO . See the Application Information section for further guidance.
The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1% with with 100 ppm/°C or better temperature stability.
This control pin has an internal pullup, and if left open-circuit, the module operates when input power is applied. The open-circuit voltage
is typically 1.5 V. A small, low-leakage (< 100 nA) MOSFET is recommended for control. See the Application Information section for
further guidance.
An external 2.2-µF ceramic capacitor is required across the input (VI and GND) for proper operation. Locate the capacitor close to the
module.
330 µF of output capacitance is required for proper operation. See the Application Information section for further guidance.
This is the typical ESR for all the electrolytic (nonceramic) capacitance. Use 17 mΩ as the minimum when using max-ESR values to
calculate.
Copyright © 2004–2011, Texas Instruments Incorporated
Product Folder Link(s): PTN78020W PTN78020H
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PTN78020H
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ELECTRICAL CHARACTERISTICS
operating at 25°C free-air temperature, VI = 24 V, VO = 12 V, IO = IO (max), CI = 4× 4.7 µF, CO = 330 µF (unless otherwise
noted)
PARAMETER
IO
Output current
VI
VO
VO (adj)
η
PTN78020H
TEST CONDITIONS
TA = 25°C, natural convection airflow
MIN
MAX
0.1
Vo =15 V
0.1
6
Vo = 22 V
0.1
4.09
15
6
(1) (2)
(3)
UNIT
(1)
A
(2)
Input voltage range
Over IO range
Set-point voltage tolerance
TA = 25°C
Temperature variation
–40°C to +85°C
Line regulation
Over VI range
±10
mV
Load regulation
Over IO range
±10
mV
Total output voltage variation
Includes set point, line, load
–40 < TA < 85°C
20-MHz bandwith
Current limit threshold
ΔVO = –50 mV
V
±0.5%
±3%
(4)
VI < 19 V
11.85
VI – 3
19 V ≤ VI ≤ 25 V
11.85
VI – 4
VI > 25 V
11.85
V
22
VI = 24 V, RSET = 383 k Ω, VO = 12 V
94%
VI = 24 V, RSET = 15 kΩ, VO = 15 V
95%
VI = 32 V, RSET = 95.3 Ω, VO = 22 V
Output voltage ripple
36
±2% (4)
Output voltage adjust range
Efficiency
IO (LIM)
TYP
Vo =12 V
96%
1% VO
V(PP)
8.0
A
1 A/µs load step from 50% to 100% IOmax
Transient response
Recovery time
200
µs
VO over/undershoot
200
mV
Input high voltage (VIH)
Inhibit control (pin 3)
1
–0.1
Input low voltage (VIL)
Input low current (IIL)
II(stby)
Input standby current
UVLO
Undervoltage lockout
FS
Switching frequency
CI
External input capacitance
Pin 3 connected to GND
VI increasing
External output capacitance
VI decreasing
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
4
Calculated reliability
0.3
Over VI and IO ranges
440
Ceramic and nonceramic
18.8
Nonceramic
Per Telcordia SR-332, 50% stress,
TA = 40°C, ground benign
mA
17
mA
V
550
660
(6)
kHz
µF
0
300
330
(7)
2,000
10
(8)
5.6
V
0.25
12
Equiv. series resistance (nonceramic)
MTBF
(5)
12.2
Ceramic
CO
Open
µF
mΩ
106 Hr
The maximum output current is 6 A or a maximum output power of 90 W, whichever is less. Above an input voltage of 24 V, the
maximum output current must be derated by 125 mA per volt above 24 V. See the Typica lCharacteristics section for further guidance.
Above an output voltage of 15 V, the maximum output current must be derated by 285 mA per volt. The maximum output power is 90 W.
See the application information for further guidance.
For output voltages less than 19 V, the minimum input voltage is 15 V or (VO + 3) V, whichever is greater. For output voltages of 19 V
and higher, the minimum input voltage is (VO + 4 V). See the Application Information section for further guidance.
The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1% with with 100 ppm/°C or better temperature stability.
This control pin has an internal pullup, and if left open-circuit, the module operates when input power is applied. The open-circuit voltage
is typically 1.5 V. A small, low-leakage (< 100 nA) MOSFET is recommended for control. See the Application Information section for
further guidance.
Four external 4.7-µF ceramic capacitors are required across the input (VI and GND) for proper operation. Locate the capacitors close to
the module.
330 µF of output capacitance is required for proper operation. See the Application Information section for further guidance.
This is the typical ESR for all the electrolytic (nonceramic) capacitance. Use 17 mΩ as the minimum when using max-ESR values to
calculate.
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Product Folder Link(s): PTN78020W PTN78020H
PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
www.ti.com
PIN ASSIGNMENT
1
7
PTN78020
(Top View)
2
6
3
4
5
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
GND
1, 7
I/O
DESCRIPTION
This is the common ground connection for the VI and VO power connections. It is also the 0-Vdc reference
for the Inhibit and VO Adjust control inputs.
VI
2
I
The positive input voltage power node to the module, which is referenced to common GND.
Inhibit
3
I
The Inhibit pin is an open-collector/drain active-low input that is referenced to GND. Applying a low-level
ground signal to this input disables the module's output and turns off the output voltage. When the Inhibit
control is active, the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left
open-circuit, the module produces an output whenever a valid input source is applied.
VO Adjust
4
I
A 1% resistor must be connected between this pin and GND (pin 7) to set the output voltage of the
module. If left open-circuit, the output voltage is set to its default value. The temperature stability of the
resistor should be 100 ppm/°C (or better). The standard resistor value for a number of common output
voltages is provided in the application information.
VO Sense
5
I
The sense input allows the regulation circuit to compensate for voltage drop between the module and the
load. For optimum voltage accuracy, VO Sense should be connected to VO
. If the
sense feature is not used, this pin may be left disconnected.
VO
6
O
The regulated positive power output with respect to the GND node.
Copyright © 2004–2011, Texas Instruments Incorporated
Product Folder Link(s): PTN78020W PTN78020H
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PTN78020H
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TYPICAL CHARACTERISTICS (7-V INPUT) (1)
EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT VOLTAGE RIPPLE
vs
OUTPUT CURRENT
VO = 5 V
VO = 3.3 V
70
60
40
30
VO = 3.3 V
VO = 5 V
20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
IO - Output Current - A
Figure 2.
Figure 3.
TEMPERATURE DERATING
vs
OUTPUT CURRENT
90
90
80
80
Airflow
Temperature Derating - oC
Temperature Derating - oC
1
0
TEMPERATURE DERATING
vs
OUTPUT CURRENT
200 LFM
70
100 LFM
60
Nat conv
50
40
VO = 3.3 V
30
Airflow
200 LFM
70
100 LFM
60
Nat conv
50
40
VO = 5 V
30
20
20
0
1
2
3
4
IO - Output Current - A
5
6
0
Figure 4.
6
VO = 3.3 V
IO - Output Current - A
Figure 1.
(2)
2
VO = 5 V
IO - Output Current - A
(1)
3
10
0
50
4
PD- Power Dissipation - W
VO- Output Voltage Ripple - mVPP
90
Efficiency - %
POWER DISSIPATION
vs
OUTPUT CURRENT
50
100
80
(2)
1
2
3
4
IO - Output Current - A
5
6
Figure 5.
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 1, Figure 2, and Figure 3.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to modules soldered directly to a 100 mm x 100 mm double-sided PCB with 2 oz. copper.
For surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power
pins. Please refer to the mechanical specification for more information. Applies to Figure 4 and Figure 5.
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TYPICAL CHARACTERISTICS (15-V INPUT) (1)
EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT VOLTAGE RIPPLE
vs
OUTPUT CURRENT
VO = 5 V
VO = 3.3 V
70
60
40
VO = 5 V
0
1
2
3
4
5
VO = 12 V
30
20
VO = 3.3 V
10
6
Figure 6.
1
2
3
4
5
VO = 5 V
1
0
6
1
2
3
4
5
6
IO - Output Current - A
Figure 7.
Figure 8.
TEMPERATURE DERATING
vs
OUTPUT CURRENT
90
90
200 LFM
80
Temperature Derating - oC
80
Temperature Derating - oC
2
0
0
TEMPERATURE DERATING
vs
OUTPUT CURRENT
Airflow
70
100 LFM
60
50
Nat conv
40
VO = 5 V
30
200 LFM
Airflow
70
100 LFM
60
Nat conv
50
40
VO = 12 V
30
20
20
0
1
2
3
4
IO - Output Current - A
5
6
0
Figure 9.
(2)
VO = 3.3 V
3
IO - Output Current - A
IO - Output Current - A
(1)
4
VO = 12 V
0
50
5
PD - Power Dissipation - W
VO- Output Voltage Ripple - mVPP
VO = 12 V
90
Efficiency - %
POWER DISSIPATION
vs
OUTPUT CURRENT
50
100
80
(2)
1
2
3
4
IO - Output Current - A
5
6
Figure 10.
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 6, Figure 7, and Figure 8.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to modules soldered directly to a 100 mm x 100 mm double-sided PCB with 2 oz. copper.
For surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power
pins. Please refer to the mechanical specification for more information. Applies to Figure 9 and Figure 10.
Copyright © 2004–2011, Texas Instruments Incorporated
Product Folder Link(s): PTN78020W PTN78020H
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PTN78020H
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TYPICAL CHARACTERISTICS (24-V INPUT) (1)
EFFICIENCY
vs
OUTPUT CURRENT
VO - Output Voltage Ripple - mVPP
VO = 15 V
80
VO = 12 V
70
VO = 5 V
60
POWER DISSIPATION
vs
OUTPUT CURRENT
6
70
VO = 18 V
90
Efficiency - %
OUTPUT VOLTAGE RIPPLE
vs
OUTPUT CURRENT
50
VO = 3.3 V
40
VO = 12 V
60
VO = 15 V
50
40
VO = 18 V
30
20
VO = 5 V
10
5
PD - Power Dissipation - W
100
VO = 5 V
4
VO = 3.3 V
3
VO = 12 V
2
VO = 15 V
1
1
2
3
4
5
VO = 18 V
VO = 3.3 V
0
0
(2)
6
0
1
2
3
5
4
0
6
0
1
2
3
4
5
IO - Output Current - A
IO - Output Current - A
Figure 11.
Figure 12.
Figure 13.
TEMPERATURE DERATING
vs
OUTPUT CURRENT
TEMPERATURE DERATING
vs
OUTPUT CURRENT
TEMPERATURE DERATING
vs
OUTPUT CURRENT
90
6
IO - Output Current - A
90
90
200 LFM
80
70
Airflow
60
100 LFM
50
Nat conv
40
30
70
Airflow
50
Nat conv
40
30
1
2
3
4
IO - Output Current - A
5
Figure 14.
8
Airflow
6
100 LFM
60
50
Nat conv
40
30
VO = 15 V
20
0
70
VO = 12 V
20
(2)
100 LFM
60
VO = 5 V
(1)
80
200 LFM
Temperature Derating - °C
200 LFM
Temperature Derating - °C
Temperature Derating - °C
80
20
0
1
2
3
4
IO - Output Current - A
5
6
0
Figure 15.
1
2
3
4
IO - Output Current - A
5
6
Figure 16.
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 11, Figure 12, and Figure 13.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to modules soldered directly to a 100 mm x 100 mm double-sided PCB with 2 oz. copper.
For surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power
pins. Please refer to the mechanical specification for more information. Applies to Figure 14 through Figure 16.
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TYPICAL CHARACTERISTICS (32-V INPUT) (1)
VO = 12 V
VO = 15 V
VO = 5 V
VO = 3.3 V
0
1
2
3
4
80
7
70
6
60
VO = 22 V
50
40
VO = 12 V
30
20
0
5
VO = 5 V
VO = 3.3 V
10
0
1
2
3
4
VO = 3.3 V
3
VO = 22 V
2
VO = 15 V
1
0
1
2
3
5
4
IO - Output Current - A
Figure 17.
Figure 18.
Figure 19.
TEMPERATURE DERATING
vs
OUTPUT CURRENT
TEMPERATURE DERATING
vs
OUTPUT CURRENT
TEMPERATURE DERATING
vs
OUTPUT CURRENT
90
90
90
200 LFM
80
Temperature Derating - °C
200 LFM
70
Airflow
60
100 LFM
50
Nat conv
40
30
80
70
Airflow
60
100 LFM
50
Nat conv
40
30
VO = 5 V
20
20
0
5
4
0
5
VO = 12 V
VO = 5 V
IO - Output Current - A
IO - Output Current - A
Temperature Derating - °C
VO = 15 V
1
2
3
4
IO - Output Current - A
Temperature Derating - °C
75
70
65
60
55
50
45
40
VO = 22 V
POWER DISSIPATION
vs
OUTPUT CURRENT
PD - Power Dissipation - W
100
95
90
85
80
OUTPUT VOLTAGE RIPPLE
vs
OUTPUT CURRENT
VO - Output Voltage Ripple - mVPP
Efficiency - %
EFFICIENCY
vs
OUTPUT CURRENT
(2)
5
60
100 LFM
50
Nat conv
40
30
20
1
2
3
4
5
0
1
2
3
4
5
IO - Output Current - A
IO - Output Current - A
Figure 20.
Airflow
70
VO = 15 V
VO = 12 V
0
200 LFM
80
Figure 21.
Figure 22.
TEMPERATURE DERATING
vs
OUTPUT CURRENT
Temperature Derating - °C
90
80
200 LFM
70
100 LFM
60
Nat conv
Airflow
50
40
30
VO = 22 V
20
0
1
2
3
IO - Output Current - A
4
Figure 23.
(1)
(2)
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 17, Figure 18, and Figure 19.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to modules soldered directly to a 100 mm x 100 mm double-sided PCB with 2 oz. copper.
For surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power
pins. Please refer to the mechanical specification for more information. Applies to Figure 20 through Figure 23.
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PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
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APPLICATION INFORMATION
Adjusting the Output Voltage of the PTN78020x Series of Wide-Output Adjust Power Modules
General
A resistor must be connected between the VO Adjust control (pin 4) and GND (pin 7) to set the output voltage.
The adjustment range is from 2.5 V to 12.6 V for PTN78020W. The adjustment range is from 11.85 V to 22 V for
PTN78020H. If pin 4 is left open, the output voltage defaults to the lowest value.
Table 2 gives the preferred value of the external resistor for a number of standard voltages, with the actual
output voltage that the value provides. For other output voltages, the value of the required resistor can either be
calculated using Equation 1 and the constants for the applicable product in Table 1. Figure 24 shows the
placement of the required resistor.
1.25 V
VO - Vmin
RSET = 54.9 kW ´
- RP
(1)
Table 1. RSET Formula Constants
PRODUCT
VMIN
RP
PTN780x0W
2.5 V
6.49 kΩ
PTN780x0H
11.824 V
6.65 kΩ
Input Voltage Considerations
The PTN78020 is a step-down switching regulator. In order that the output remains in regulation, the input
voltage must exceed the output by a minimum differential voltage.
Another consideration is the pulse width modulation (PWM) range of the regulator's internal control circuit. For
stable operation, its operating duty cycle should not be lower than some minimum percentage. This defines the
maximum advisable ratio between the regulator input and output voltage magnitudes.
As an example, for satisfactory performance, the operating input voltage range of the PTN78020x must adhere to
the following requirements.
1. For PTN78020W output voltages lower than 10 V, the minimum input voltage is (VO + 2 V) or 7 V, whichever
is higher.
2. For PTN78020W output voltages equal to 10 V and higher, the minimum input voltage is (VO + 2.5 V) .
3. For PTN78020W, the maximum input voltage is (10 × VO) or 36 V, whichever is less.
4. For PTN78020H output voltages lower than 19 V, the minimum input voltage is (VO + 3 V) or 15 V, whichever
is higher.
5. For PTN78020H output voltages equal to 19 V and higher, the minimum input voltage is (VO + 4 V) .
Table 2 gives the operating input voltage range for the common output bus voltages. In addition, the Electrical
Characteristics table defines the available output voltage adjust range for various input voltages.
Table 2. Standard Values of Rset for Common Output Voltages
PRODUCT
PTN780x0W
PTN780x0H
10
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VO
(Required)
RSET
(Standard Value)
VO
(Actual)
Operating
VI Range
2.5 V
Open
2.5 V
7 V to 25 V
3.3 V
78.7 kΩ
3.306 V
7 V to 33 V
5V
21 kΩ
4.996 V
7 V to 36 V
12 V
732 Ω
12.002 V
14.5 V to 36 V
12 V
383 kΩ
12.000 V
15 V to 36 V
15 V
15 kΩ
14.994 V
18 V to 36 V
18 V
4.42 kΩ
18.023 V
21 V to 36 V
22 V
95.3
21.998 V
26 V to 36 V
Copyright © 2004–2011, Texas Instruments Incorporated
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5
Sense
VI
2
PTN78020W
VI
Inhibit
3
VO
VO
6
GND GND Adjust
1
7
4
CI
2.2 mF
Ceramic
RSET
0 .05 W
CO
330 mF
1%
GND
GND
(1)
A 0.05-W rated resistor may be used. The tolerance should be 1%, with a temperature stability of 100 ppm/°C (or
better). Place the resistor as close to the regulator as possible. Connect the resistor directly between pins 4 and 7
using dedicated PCB traces.
(2)
Never connect capacitors from VO Adjust to either GND or VO
pin affects the stability of the regulator.
. Any capacitance added to the VO Adjust
Figure 24. PTN78020W VO Adjust Resistor Placement
Table 3. PTN78020W Output Voltage Set-Point Resistor Values
VO (V)
RSET (kΩ)
VO (V)
RSET (kΩ)
VO (V)
RSET (kΩ)
VO (V)
RSET (kΩ)
2.50
Open
3.7 V
50.7
6.1
12.6
9.0
4.07
2.55
1370
3.8 V
46
6.2
12.1
9.2
3.75
2.60
680
3.9 V
42.5
6.3
11.6
9.4
3.46
2.65
451
4.0 V
39.3
6.4
11.1
9.6
3.18
2.70
337
4.1 V
36.4
6.5
10.7
9.8
2.91
2.75
268
4.2 V
33.9
6.6
10.2
10.0
2.66
2.80
222
4.3 V
31.6
6.7
9.85
10.2
2.42
2.85
190
4.4 V
29.6
6.8
9.47
10.4
2.20
2.90
165
4.5 V
27.8
6.9
9.11
10.6
1.98
2.95
146
4.6 V
26.2
7.0
8.76
10.8
1.78
3.00
131
4.7 V
24.7
7.1
8.43
11.0
1.58
3.05
118
4.8 V
23.3
7.2
8.11
11.2
1.40
3.10
108
4.9 V
22.1
7.3
7.81
11.4
1.22
3.15
99.1
5.0 V
21.0
7.4
7.52
11.6
1.05
3.20
91.5
5.1 V
19.9
7.5
7.24
11.8
0.889
3.25
85.0
5.2 V
18.9
7.6
6.97
12.0
0.734
3.30
79.3
5.3 V
18.0
7.7
6.71
12.2
0.585
3.35
74.2
5.4 V
17.2
7.8
6.46
12.4
0.442
3.40
69.8
5.5 V
16.4
7.9
6.22
12.6
0.305
3.45
65.7
5.6 V
15.6
8.0
5.99
3.50
62.1
5.7 V
15.0
8.2
5.55
3.55
58.9
5.8 V
14.3
8.4
5.14
3.60
55.9
5.9 V
13.7
8.6
4.76
3.65
53.2
6.0 V
13.1
8.8
4.40
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PTN78020H
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5
Sense
VI
2
PTN78020H
VI
Inhibit
3
VO
VO
6
GND GND Adjust
1
7
4
CI
4 x 4.7 mF
Ceramic
RSET
CO
330 mF
0 .05 W
1%
GND
GND
(1)
A 0.05-W rated resistor may be used. The tolerance should be 1%, with a temperature stability of 100 ppm/°C (or
better). Place the resistor as close to the regulator as possible. Connect the resistor directly between pins 4 and 7
using dedicated PCB traces.
(2)
Never connect capacitors from VO Adjust to either GND or VO
pin affects the stability of the regulator.
. Any capacitance added to the VO Adjust
Figure 25. PTN78020H VO Adjust Resistor Placement
Table 4. PTN78020H Output Voltage Set-Point Resistor Values
12
VO
RSET
VO
RSET
VO
RSET
11.85 V
2633 kΩ
13.50 V
34.3 kΩ
17.20 V
6.12 kΩ
11.90 V
896 kΩ
13.65 V
30.9 kΩ
17.40 V
5.66 kΩ
11.95 V
538 kΩ
13.80 V
28.1 kΩ
17.60 V
5.23 kΩ
12.00 V
383 kΩ
13.95 V
25.6 kΩ
17.80 V
4.83 kΩ
12.10 V
242 kΩ
14.10 V
23.5 kΩ
18.00 V
4.46 kΩ
12.15 V
204 kΩ
14.25 V
21.6 kΩ
18.20 V
4.11 kΩ
12.20 V
176 kΩ
14.40 V
19.9 kΩ
18.40 V
3.79 kΩ
12.25 V
154 kΩ
14.55 V
18.5 kΩ
18.60 V
3.48 kΩ
12.30 V
138 kΩ
14.70 V
17.2 kΩ
18.80 V
3.19 kΩ
12.35 V
124 kΩ
14.85 V
16.0 kΩ
19.00 V
2.91 kΩ
12.40 V
113 kΩ
15.00 V
14.9 kΩ
19.20 V
2.65 kΩ
12.45 V
103 kΩ
15.15 V
13.9 kΩ
19.40 V
2.41 kΩ
12.50 V
94.9 kΩ
15.30 V
13.1 kΩ
19.60 V
2.18 kΩ
12.55 V
87.9 kΩ
15.45 V
12.3 kΩ
19.80 V
1.95 kΩ
12.60 V
81.8 kΩ
15.60 V
11.5 kΩ
20.00 V
1.74 kΩ
12.65 V
76.4 kΩ
15.75 V
10.8 kΩ
20.20 V
1.54 kΩ
12.70 V
71.7 kΩ
15.90 V
10.2 kΩ
20.40 V
1.35 kΩ
12.75 V
67.5 kΩ
16.05 V
9.59 kΩ
20.60 V
1.17 kΩ
12.80 V
63.7 kΩ
16.20 V
9.03 kΩ
20.80 V
995 Ω
12.85 V
60.2 kΩ
16.35 V
8.51 kΩ
21.00 V
829 kΩ
12.90 V
57.1 kΩ
16.50 V
8.03 kΩ
21.20 V
669 Ω
12.95 V
54.3 kΩ
16.65 V
7.57 kΩ
21.40 V
516 Ω
13.00 V
51.7 kΩ
16.80 V
7.14 kΩ
21.80 V
229 Ω
13.05 V
49.3 kΩ
17.10 V
6.36 kΩ
22.00 V
94 Ω
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CAPACITOR RECOMMENDATIONS for the PTN78020 WIDE-OUTPUT
ADJUST POWER MODULES
PTN78020W Input Capacitor
The minimum requirement for the input capacitance is a 2.2-µF ceramic capacitor for PTN78020W, in either a
X5R or X7R temperature characteristic. Ceramic capacitors should be located within 0.5 inch (1,27 cm) of the
regulator's input pins. Electrolytic capacitors can be used at the input, but only in addition to the required ceramic
capacitance. The minimum ripple current rating for any nonceramic capacitance must be at least 500 mA rms for
VO ≤ 5.5. For VO > 5.5 V, the minimum ripple current rating is 750 mA rms. The ripple current rating of electrolytic
capacitors is a major consideration when they are used at the input. This ripple current requirement can be
reduced by placing more ceramic capacitors at the input, in addition to the minimum required 2.2 µF.
Tantalum capacitors are not recommended for use at the input bus, as none were found to meet the minimum
voltage rating of 2 × (maximum dc voltage + ac ripple). This voltage derating is standard practice for regular
tantalum capacitors to ensure reliability. Polymer-tantalum capacitors are more reliable, and are available with a
maximum rating of typically 20 V. These can be used with input voltages up to 16 V.
PTN78020H Input Capacitor
The minimum requirement for PTN78020H the input capacitance is 18.8 µF (4x 4.7-µF) or equivalent . Ceramic
capacitors should be located within 0.5 inch (1,27 cm) of the regulator's input pins. Electrolytic capacitors can be
used at the input, but only in addition to the required ceramic capacitance. The minimum ripple current rating for
any nonceramic capacitance must be at least 500 mA rms for VO ≤ 5.5. For VO > 5.5 V, the minimum ripple
current rating is 750 mA rms. The ripple current rating of electrolytic capacitors is a major consideration when
they are used at the input.
Tantalum capacitors are not recommended for use at the input bus, as none meet the minimum voltage rating of
2 × (maximum dc voltage + ac ripple). This voltage derating is standard practice for regular tantalum capacitors
to ensure reliability. Polymer-tantalum capacitors are more reliable, and are available with a maximum rating of
typically 20 V. These can be used with input voltages up to 16 V.
PTN78020W/PTN78020H Output Capacitor
The minimum capacitance required to ensure stability is a 330 µF. Either ceramic or electrolytic-type capacitors
can be used. The minimum ripple current rating for the nonceramic capacitance must be at least 250 mA rms.
The stability of the module and voltage tolerances are compromised if the capacitor is not placed near the output
bus pins. A high-quality, computer-grade electrolytic capacitor should be adequate. A ceramic capacitor can be
also be located within 0.5 inch (1,27 cm) of the output pin.
For applications with load transients (sudden changes in load current), the regulator response improves with
additional capacitance. Additional electrolytic capacitors should be located close to the load circuit. These
capacitors provide decoupling over the frequency range, 2 kHz to 150 kHz. Aluminum electrolytic capacitors are
suitable for ambient temperatures above 0°C. For operation below 0°C, tantalum or Os-Con type capacitors are
recommended. When using one or more nonceramic capacitors, the calculated equivalent ESR should be no
lower than 10 m Ω (17 mΩ using the manufacturer's maximum ESR for a single capacitor). A list of capacitors
and vendors are identified in Table 5 and Table 6, the recommended capacitor tables.
Ceramic Capacitors
Above 150 kHz, the performance of aluminum electrolytic capacitors becomes less effective. To further reduce
the reflected input ripple current, or the output transient response, multilayer ceramic capacitors must be added.
Ceramic capacitors have low ESR and their resonant frequency is higher than the bandwidth of the regulator.
When placed at the output, their combined ESR is not critical as long as the total value of ceramic capacitance
does not exceed 300 µF. Also, to prevent the formation of local resonances, do not place more than three
identical ceramic capacitors with values of 10 µF or greater in parallel.
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PTN78020H
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Tantalum Capacitors
Tantalum-type capacitors may be used at the output, and are recommended for applications where the ambient
operating temperature can be less than 0°C. The AVX TPS, Sprague 593D/594/595, and Kemet
T495/T510/T520 capacitors series are suggested over many other tantalum types due to their rated surge, power
dissipation, and ripple current capability. As a caution, many general-purpose tantalum capacitors have
considerably higher ESR, reduced power dissipation, and lower ripple current capability. These capacitors are
also less reliable as they have lower power dissipation and surge current ratings. Tantalum capacitors that do not
have a stated ESR or surge current rating are not recommended for power applications. When specifying
Os-Con and polymer-tantalum capacitors for the output, the minimum ESR limit is encountered well before the
maximum capacitance value is reached.
Capacitor Table
The capacitor tables, Table 5 and Table 6, identifies the characteristics of capacitors from a number of vendors
with acceptable ESR and ripple current (rms) ratings. The recommended number of capacitors required at both
the input and output buses is identified for each capacitor type. This is not an extensive capacitor list. Capacitors
from other vendors are available with comparable specifications. Those listed are for guidance. The rms rating
and ESR (at 100 kHz) are critical parameters necessary to ensure both optimum regulator performance and long
capacitor life.
Designing for Load Transients
The transient response of the dc/dc converter has been characterized using a load transient with a di/dt of
1 A/µs. The typical voltage deviation for this load transient is given in the data sheet specification table using the
required value of output capacitance. As the di/dt of a transient is increased, the response of a converter's
regulation circuit ultimately depends on its output capacitor decoupling network. This is an inherent limitation of
any dc/dc converter once the speed of the transient exceeds its bandwidth capability. If the target application
specifies a higher di/dt or lower voltage deviation, the requirement can only be met with additional output
capacitor decoupling. In these cases, special attention must be paid to the type, value, and ESR of the
capacitors selected.
Table 5. Recommended Input/Output Capacitors (PTN78020W)
CAPACITOR CHARACTERISTICS
QUANTITY
WORKING
VOLTAGE
(V)
VALUE
(µF)
EQUIVALENT
SERIES
RESISTANCE
(ESR) (Ω)
85°C
MAXIMUM
RIPPLE
CURRENT
(mArms)
Panasonic FC( Radial)
35
330
0.068
1050
10 × 16
FK (SMD)
50
330
0.12
900
12,5 × 13,5
United Chemi-Con PXA (SMD)
16
330
0.014
4360
10 × 12,2
PS
16
330
0.014
5500
LXZ
35
220
0.090
MVZ(SMD)
25
470
0.09
Nichicon UWG (SMD)
35
330
0.15
670
10 × 10
SP
20
180
0.032
4280
10 ×10.5
2
(1)
≤2
20SP180M (VI ~VO ≤ 16 V)
Sanyo Os-Con SVP (SMD)
16
330
0.020
4700
10 × 12,7
1
(1)
≤1
16SVP330M (VI ≤ 14 V)
SP
20
180
0.032
4280
10 ×10.5
2
(1)
≤2
20SP180M (VI ≤ 16 V)
20
100
0.085
1543
7,3 L × 4,3
W × 4,1 H
N/R
(2)
≤3
TPSV107M020R0085
(VO ≤ 10 V)
20
100
0.200
> 817
3225
N/R
(2)
≤3
TPSE107M020R0200
(VO ≤ 10 V)
CAPACITOR VENDOR/
COMPONENT
SERIES
AVX Tantalum TPS (SMD)
(1)
(2)
14
PHYSICAL
SIZE
(mm)
INPUT
BUS
OUTPUT
BUS
1
VENDOR
NUMBER
1
EEUFC1V331 (VI < 30 V)
(1)
1
EEVFK1H331Q
1
(1)
≤1
PXA16VC331MJ12TP
(VI < 14 V)
10 × 12,5
1
(1)
≤1
16PS330M J12 (VI < 14 V)
760
10 × 12,5
1 (1)
2
LXZ35VB221M10X12LL
(VI < 30 V)
670
10 × 10
1
1
MVZ25VC471MJ10TP
(VI < 24 V) (VO ≤ 5.5 V)
1
UWG1V331MNR1GS
1
1
The voltage rating of the input capacitor must be selected for the desired operating input voltage range of the regulator. To operate the
regulator at a higher input voltage, select a capacitor with the next higher voltage rating.
Not recommended (N/R). The voltage rating does not meet the minimum operating limits in most applications.
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Table 5. Recommended Input/Output Capacitors (PTN78020W) (continued)
CAPACITOR CHARACTERISTICS
QUANTITY
WORKING
VOLTAGE
(V)
VALUE
(µF)
EQUIVALENT
SERIES
RESISTANCE
(ESR) (Ω)
85°C
MAXIMUM
RIPPLE
CURRENT
(mArms)
Kemet X5R Ceramic
6.3
47
0.002
>1000
3225
N/R
(3)
≤4
C1210C476K9PAC
(VO ≤ 5.5 V)
TDK X5R Ceramic
6.3
47
0.002
>1000
3225
N/R
(3)
≤4
C3225X5R0J476MT
(VO ≤ 5.5 V)
Murata X5R Ceramic
6.3
47
0.002
>1000
3225
N/R
(3)
≤4
GRM42-2X5R476M6.3
(VO ≤ 5.5 V)
Murata X7R Ceramic
50
4.7
0.002
>1000
3225
≥1
1
GRM32ER71H475KA88L
TDK X7R Ceramic
50
2.2
0.002
>1000
3225
≥1
1
C3225X7R1H225KT
TDK X7R Ceramic
25
2.2
0.002
>1000
3225
≥1
(4)
1
C3225X7R1E225KT/MT
(VI~VO ≤ 20 V)
Kemet X7R Ceramic
25
2.2
0.002
>1000
3225
≥1
(4)
1
C1210C225K3RAC
(VO ≤ 20 V)
AVX X7R Ceramic
25
2.2
0.002
>1000
3225
≥1
(4)
1
C12103C225KAT2A
(VO ≤ 20 V)
TDK X7R Ceramic
50
1.0
0.002
>1000
3225
≥2
(5)
1
C3225X7R1H105KT
Kemet X7R Ceramic
50
1.0
0.002
>1000
3225
≥2
(5)
1
C1210C105K5RAC
≥2
(5)
1
C330C105K5R5CA
1
RPER71H2R2KK6F03
CAPACITOR VENDOR/
COMPONENT
SERIES
PHYSICAL
SIZE
(mm)
Kemet Radial Through-hole
50
1.0
0.002
>1000
5,08 × 7,62
× 9,14 H
Murata Radial Through-hole
50
2.2
0.004
>1000
10 H × 10
W×4D
(3)
(4)
(5)
INPUT
BUS
≥1
OUTPUT
BUS
VENDOR
NUMBER
The voltage rating of the input capacitor must be selected for the desired operating input voltage range of the regulator. To operate the
regulator at a higher input voltage, select a capacitor with the next higher voltage rating.
The maximum rating of the ceramic capacitor limits the regulator operating input voltage to 20 V. Select a alternative ceramic
component to operate at a higher input voltage.
A total capacitance of 2 µF is an acceptable replacement value for a single 2.2-µF ceramic capacitor
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PTN78020H
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Table 6. Recommended Input/Output Capacitors (PTN78020H)
CAPACITOR CHARACTERISTICS
QUANTITY
WORKING
VOLTAGE
(V)
VALUE
(µF)
EQUIVALENT
SERIES
RESISTANCE
(ESR) (Ω)
85°C
MAXIMUM
RIPPLE
CURRENT
(mArms)
Panasonic FC( Radial)
35
330
0.068
1050
10 × 16
FK (SMD)
50
330
0.12
900
12,5 × 13,5
LXZ
35
220
0.09
760
10 × 12,5
MVY(SMD)
35
220
0.15
670
Nichicon UWG (SMD)
35
330
0.15
Sanyo Os-Con SP (SMD
20
180
TDK X7R Ceramic
25
2.2
Murata X7R Ceramic
25
Kemet X7R Ceramic
CAPACITOR VENDOR/
COMPONENT
SERIES
PHYSICAL
SIZE
(mm)
INPUT
BUS
OUTPUT
BUS
1
VENDOR
NUMBER
1
EEUFC1V331 (VI < 30 V)
1
(1)
1
EEVFK1H331Q
1
(1)
2
LXZ35VB2231M10X12LL
(VI < 30 V)
10 × 10
1
2
MVY35VC221M10X10TP
(VI < 30 V)
670
10 × 10
1
1
UWG1V331MNR1GS
(VI < 30 V)
0.032
4280
10 ×10.5
2
0.002
>1000
3225
≥8
(2)
1
C3225X7R1E225KT/MT
(VO ≤ 20 V)
2.2
0.002
>1000
3225
≥8
(2)
1
GRM32RR71E225K
(VO ≤ 20 V)
25
2.2
0.002
>1000
3225
≥8
(2)
1
C1210C225K3RAC
(VO ≤ 20 V)
AVX X7R Ceramic
25
2.2
0.002
>1000
32225
≥8
(2)
1
C12103C225KAT2A
(VO ≤ 20 V)
Murata X7R Ceramic
50
4.7
0.002
>1000
3225
≥4
1
GRM32ER71H475KA88L
TDK X7R Ceramic
50
3.3
0.002
>1000
3225
≥6
1
CKG45NX7R1H335M
Murata Radial Through-hole
50
3.3
0.004
>1000
12,5 H x
12,5 W x
4D
≥6
1
RPER71H3R3KK6F03
Kemet Radial Through-hole
50
4.7
0.002
>1000
5,08 × 7,62
× 9,14 H
1
C350C475K5R5CA
(1)
(2)
(3)
(1)
≥4
(3)
≤2
20SP180M (VI~ VO ≤ 16 V)
The voltage rating of the input capacitor must be selected for the desired operating input voltage range of the regulator. To operate the
regulator at a higher input voltage, select a capacitor with the next higher voltage rating.
The maximum rating of the ceramic capacitor limits the regulator operating input voltage to 20 V. Select a alternative ceramic
component to operate at a higher input voltage.
A total capacitance of 2 µF is an acceptable replacement value for a single 2.2-µF ceramic capacitor
Output Voltage Sense
An external output voltage sense improves the load regulation performance of the module by enabling it to
compensate for any IR-voltage drop between the module and the load circuit. This voltage drop is caused by the
flow of current through the resistance in the printed-circuit board connections.
To use the output voltage sense feature, simply connect the VO Sense input (pin 5) to VO, close to the device
that draws the most supply current. If an external voltage sense is not desired, the VO Sense input may be left
open circuit. An internal resistor (15 Ω or less), connected between this input and VO, ensures that the output
remains in regulation.
With VO Sense connected, the difference between the voltage measured directly between the VO and GND, and
that measured from VO Sense to GND, represents the amount of IR-voltage drop being compensated by the
regulator. This should be limited to a maximum of 0.3 V.
Note: The external voltage sense is not designed to compensate for the forward drop of nonlinear or
frequency-dependent components that may be placed in series with the regulator's output. Examples include
OR-ing diodes, filter inductors, ferrite beads, and fuses. When these components are enclosed by the external
sense connection, they are effectively placed inside the regulation control loop. This can adversely affect the
stability of the module.
Undervoltage Lockout
The undervoltage lockout (UVLO) circuit prevents the module from attempting to power up until the input voltage
is above the UVLO threshold. This is to prevent the module from drawing excessive current from the input source
at power up. Below the UVLO threshold, the module is held off.
16
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PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
www.ti.com
Power-Up Characteristics
When configured per the standard application, the PTN78020 power module produces a regulated output voltage
following the application of a valid input source voltage. During power up, internal soft-start circuitry slows the
rate that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input
source. The soft-start circuitry introduces a short time delay (typically 5 ms – 10 ms) into the power-up
characteristic. This is from the point that a valid input source is recognized. Figure 26 shows the power-up
waveforms for a PTN78020W, operating from a 12-V input and with the output voltage adjusted to 5 V. The
waveforms were measured with a 1.5-A resistive load.
VI (5 V/div)
VO (2 V/div)
II (2 A/div)
t - Time = 5 ms/div
Figure 26. Power-Up Waveforms
Current-Limit Protection
The PTN78020 modules protect against load faults with a continuous current limit characteristic. Under a load
fault condition, the output current cannot exceed the current limit value. Attempting to draw current that exceeds
the current-limit value causes the module to progressively reduce its output voltage. Current is continuously
supplied to the fault until it is removed. On removal of the fault, the output voltage promptly recovers. When
limiting output current, the regulator experiences higher power dissipation, which increases its temperature. If the
temperature increase is excessive, the module overtemperature protection begins to periodically turn the output
voltage completely off.
Overtemperature Protection
A thermal shutdown mechanism protects the module's internal circuitry against excessively high temperatures. A
rise in temperature may be the result of a drop in airflow, a high ambient temperature, or a sustained current limit
condition. If the junction temperature of the internal control IC rises excessively, the module turns itself off,
reducing the output voltage to zero. The module instantly restarts when the sensed temperature decreases by a
few degrees.
Overtemperature protection is a last resort mechanism to prevent damage to the module. It should not be relied
on as permanent protection against thermal stress. Always operate the module within its temperature derated
limits, for the worst-case operating conditions of output current, ambient temperature, and airflow. Operating the
module above these limits, albeit below the thermal shutdown temperature, reduces the long-term reliability of
the module.
Copyright © 2004–2011, Texas Instruments Incorporated
Product Folder Link(s): PTN78020W PTN78020H
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17
PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
www.ti.com
Output On/Off Inhibit
For applications requiring output voltage on/off control, the PTN78020 power module incorporates an output
on/off Inhibit control (pin 3). The inhibit feature can be used wherever there is a requirement for the output
voltage from the regulator to be turned off.
The power module functions normally when the Inhibit pin is left open-circuit, providing a regulated output
whenever a valid source voltage is connected to VI with respect to GND. Figure 27 shows the the circuit used to
demonstrate the inhibit function. Note the discrete transistor (Q1). Turning Q1 on applies a low voltage to the
Inhibit control pin and turns the module off. The output voltage decays as the load circuit discharges the
capacitance. The current drawn at the input is reduced to typically 17 mA. If Q1 is then turned off, the module
executes a soft-start power up. A regulated output voltage is produced within 20 ms. Figure 28 shows the typical
rise in the output voltage, following the turn off of Q1. The turn off of Q1 corresponds to the fall in the waveform,
Q1 Vgs. The waveforms were measured with a 1.5-A resistive load.
5
Sense
VI = 12 V
2
VI
PTN78020
Inhibit
CI
2.2 mF
(Ceramic)
Q1
Inhibit
3
GND
1
VO = 5 V
6
VO
Adjust
7
4
RSET
21 k
0.05 W
1%
+
CO
330 mF
L
O
A
D
BSS 138
GND
GND
Figure 27. On/Off Inhibit Control Circuit
VO (2 V/div)
II (2 A/div)
Q1 VGS (10 V/div)
t - Time = 5 ms/div
Figure 28. Power Up Response From Inhibit Control
18
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Product Folder Link(s): PTN78020W PTN78020H
PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
www.ti.com
Optional Input/Output Filters
Power modules include internal input and output ceramic capacitors in all of their designs. However, some
applications require much lower levels of either input reflected or output ripple/noise. This application describes
various filters and design techniques found to be successful in reducing both input and output ripple/noise.
Input/Output Capacitors
The easiest way to reduce output ripple and noise is to add one or more 1-μF ceramic capacitors, such as C4
shown in Figure 29. Ceramic capacitors should be placed close to the output power terminals. A single 1-μF
capacitor reduces the output ripple/noise by 10% to 30% for modules with a rated output current of less than 3 A.
(Note: C3 is required to improve the regulator transient response, and does not reduce output ripple and noise.)
Switching regulators draw current from the input line in pulses at their operating frequency. The amount of
reflected (input) ripple/noise generated is directly proportional to the equivalent source impedance of the power
source including the impedance of any input lines. The addition of C1, minimum 2.2-μF ceramic capacitor, near
the input power pins, reduces reflected conducted ripple/noise by 30% to 50%.
5
Sense
2
VI
PTN78020W
VI
Inhibit
C1
1 µF
50 V
Ceramic
(1)
C2
2.2 µF
50 V
Ceramic
(Required)
3
GND
VO
6
VO
Adjust
+
1
7
4
(2)
RSET
(1)
C3
330 µF
(Required)
GND
C4
1 µF
Ceramic
GND
UDG−06049
(1)
See the specifications for required value and type. For the PTN78020H, C2 = 4 × 4.7 μF.
(2)
See the Application Information section for suggeted value and type.
Figure 29. Adding High-Frequency Bypass Capacitors To The Input and Output
π Filters
If a further reduction in ripple/noise level is required for an application, higher order filters must be used. A π (pi)
filter, employing a ferrite bead (Fair-Rite part number 2773021447 or equivalent) in series with the input or output
terminals of the regulator reduces the ripple/noise by at least 20 db (see Figure 30 and Figure 31). In order for
the inductor to be effective in reduction of ripple and noise, ceramic capacitors are required. (Note: see Capacitor
Recommendations for the PTN78020W for addtional information on vendors and component suggestions.)
These inductors plus ceramic capacitors form an excellent filter because of the rejection at the switching
frequency (650 kHz - 1 MHz). The placement of this filter is critical. It must be located as close as possible to the
input or output pins to be efffective. The ferrite bead is small (12.5 mm × 3 mm), easy to use, low cost, and has
low dc resistance. Fair-Rite also manufactures a surface mount bead (part number 2773021447), through hole
(part number 2673000701) rated to 5 A, but in this application, it is effective to 6 A on the output bus. 1-µH to
5-µH inductors can be used in place of the ferrite inductor bead.
Copyright © 2004–2011, Texas Instruments Incorporated
Product Folder Link(s): PTN78020W PTN78020H
Submit Documentation Feedback
19
PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
www.ti.com
5
Sense
L1
1−5 µH
2
VI
C1
2.2 µF
50 V
Ceramic
(1)
C3
2.2 µF
50 V
Ceramic
(Required)
C2
330 µF
50 V
(Optional)
Vo
PTN78020W
Inhibit GND GND
+
(4)
VI
3
1
Adjust
7
L2
1−5 µH
6
Vo
+
4
C4
330 µF
(Required)
(2)
RSET
GND
+
C5
1 µF
Ceramic
(3)
C6
100 µF
GND
UDG−06050
(1)
See the specifications for required value and type. For the PTN78020H, C3 = 4 × 4.7 μF.
(2)
See the Application Information section for suggeted value and type.
(3)
Recommended whenever IO > 2A.
(4)
For PTN78020H, C1 ≤ 4.7 μF.
Figure 30. Adding π Filters (IO ≤ 3 A)
45
40
Attenuation − dB
35
1 MHz
30
25
600 kHz
20
15
10
0
0.5
1
1.5
2
Load Current − A
2.5
3
Figure 31. π-Filter Attenuation vs. Load Current
20
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Product Folder Link(s): PTN78020W PTN78020H
PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
www.ti.com
5
L2
1 µH to 5 µH
Sense
L1
1 µH to 5 µH
VI
2
VI
Inhibit GND GND
C1
1 µF
50 V
Ceramic
(1)
3
1
Adjust
7
C3
2.2 µF
50 V
Ceramic
(Required)
C2
330 µF
50 V
(Optional)
VO
6
VO
PTN78020W
L3
1 µH to 5 µH
+
+
4
(1)
(2)
RSET
C4
330 µF
(Required)
GND
C5
1 µF
Ceramic
C6 (3)
100 µF
GND
UDG−05089
(1)
See the specifications for required value and type. For the PTN78020H, C2 = 4 × 4.7 μF.
(2)
See the Application Information section for suggeted value and type.
(3)
Recommended whenever IO > 2A.
(4)
For PTN78020H, C1 ≥ 4.7 μF.
Figure 32. Adding π Filters (IO = 3 A to 6 A)
Copyright © 2004–2011, Texas Instruments Incorporated
Product Folder Link(s): PTN78020W PTN78020H
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21
PTN78020W
PTN78020H
SLTS228C – DECEMBER 2004 – REVISED AUGUST 2011
www.ti.com
REVISION HISTORY
Changes from Revision B (APRIL 2008) to Revision C
•
22
Page
Added Output Voltage Sense section ............................................................................................................................... 16
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PTN78020HAH
ACTIVE
ThroughHole Module
EUK
7
20
Pb-Free
(RoHS)
SN
N / A for Pkg Type
-40 to 85
PTN78020HAS
ACTIVE
Surface
Mount Module
EUL
7
20
TBD
SNPB
Level-1-235C-UNLIM/
Level-3-260C-168HRS
-40 to 85
PTN78020HAZ
ACTIVE
Surface
Mount Module
EUL
7
20
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
-40 to 85
PTN78020WAD
ACTIVE
ThroughHole Module
EUK
7
20
Pb-Free
(RoHS)
SN
N / A for Pkg Type
-40 to 85
PTN78020WAH
ACTIVE
ThroughHole Module
EUK
7
20
Pb-Free
(RoHS)
SN
N / A for Pkg Type
-40 to 85
PTN78020WAS
ACTIVE
Surface
Mount Module
EUL
7
20
TBD
SNPB
Level-1-235C-UNLIM/
Level-3-260C-168HRS
-40 to 85
PTN78020WAZ
ACTIVE
Surface
Mount Module
EUL
7
20
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
-40 to 85
PTN78020WAZT
ACTIVE
Surface
Mount Module
EUL
7
200
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
27-Nov-2014
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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