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REF6025, REF6030, REF6033, REF6041, REF6045, REF6050
SBOS708B – MAY 2016 – REVISED AUGUST 2016
REF60xx High-Precision Voltage Reference With Integrated ADC Drive Buffer
1 Features
3 Description
•
The REF6000 family of voltage references have an
integrated low output impedance buffer that enable
the user to directly drive the REF pin of precision
data converters, while preserving linearity, distortion,
and noise performance. Most precision SAR and
Delta-Sigma ADCs, switch binary-weighted capacitors
onto the REF pin during the conversion process. In
order to support this dynamic load the output of the
voltage reference must be buffered with a low-output
impedance (high-bandwidth) buffer. The REF6000
family devices are well suited, but not limited, to drive
the REF pin of the ADS88xx family of SAR ADCs,
and ADS127xx family of delta-sigma ADCs, as well
as other digital-to-analog converters (DACs).
Excellent Temperature Drift Performance
– 5 ppm/°C (max) from –40°C to +125°C
Extremely Low Noise
– Total Noise: 5 µVRMS With 47-µF Capacitor
– 1/f Noise (0.1 Hz to 10 Hz): 3 µVPP/V
Integrated ADC Drive Buffer
– Low Output Impedance: < 50 mΩ (0-200 kHz)
– First Sample Precise to 18 Bits With ADS8881
– Enables Burst-Mode DAQ Systems
Low Supply Current: 820 μA
Low Shutdown Current: 1 µA
High Initial Accuracy: ±0.05%
Very-Low Noise and Distortion
– SNR: 100.5 dB, THD: –125 dB (ADS8881)
– SNR: 106 dB, THD: –120 dB (ADS127L01)
Output Current Drive: ±4 mA
Programmable Short-Circuit Current
Verified to Drive REF Pin of ADS88xx family of
SAR ADCs and ADS127xx family of Wideband ΔΣ
ADCs
1
•
•
•
•
•
•
•
•
•
The REF6000 family of voltage references are able to
maintain an output voltage within 1LSB (18-bit) with
minimal droop, even during the first conversion while
driving the REF pin of the ADS8881. This feature is
useful in burst-mode, event-triggered, equivalent-time
sampling, and variable-sampling-rate data-acquisition
systems. The REF60xx variants of REF6000 family
specify a maximum temperature drift of just 5 ppm/°C
and initial accuracy of 0.05% for both the voltage
reference and the low output impedance buffer
combined. For various temperature drift options in
REF6000 family, see the Device Comparison Table.
2 Applications
•
•
•
•
•
Device Information(1)
ATE Testers and Oscilloscopes
Test and Measurement Equipment
Analog Input Modules for PLCs
Medical Equipment
Precision Data Acquisition Systems
PART NUMBER
REF60xx
Typical Application
Reference Droop comparison
(1 LSB = 19.07 µV, With ADS8881 at 1 MSPS)
RLIM
REF60xx
4
SS
OUT_S
VIN
3
+
RESR
GND_S
FILT
GND_F
CL
CFILT
R
Power Supply
R
RF
+
VIN
AINP
CF
THS4521
GND
2
1
0
±1
REF60xx Droop
±2
REF
±3
ADS8881
AINN
R
Regular Voltage Reference Droop
OUT_F
Buffer
RFILT
Bandgap
Voltage
Reference
Reference Droop (LSB)
EN
BODY SIZE (NOM)
3.00 mm x 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Power Supply
VIN
PACKAGE
VSSOP (8)
RF
±4
0
R
Copyright © 2016, Texas Instruments Incorporated
200
400
600
Time (µs)
800
1000
C042
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
REF6025, REF6030, REF6033, REF6041, REF6045, REF6050
SBOS708B – MAY 2016 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
7
Parameter Measurement Information ................ 14
8.1
8.2
8.3
8.4
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Typical Characteristics ..............................................
Solder Heat Shift.....................................................
Thermal Hysteresis .................................................
Reference Droop Measurements ............................
1/f Noise Performance ............................................
14
15
16
18
Detailed Description ............................................ 19
9.1 Overview ................................................................. 19
9.2 Functional Block Diagram ....................................... 19
9.3 Feature Description................................................. 20
9.4 Device Functional Modes........................................ 23
10 Applications and Implementation...................... 24
10.1 Application Information.......................................... 24
10.2 Typical Application ................................................ 24
11 Power Supply Recommendations ..................... 27
12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
12.2 Layout Example .................................................... 28
13 Device and Documentation Support ................. 29
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
30
14 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
Changes from Revision A (June 2016) to Revision B
Page
•
Changed the Description ....................................................................................................................................................... 1
•
Changed the Device Comparison Table ............................................................................................................................... 3
•
Changed list of devices for output current in Recommended Operating Conditions ............................................................ 4
•
Changed load regulation max value for REF6050 at TA = –40°C to +125°C from 30 to 50 .................................................. 5
•
Changed "second pass" to "final pass" in last paragraph of Solder Heat Shift section ...................................................... 14
•
Added link to SLYY097 in Overview section ........................................................................................................................ 19
Changes from Original (May 2016) to Revision A
•
2
Page
Changed from product preview to production data ................................................................................................................ 1
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
5 Device Comparison Table
DEVICE FAMILY
TEMPERATURE DRIFT
REF60xx
5 ppm/°C from –40 to 125°C
REF61xx
8 ppm/°C from –40 to 125°C
REF62xx
3 ppm/°C from 0 to 70°C
6 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
VIN
1
8
GND_S
EN
2
7
GND_F
SS
3
6
OUT_F
FILT
4
5
OUT_S
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
EN
2
Input
FILT
4
—
GND_F
7
Ground
Ground force pin
GND_S
8
Ground
Ground sense pin
OUT_F
6
Output
Output voltage force pin
OUT_S
5
Input
Output voltage sense pin
SS
3
—
VIN
1
Power
Copyright © 2016, Texas Instruments Incorporated
Enable pin
Filter capacitor pin. A capacitor (CFILT) ≥ 1 µF must be connected between the FILT pin and
ground for stability.
Short circuit current limit pin. Connect a resistor to this pin to set the output short-circuit current
limit. Connect to VIN pin for highest current limit
Input supply voltage pin
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REF6025, REF6030, REF6033, REF6041, REF6045, REF6050
SBOS708B – MAY 2016 – REVISED AUGUST 2016
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Input voltage
MIN
MAX
UNIT
VIN
–0.3
6
V
VEN
–0.3
VIN + 0.3
V
–55
150
°C
150
°C
150
°C
Operating temperature, TA
Junction temperature, Tj
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
REF6025
Supply input voltage
(IOUT = 0 mA)
VIN
VEN
Output current
TA
MAX
3
5.5
VOUT + 0.25
5.5
REF6050
5.3
5.5
0
VIN
REF6025, REF6030, REF6033, REF6041
–4
4
REF6045
–3.5
3.5
REF6050
–3
3
REF6030, REF6033, REF6041, REF6045
Enable voltage
IL
NOM
Operating temperature
–40
25
125
UNIT
V
V
mA
°C
7.4 Thermal Information
REF60xx
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
158.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.2
°C/W
RθJB
Junction-to-board thermal resistance
79.5
°C/W
ψJT
Junction-to-top characterization parameter
5.2
°C/W
ψJB
Junction-to-board characterization parameter
78.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5
SBOS708B – MAY 2016 – REVISED AUGUST 2016
Electrical Characteristics
at TA = 25°C, VIN = 5 V for all devices except REF6050, VIN = 5.4 V for REF6050, IL = 0 mA, CL = 22 µF, CFILT = 1 µF, and
VEN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy
-0.05%
0.05%
Output voltage temperature
coefficient (1)
5
ppm/°C
LINE AND LOAD REGULATION
REF6025
ΔVO(ΔVI)
ΔVO(ΔIL)
ISC
Line regulation
Load regulation, sourcing and sinking
Short-circuit current
VOUT + 0.5 V ≤ VIN ≤ 5.5 V
TA = 25°C
4
TA = –40°C to +125°C
REF6030,
REF6033,
REF6041,
REF6045
VOUT + 0.25 V ≤ VIN ≤ 5.5 V
REF6050
VOUT + 0.3 V ≤ VIN ≤ 5.5 V
REF6025,
REF6030,
REF6033,
REF6041
IL = 0 mA to 4 mA,
VIN = VOUT + 600 mV
REF6045
IL = 0 mA to 3.5 mA,
VIN = VOUT + 600 mV
TA = 25°C
REF6050
IL = 0 mA to 3 mA,
VIN = VOUT + 400 mV
TA = 25°C
20
30
TA = 25°C
4
TA = –40°C to +125°C
20
ppm/V
30
TA = 25°C
7
TA = –40°C to +125°C
60
120
TA = 25°C
2
TA = –40°C to +125°C
20
30
2
TA = –40°C to +125°C
20
ppm/mA
30
2
TA = –40°C to +125°C
20
50
SS = open
10.5
mA
CL = 22 µF
5
CL = 47 µF
5
0.1 Hz ≤ f ≤ 10 Hz
3
µVPP/V
50
mΩ
100
ms
NOISE
Total integrated noise
Low frequency noise
µVRMS
OUTPUT IMPEDANCE
Output impedance
f = DC to 200 kHz, CL= 47 μF
TURN-ON TIME
ton
Turn-on time
0.1% settling, CL = 47 µF, SS = open, REF6025
HYSTERESIS AND LONG TERM DRIFT
Long term stability
Output voltage hysteresis (2)
0 to 1000h at 25°C
80
1000h to 2000h at 25°C
20
25°C, –40°C,125°C, 25°C (cycle 1)
33
25°C, –40°C,125°C, 25°C (cycle 2)
8
ppm
ppm
CAPACITIVE LOAD
CL
(1)
(2)
Stable output capacitor value
10
47
µF
Temperature drift is specified according to the box method. See the Feature Description section for more details.
See the Thermal Hysteresis section.
Copyright © 2016, Texas Instruments Incorporated
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
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Electrical Characteristics (continued)
at TA = 25°C, VIN = 5 V for all devices except REF6050, VIN = 5.4 V for REF6050, IL = 0 mA, CL = 22 µF, CFILT = 1 µF, and
VEN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT VOLTAGE
REF6025
VOUT
Output voltage
2.5
REF6030
3
REF6033
3.3
REF6041
4.096
REF6045
4.5
REF6050
5
V
POWER SUPPLY
REF6025,
REF6030,
REF6033,
REF6041
ICC
Supply current
REF6045,
REF6050
TA = 25°C
Active mode, VEN = 5 V
Active mode, VEN = 5 V
Shutdown mode, VEN = 0 V
TA = 25°C
0.83
TA = –40°C to +125°C
REF6030, REF6033, REF6041
Dropout voltage
REF6045
REF6050
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mA
0.95
1.15
TA = 25°C
1
TA = –40°C to +125°C
3
15
1.6
0.6
VEN = 5 V
REF6025
0.90
1.1
Voltage reference in shutdown mode (EN = 0)
Enable pin current
6
TA = –40°C to +125°C
Voltage reference in active mode (EN = 1)
Enable pin voltage
0.82
IL = 0 mA
100
150
500
500
IL = 4 mA
µA
V
nA
600
IL = 0 mA
50
IL = 4 mA
250
600
IL = 0 mA
50
IL = 3.5 mA
250
mV
600
IL = 0 mA
100
IL = 3 mA
300
400
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REF6025, REF6030, REF6033, REF6041, REF6045, REF6050
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
7.6 Typical Characteristics
100
100
90
90
80
80
70
70
Population (%)
Population (%)
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6025 (unless otherwise noted)
60
50
40
30
60
50
40
30
20
20
10
10
0
0
1
2
3
4
0
5
0
1
Drift Distribution (ppm/ºC)
2
3
4
5
Drift Distribution (ppm/ºC)
C002
C003
TA = –40°C to +125°C
TA = –40°C to +85°C
Figure 1. Drift Distribution
Figure 2. Drift Distribution
100
40
90
30
70
Population (%)
Population (%)
80
60
50
40
30
20
10
20
C005
Initial Accuracy (%)
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
0
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.05
0
-0.04
10
C004
Solder Heat Shift (%)
Figure 3. Initial Accuracy Distribution
Figure 4. Solder-Heat Shift Distribution
0.05
250
0.03
Dropout Voltage (mV)
Output Voltage Accuracy (%)
0.04
0.02
0.01
0
-0.01
-0.02
90ƒC
200
125ƒC
150
100
25ƒC
50
-0.03
-40ƒC
-0.04
0
-0.05
±50
±25
0
25
50
Temperature (ºC)
75
100
125
C001
Figure 5. Output Voltage Accuracy vs Temperature
Copyright © 2016, Texas Instruments Incorporated
±4
±3
±2
±1
0
1
2
3
Load Current (mA)
4
C017
Figure 6. Dropout Voltage vs Load Current
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
www.ti.com
Typical Characteristics (continued)
14
14
12
12
Load Regulation (ppm/mA)
Load Regulation (ppm/mA)
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6025 (unless otherwise noted)
10
8
6
4
2
10
8
6
4
2
0
0
±50
0
±25
25
50
75
100
Temperature (ºC)
125
±50
±25
0
25
50
75
100
Temperature (ºC)
C006
VIN = VOUT + 600 mV,
IL = 0 mA to 4 mA
125
C007
VIN = VOUT + 600 mV,
IL = 0 mA to 4 mA
Figure 7. Load Regulation Sourcing vs Temperature
Figure 8. Load Regulation Sinking vs Temperature
1000
8
6
Supply Current (µA)
Line Regulation (ppm/V)
950
4
2
900
850
800
750
700
650
0
±50
0
±25
25
50
75
100
Temperature (ºC)
±50
125
±25
0
25
50
75
100
Temperature (ƒC)
C01
125
C019
VOUT + 0.25 V ≤ VIN ≤ 5.5 V
Figure 9. Line Regulation vs Temperature
Figure 10. Supply Current vs Temperature
870
Supply Current (µA)
850
830
EN
810
2 V/div
790
VREF
770
750
2
3
4
5
Input Voltage (V)
Figure 11. Supply Current vs Input Voltage
8
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6
Time (100 ms/div)
C020
C018
Figure 12. Turn-On Settling Time
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
Typical Characteristics (continued)
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6025 (unless otherwise noted)
Voltage (2 µV/div)
2XWSXW 1RLVH 6SHFWUDO 'HQVLW\ Q9 ¥+]
25
Time (2 s/div)
20
15
10 µF
10
22 µF
47 µF
5
0
1k
10k
±60
25
CL = 47 µF
±80
CL = 22 µF
±90
1000k
C022
Figure 14. Output-Voltage Noise Spectrum
30
Output Impedance (mŸ)
Power Supply Rejection Ratio (dB)
Figure 13. 0.1-Hz to 10-Hz Noise
±50
±70
100k
Frequency (Hz)
C021
20
15
10 µF
10
22 µF
47 µF
5
±100
0
±110
10
100
1k
10k
Frequency (Hz)
100
100k
1k
10k
C011
100k
1M
Frequency (Hz)
C025
Graph obtained by design simulation
Figure 15. PSRR vs Frequency
Figure 16. Output Impedance vs Frequency
VOUT
VOUT
50 mV/div
2 mV/div
+1 mA
2 mA/div
+3 mA
6 mA/div
-1 mA
-1 mA
Time (0.5 ms/div)
0
C014
Load current = ±1 mA
Figure 17. Load Transient Response
Copyright © 2016, Texas Instruments Incorporated
-3 mA
-3 mA
5
10
Time (5 ms/div)
15
C015
Load current = ±3 mA
Figure 18. Load Transient Response
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Typical Characteristics (continued)
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6025 (unless otherwise noted)
50
VIN - 0.25 V
VIN - 0.25 V
40
Population (%)
500 mV/div
VIN + 0.25 V
VREF
30
20
200 µV/div
10
0
Time (500 µs/div)
-80
-60
-40
-20
0
20
40
60
Thermal hysteresis - Cycle 1 (ppm)
C013
C030
Figure 19. Line Transient Response
100
40
10
Output Impedance (Ÿ)
Population (%)
Figure 20. Thermal Hysteresis Distribution (Cycle 1)
50
30
20
REF20xx (CL = 10 µF)
1
REF60xx (CL = 10 µF)
0.1
0.01
10
0
-20
-15
-10
-5
0
5
15
0.001
20
100
1k
Thermal hysteresis - Cycle 2 (ppm)
10k
100k
Frequency (Hz)
1M
C063
C031
0
±20
±20
±40
±40
±60
±60
±80
±100
±120
±80
±100
±120
±140
±140
±160
±160
±180
±180
±200
±200
0
100
200
300
400
Frequency (kHz)
fIN
REF6050 driving REF pin of ADS8881,
= 1 kHz, SNR = 100.5 dB, THD = –125.9 dB
Figure 23. Typical FFT Plot
10
Figure 22. Output Impedance Comparison
0
Amplitude (dB)
Amplitude (dB)
Figure 21. Thermal Hysteresis Distribution (Cycle 2)
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500
0
100
200
300
400
Frequency (kHz)
C024
fIN
500
C037
REF6050 driving REF pin of ADS8881,
= 2 kHz, SNR = 100.4 dB, THD = –123.9 dB
Figure 24. Typical FFT Plot
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
Typical Characteristics (continued)
0
0
±20
±20
±40
±40
±60
±60
Amplitude (dB)
Amplitude (dB)
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6025 (unless otherwise noted)
±80
±100
±120
±80
±100
±120
±140
±140
±160
±160
±180
±180
±200
±200
0
100
200
300
400
Frequency (kHz)
fIN
500
0
REF6050 driving REF pin of ADS8881,
= 10 kHz, SNR = 99.2 dB, THD = –119.4 dB
300
400
500
C030
REF6041 driving REF pin of ADS8881,
fIN = 1 kHz, SNR = 99 dB, THD = –124.4 dB
Figure 26. Typical FFT Plot
0
0
±20
±20
±40
±40
±60
±60
Amplitude (dB)
Amplitude (dB)
200
Frequency (kHz)
Figure 25. Typical FFT Plot
±80
±100
±120
±80
±100
±120
±140
±140
±160
±160
±180
±180
±200
±200
0
100
200
300
400
Frequency (kHz)
0
500
100
200
300
400
Frequency (kHz)
C031
REF6041 driving REF pin of ADS8881,
fIN = 2 kHz, SNR = 99 dB, THD = –123.6 dB
fIN
Figure 27. Typical FFT Plot
500
C032
REF6041 driving REF pin of ADS8881,
= 10 kHz, SNR = 97.2 dB, THD = –119.7 dB
Figure 28. Typical FFT Plot
0
0
±20
±20
±40
±40
±60
±60
Amplitude (dB)
Amplitude (dB)
100
C038
±80
±100
±120
±80
±100
±120
±140
±140
±160
±160
±180
±180
±200
±200
0
100
200
300
400
Frequency (kHz)
REF6025 driving REF pin of ADS8881,
fIN = 1 kHz, SNR = 95.4 dB, THD = –124 dB
Figure 29. Typical FFT Plot
Copyright © 2016, Texas Instruments Incorporated
500
0
100
200
300
400
Frequency (kHz)
C033
fIN
500
C034
REF6025 driving REF pin of ADS8881,
= 2 kHz, SNR = 95.4 dB, THD = –123.5 dB
Figure 30. Typical FFT Plot
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Typical Characteristics (continued)
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6025 (unless otherwise noted)
121410
0
±20
121409
±60
ADC Code
Amplitude (dB)
±40
±80
±100
±120
121408
121407
±140
121406
±160
±180
121405
±200
0
100
200
300
400
Frequency (kHz)
60
80
C047
Figure 32. Reference Droop
±121335
±132
ADC Code
±131
±121336
±121337
±133
±134
±135
±121338
±136
±121339
20
40
60
80
Time (µs)
0
100
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
negative full-scale input to ADS8881
20
40
60
80
Time (µs)
C048
C049
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
AINP = AINN = VREF / 2 for ADS8881
Figure 33. Reference Droop
Figure 34. Reference Droop
40
30
30
Hits per Code (%)
40
20
20
10
0
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
10
ADC Output Code
ADC Output Code
C050
C051
AINP = AINN = VREF / 2 for ADS8881,
sampling rate = 1 MSPS
AINP = AINN = VREF / 2 for ADS8881,
sampling rate = 500 kSPS
Figure 35. DC Input Histogram
Figure 36. DC Input Histogram
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100
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
0
12
100
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
positive full-scale input to ADS8881
±121334
Hits per Code (%)
40
Time (µs)
Figure 31. Typical FFT Plot
ADC Code
20
C035
REF6025 driving REF pin of ADS8881,
= 10 kHz, SNR = 94.0 dB, THD = –119.3 dB
fIN
0
500
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: REF6025 REF6030 REF6033 REF6041 REF6045 REF6050
REF6025, REF6030, REF6033, REF6041, REF6045, REF6050
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
Typical Characteristics (continued)
40
30
30
20
20
10
10
0
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Hits per Code (%)
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Hits per Code (%)
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6025 (unless otherwise noted)
ADC Output Code
ADC Output Code
C052
C053
AINP = AINN = VREF / 2 for ADS8881,
sampling rate = 100 kSPS
AINP = AINN = VREF / 2 for ADS8881,
sampling rate = 20 kSPS
Figure 37. DC Input Histogram
Figure 38. DC Input Histogram
4
Reference Droop (LSB)
3
Regular Voltage Reference Droop
2
1
0
±1
REF60xx Droop
±2
±3
±4
0
200
400
600
800
Time (µs)
1000
C042
1 LSB = 19.07 µV, with ADS8881 at 1 MSPS
Figure 39. Reference Droop Comparison
Copyright © 2016, Texas Instruments Incorporated
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8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF60xx have differing coefficients of thermal expansion, and
result in stress on the device die when the part is heated. Mechanical and thermal stress on the device die
sometimes causes the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow
soldering is a common cause of this error.
In order to illustrate this effect, a total of 128 devices were soldered on eight printed circuit boards (PCBs), with
16 devices on each PCB, using lead-free solder paste, and the manufacturer-suggested reflow profile. The reflow
profile is as shown in Figure 40. The printed circuit board is comprised of FR4 material. The board thickness is
1.65 mm and the area is 101.6 mm × 127 mm.
The reference output voltage is measured before and after the reflow process; the typical shift is displayed in
Figure 41. Although all tested units exhibit very low shifts (< 0.03%), higher shifts are also possible depending on
the size, thickness, and material of the PCB.
The histogram displays the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is
common on PCBs with surface-mount components on both sides, causes additional shifts in the output bias
voltage. If the PCB is exposed to multiple reflows, solder the device in the final pass to minimize exposure to
thermal stress.
40
300
250
Population (%)
Temperature (ƒC)
30
200
150
100
20
10
Time (seconds)
Figure 40. Reflow Profile
14
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400
C01
0
Solder Heat Shift (%)
0.05
350
0.04
300
0.03
250
0.02
200
0.01
150
-0.01
100
-0.02
50
-0.03
0
-0.04
0
0
-0.05
50
C004
Figure 41. Solder Heat Shift Distribution
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
8.2 Thermal Hysteresis
Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C,
cycling the device through the specified temperature range, and returning to 25°C. Thermal hysteresis was
measured with the REF60xx soldered to a PCB, similar to a real-world application. The PCB was baked at 150°C
for 30 minutes before thermal hysteresis was measured. Thermal hysteresis is expressed as:
§ VPRE VPOST ·
6
VHYST
¨¨
¸¸ x 10 (ppm)
V
NOM
©
¹
where
•
•
•
•
VHYST = thermal hysteresis (in units of ppm).
VNOM = the specified output voltage.
VPRE = output voltage measured at 25°C pretemperature cycling.
VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature
range of –40°C to 125°C and returns to 25°C.
(1)
50
50
40
40
Population (%)
Population (%)
Typical thermal hysteresis distribution is shown in Figure 42 and Figure 43.
30
20
10
0
30
20
10
-80
-60
-40
-20
0
20
40
0
60
Thermal hysteresis - Cycle 1 (ppm)
-20
-15
-10
-5
0
5
15
20
Thermal hysteresis - Cycle 2 (ppm)
C030
Figure 42. Thermal Hysteresis Distribution (Cycle 1)
Copyright © 2016, Texas Instruments Incorporated
C031
Figure 43. Thermal Hysteresis Distribution (Cycle 2)
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8.3 Reference Droop Measurements
121410
±121334
121409
±121335
121408
±121336
ADC Code
ADC Code
Many applications, such as event-triggered and multiplexed data-acquisition systems, require the very first
conversion of the ADC to have 18-bit or greater precision. These types of data-acquisition systems capture data
in bursts, and are also called burst-mode, data-acquisition systems. Achieving 18-bit precision for the first sample
is a very difficult using a conventional voltage reference because the voltage reference droop limits the accuracy
of the first few conversions. The REF60xx have an integrated ADC drive buffer that makes sure the reference
droop is less than 1 LSB at 18-bit precision when used with the ADS8881, even at full throughput. Figure 44 and
Figure 45 show the REF60xx output voltage droop when driving the REF pin of the ADS8881 at positive and
negative full-scale inputs, respectively.
121407
121406
±121337
±121338
121405
0
20
40
60
80
Time (µs)
100
C047
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
positive full-scale input to ADS8881
Figure 44. Output Voltage Droop
±121339
0
20
40
60
80
Time (µs)
100
C048
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
negative full-scale input to ADS8881
Figure 45. Output Voltage Droop
Direct measurement of the reference droop to 18-bit accuracy can be a challenging process. Therefore, the plots
in Figure 44 and Figure 45 were obtained by processing the output code of the ADC. The ADC output code is
given by:
C = (Input Voltage / VREF) × 2N
(2)
If the input voltage is kept constant, VREF is computed by monitoring the ADC output code C. The ADC code
usually has six to seven LSBs of code spread due to the inherent noise of the ADC. In order to measure
reference droop, this noise must be reduced drastically. Noise reduction is done by averaging the output code
multiple times, as described in the next paragraph.
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
Reference Droop Measurements (continued)
Figure 46 shows the setup that was used to measure the reference droop. The output ADC code was captured
using a field-programmable gate array (FPGA), and post-processing was done on a personal computer. The
input to the THS4521, and hence in turn to the ADS8881, is a constant dc voltage (close to positive or negative
full-scale because this condition is the worst-case for charge drawn from the REF pin). The dc source must have
extremely low noise. After the REF60xx device is powered up and stable, the FPGA sends commands to the
ADS8881 to capture data in bursts. The ADS8881 is initially in idle mode for 100 ms. The FPGA then sends a
command to the ADS8881 to perform 100 conversions at 1 MSPS. The ADC code corresponding to these 100
conversions (one burst of data) is stored as the first row in a 1000 × 100 dimensional array. This operation is
repeated 1000 times, and the data corresponding to each burst is stored in a new row of the 1000 × 100
dimensional array. Finally, each column in this array is averaged to get a final data-set of 100 elements. This
final data-set now has code spread that is much less than 1 LSB because most of the noise has now been
removed through averaging. This data-set was plotted on a graph with X axis = column number (each column
number corresponds to 1 µs of time because the sampling rate is 1 MSPS), and Y axis = ADC output code to
obtain reference-droop measurements.
Power Supply
RLIM = 120 NŸ
VIN
REF60xx
SS
OUT_S
VIN
EN
Bandgap
Voltage
Reference
GND_S
Buffer
RFILT
OUT_F
+
RESR = 5 PŸ
FILT
GND_F
CL = 47 µF
CFILT = 1 µF
R = 1 NŸ
Power Supply
R = 1 NŸ
RF = 5 Ÿ
+
VIN
THS4521
AINP
GND
CF = 10 nF
REF
ADS8881
AINN
R = 1 NŸ
RF = 5 Ÿ
Copyright © 2016, Texas Instruments Incorporated
R = 1 NŸ
Figure 46. Burst-Mode Measurement Setup
Copyright © 2016, Texas Instruments Incorporated
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8.4 1/f Noise Performance
Voltage (2 µV/div)
Typical 0.1-Hz to 10-Hz voltage noise for the REF6025 is shown in Figure 47. The 1/f noise scales with output
voltage, but remains 3 µVPP/V for all the variants. Peak-to-peak noise measurement setup is shown in Figure 48.
Time (2 s/div)
C021
Figure 47. 0.1-Hz to 10-Hz Noise
10 k
100
40 mF
VIN
+
EN
Power
Supply
To Scope
OUT_F
REF60xx
OUT_S
0.1 F
GND
GND_F
1k
22 F
2-Pole High-Pass
4-Pole Low-Pass
0.1-Hz to 10-Hz Filter
GND_S
Copyright © 2016, Texas Instruments Incorporated
Figure 48. 0.1-Hz to 10-Hz Noise Measurement Setup
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9 Detailed Description
9.1 Overview
Most SAR ADCs, and a few delta-sigma ADCs, switch binary-weighted capacitors onto the REF pin during the
conversion process. The magnitude of the capacitance switched onto the REF pin during each conversion
depends on the input signal to the ADC. If a voltage reference is directly connected to the REF pin of these
ADCs, the reference voltage droops because of the dynamic input signal dependent load of the binary-weighted
capacitors. Because the reference voltage droop now has input signal dependance, significant degradation in
THD and linearity for the system occurs.
In order to support this dynamic load and preserve the ADC linearity, distortion and noise performance, the
output of the voltage reference must be buffered with a low-output impedance (high-bandwidth) buffer. The
REF60xx family of voltage references have an integrated low output impedance buffer that enables the user to
directly drive the REF pin of a SAR ADC, while preserving ADC linearity and distortion. In addition, the total noise
in the full bandwidth of the REF60xx is extremely low, thus preserving the noise performance of the ADC.
Voltage-Reference Impact on Total Harmonic Distortion (SLYY097) correlates the effect of reference settling to
ADC distortion, and how the REF60xx achieves lowest distortion with minimal components and lowest power
consumption.
The output voltage of the REF60xx does not droop below 1 LSB (18-bit), even during the first conversion while
driving the REF pin of the ADS8881. This feature is useful in burst-mode, event-triggered, equivalent-time
sampling, and variable-sampling-rate data-acquisition systems. Functional Block Diagram shows a simplified
schematic of the REF60xx.
9.2 Functional Block Diagram
SS
VIN
OUT_S
VIN
EN
Bandgap
Voltage
Reference
GND_S
Copyright © 2016, Texas Instruments Incorporated
Buffer
RFILT
OUT_F
+
FILT
GND_F
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9.3 Feature Description
9.3.1 Integrated ADC Drive Buffer
Many ADC data sheets specify a few microamps of average current draw from the REF pin. Almost all voltage
references provide these few microamps of average current; but not all voltage references are practical for
driving a high-resolution, high-throughput SAR ADC because the peak current drawn can be very high when the
capacitors are switched on the REF pin. The worst-case demand for the voltage reference is during a burst-mode
conversion, when the ADC is idle for a very long time, before a conversion is initiated, and the first sample
converted is expected to be precise. Usually, a large capacitor is connected between the REF pin and ground pin
(or sometimes between the REFP and REFM pins) of the ADC to smoothen the current load and reduce the
burden on the voltage reference. The voltage reference must then be capable of providing the average current
required to completely charge the reference capacitor, but without causing the reference voltage to droop
significantly. Most voltage references lack the ability to completely charge the reference capacitor, and settle
when the binary-weighted capacitors are being switched onto the REF pin because of the large output
impedance. Usually, voltage references have output impedances in the range of 10's of ohms at frequencies
higher than 100 Hz. The output voltage of the voltage reference must be buffered with a low output impedance
(usually high bandwidth) amplifier to achieve excellent linearity and distortion performance.
The key amplifier specifications to be considered when designing a reference buffer for a high-precision ADC
are: low offset, low drift, wide bandwidth, and low output impedance. While it is possible to select an amplifier
that sufficiently meets all these requirements, the amplifier comes at a cost of excessive power consumption. For
example, the OPA350 is a 38-MHz bandwidth amplifier with a maximum offset of 0.5 mV, and low offset drift of 4
µV/ºC, but consumes a quiescent current of 5.2mA. This is because (from an amplifier design perspective) offset
and drift are dc specifications, whereas bandwidth, low output impedance, and high capacitive drive capability
are high-frequency specifications. Therefore, achieving all the performance in one amplifier requires power.
However, a more efficient design to meet the low power budget is to use a composite reference buffer, which
uses an amplifier with superior high-frequency specifications in the feedback loop of a dc precision amplifier to
get the overall performance at much lower power consumption. Figure 49 shows such a composite amplifier
design with the OPA333 (dc precision amplifier) and THS4281 (high-bandwidth amplifier). This reference buffer
design requires three devices, and a large number of external components. This solution still consumes close to
2 mA of quiescent current.
VDD
5-V Power Supply
VIN
Temp
VDD
1 NŸ
VOUT
+
1 NŸ
+
OPA333
REF5045
200 PŸ
Temp
THS4281
1 µF
GND
Trim
1 µF
10 µF
1 µF
1 µF
To REF pin
of ADC
20 NŸ
200 PŸ
10 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 49. Composite Amplifier Reference Buffer
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Feature Description (continued)
The REF60xx family of voltage references have an integrated low output impedance buffer (ADC drive buffer);
therefore, there is no need for an external buffer while driving the REF pin of high-precision, high-throughput
SAR ADCs, as shown in Figure 50. The ADC drive buffer of the REF60xx is capable of replenishing a charge of
70 pC on a 47-µF capacitor in 1 µs, without allowing the voltage on the capacitor to droop more than 1 LSB at
18-bit precision. The REF60xx are trimmed at multiple temperatures in production, achieving a max drift of just 5
ppm/°C for both the voltage reference and the buffer combined, while operating at a typical quiescent current of
820 µA. Figure 51 compares the output impedance of a regular voltage reference (REF20xx) and a voltage
reference with integrated ADC drive buffer (REF60xx). Figure 52 compares the burst-mode, reference-settling
performance of a regular voltage reference and the REF60xx.
Power Supply
RLIM = 120 NŸ
VIN
SS
REF60xx
OUT_S
VIN
EN
Buffer
RFILT
Bandgap
Voltage
Reference
OUT_F
+
RESR = 5 PŸ
GND_S
FILT
GND_F
CL = 47 µF
CFILT = 1 µF
R = 1 NŸ
Power Supply
R = 1 NŸ
RF = 5 Ÿ
+
VIN
AINP
THS4521
CF = 10 nF
REF
GND
ADS8881
AINN
R = 1 NŸ
RF = 5 Ÿ
Copyright © 2016, Texas Instruments Incorporated
R = 1 NŸ
Figure 50. REF60xx Driving REF Pin of ADS8881 SAR ADC
100
4
Reference Droop (LSB)
Output Impedance (Ÿ)
3
10
REF20xx (CL = 10 µF)
1
REF60xx (CL = 10 µF)
0.1
0.01
Regular Voltage Reference Droop
2
1
0
±1
REF60xx Droop
±2
±3
0.001
100
1k
10k
100k
Frequency (Hz)
1M
C063
±4
0
200
400
600
800
Time (µs)
1000
C042
1 LSB = 19.07 µV, with ADS8881 at 1 MSPS
Figure 51. Output Impedance Comparison
Copyright © 2016, Texas Instruments Incorporated
Figure 52. Reference Droop Comparison
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Feature Description (continued)
9.3.2 Temperature Drift
The REF60xx family is designed for minimal drift error, defined as the change in output voltage over temperature.
The drift is calculated using the box method, as described by the following equation:
V REF(MAX) V REF(MIN)
§
·
6
Drift ¨
¸ x 10 (ppm)
x
V
Temperature
Range
© REF
¹
(3)
9.3.3 Load Current
The REF6025, REF6030, REF6033 and REF6041 are specified to deliver current load of ±4 mA. The REF6045
is specified to deliver ±3.5 mA, and the REF6050 is specified to deliver ±3 mA. The REF60xx are protected from
short circuits at the output by limiting the output short-circuit current.
The short-circuit current limit (ISC) of the REF60xx family of devices is adjusted by connecting a resistor (RSS) on
the SS pin. The short-circuit current limit when the REF60xx device is sourcing current can be calculated as
shown in Equation 4:
ISC
(80 * 10 9 ) * RSS
(3 * 10 3 )
(4)
The short circuit current limit when the REF60xx device is sinking is calculated as shown in Equation 5:
ISC
(115 * 10
9
) * RSS
(4.6 * 10
3
)
(5)
The recommended output current of the REF60xx also depends on the resistor connected to the SS pin. The
recommended output current (sourcing and sinking) for the REF6025, REF6030, REF6033 and REF6041 is
given by Equation 6:
IL
(31.25 * 10 9 ) * RSS
(0.25 * 10 3 )
(6)
The recommended output current (sourcing and sinking) for the REF6045 is given by Equation 7:
IL
(27.08 * 10 9 ) * RSS
(0.25 * 10 3 )
(7)
The recommended output current (sourcing and sinking) for the REF6050 is given by Equation 8:
IL
(23.75 * 10 9 ) * RSS
(0.15 * 10 3 )
(8)
The temperature of the device increases according to Equation 9:
TJ TA PD ‡ R -$
where:
•
•
•
•
TJ = junction temperature (°C).
TA = ambient temperature (°C).
PD = power dissipated (W).
RθJA = junction-to-ambient thermal resistance (°C/W).
(9)
The REF60xx maximum junction temperature must not exceed the absolute maximum rating of 150°C.
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Feature Description (continued)
9.3.4 Stability
The REF60xx family of voltage references are stable with output capacitor values ranging from 10 µF to 47 µF.
At a low output-capacitor value of 10 µF, an effective series resistance (ESR) of 20 mΩ to 100 mΩ is required for
stability; whereas, at a higher value of 47 µF, an ESR of 5 mΩ to 100 mΩ is required. The shaded region in
Figure 53 shows the stable region of operation for the REF60xx devices.
120
ESR (PŸ)
100
80
60
40
20
10
20
30
40
50
Output Capacitor (µF)
Figure 53. Stable Output Capacitor Range
A capacitor of value 1 µF is required at the FILT pin for stability and noise performance. A low ESR (5 mΩ to 20
mΩ) is easily achieved by increasing the PCB trace length, thus eliminating the need for a discrete resistor.
Higher values of ESR (greater than 20 mΩ, but lesser than 100 mΩ) can be intentionally added to increase the
output bandwidth of the REF60xx. This higher ESR improves the transient performance of the REF60xx, but
worsens noise performance because of increased bandwidth.
9.4 Device Functional Modes
When the EN pin of the REF60xx is pulled high, the device is in active mode. The device must be in active mode
for normal operation.
To place the REF60xx into a shutdown mode, pull the ENABLE pin low. When in shutdown mode, the output of
the device becomes high impedance and the quiescent current of the device reduces to 1 µA (typ). See the
enable pin voltage parameter in the Electrical Characteristics table for logic high and logic low voltage levels.
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Many applications, such as event-triggered and multiplexed data-acquisition systems, require the very first
conversion of the ADC to have 18-bit or greater precision. These types of data acquisition systems capture data
in bursts, and are also called burst-mode, data-acquisition systems. Achieving 18-bit precision for the first sample
is very difficult using a conventional voltage reference because the voltage reference droop limits the accuracy of
the first few conversions. Furthermore, variable-sampling-rate systems require that the gain error of the system
does not vary with sampling rate. The primary objective of this design example is to demonstrate the lowest
distortion and noise, burst-mode data-acquisition block with low power consumption, using an 18-bit SAR ADC
operating at a throughput of 1 MSPS, for a 1-kHz, full-scale, pure sine-wave input.
10.2 Typical Application
Power Supply
RLIM = 120 NŸ
VIN
REF60xx
SS
OUT_S
VIN
EN
Bandgap
Voltage
Reference
GND_S
Buffer
RFILT
OUT_F
+
RESR = 5 PŸ
FILT
GND_F
CL = 47 µF
CFILT = 1 µF
R = 1 NŸ
Power Supply
R = 1 NŸ
RF = 5 Ÿ
+
VIN
THS4521
AINP
CF = 10 nF
GND
REF
ADS8881
AINN
R = 1 NŸ
RF = 5 Ÿ
Copyright © 2016, Texas Instruments Incorporated
R = 1 NŸ
Figure 54. 18-bit, 1-MSPS, Burst-Mode Data Acquisition system
10.2.1 Design Requirements
1.
2.
3.
4.
5.
24
Burst-mode support (see Reference Droop Measurements section for more details)
ENOB > 16 bits
THD < –120 dB
Power consumption < 50 mW
Throughput = 1 MSPS
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
Typical Application (continued)
10.2.2 Detailed Design Procedure
The data acquisition system shown in Figure 54 has three major contributors to the noise and accuracy in the
system: the input driver, the reference with driver, and the data converter. Each analog block is carefully
designed so that the data converter specifications limit the system specifications. The THS4551, a fully
differential operational amplifier is used to drive the 18-bit ADC (ADS8881). The charge-kickback RC filter at the
output of the THS4551 is used to reduce the charge kickback created by the opening and closing of the sampling
switch inside the ADC. Design the RC filter so that the voltage at the sampling capacitor settles to 18-bit
accuracy within the acquisition time of the ADC.
Data-acquisition systems require stable and accurate voltage references in order to perform the most accurate
data conversion. The REF60xx family of voltage references have integrated an ADC drive buffer, and can
therefore drive the REF pin of the ADS8881 directly, without the need for an external reference buffer. See the
Integrated ADC Drive Buffer section for more details about reference-buffer requirements. Correct output
capacitor selection for the REF60xx is very important in this design. The Stability section describes the ESR
requirements of the output capacitor for stability and burst-mode requirements. A capacitance of 1 μF is
connected to the FILT pin to reduce broadband noise of the REF60xx.
10.2.2.1 Results
Table 1 summarizes the measured results.
Table 1. Measured Results
SPECIFICATION
MEASURED RESULT
SNR
100.5 dB
ENOB
16.4
THD
–125.9 dB
Throughput
1 MSPS
Burst mode
First sample > 18-bit precision
Power consumption
40 mW
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0
0
±20
±20
±40
±40
±60
±60
Amplitude (dB)
Amplitude (dB)
10.2.3 Application Curves
±80
±100
±120
±80
±100
±120
±140
±140
±160
±160
±180
±180
±200
±200
0
100
200
300
400
Frequency (kHz)
fIN
0
500
100
200
300
400
Frequency (kHz)
C024
REF6050 driving REF pin of ADS8881,
= 1 kHz, SNR = 100.5 dB, THD = –125.9 dB
fIN
Figure 55. Typical FFT Plot
500
C037
REF6050 driving REF pin of ADS8881,
= 2 kHz, SNR = 100.4 dB, THD = –123.9 dB
Figure 56. Typical FFT Plot
0
±131
±20
±132
±60
ADC Code
Amplitude (dB)
±40
±80
±100
±120
±133
±134
±140
±160
±135
±180
±200
0
100
200
300
400
Frequency (kHz)
fIN
±136
500
0
REF6050 driving REF pin of ADS8881,
= 10 kHz, SNR = 99.2 dB, THD = –119.4 dB
60
80
100
C049
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
AINP = AINN = VREF / 2 for ADS8881
Figure 58. Reference Droop
121410
±121334
121409
±121335
121408
±121336
ADC Code
ADC Code
40
Time (µs)
Figure 57. Typical FFT Plot
121407
121406
±121337
±121338
121405
0
20
40
60
Time (µs)
80
100
C047
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
positive full-scale input to ADS8881
Figure 59. Reference Droop
26
20
C038
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±121339
0
20
40
60
Time (µs)
80
100
C048
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
negative full-scale input to ADS8881
Figure 60. Reference Droop
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
11 Power Supply Recommendations
The REF60xx family of references have extremely low dropout voltage. The dropout specifications can be found
in the Electrical Characteristics section. A minimum 0.1 µF decoupling capacitor must be connected between the
VIN and GND_F pins of the REF60xx. A typical dropout voltage versus load is shown in Figure 61.
Dropout Voltage (mV)
250
90ƒC
200
125ƒC
150
100
25ƒC
50
-40ƒC
0
±4
±3
±2
±1
0
1
Load Current (mA)
2
3
4
C017
Figure 61. Dropout Voltage vs Load Current
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12 Layout
12.1 Layout Guidelines
Figure 62 illustrates an example of a PCB layout for a data-acquisition system using the REF60xx. Some key
considerations are:
• Connect low-ESR, 0.1-μF ceramic bypass capacitors between the VIN pin and ground.
• Place the REF60xx output capacitor (CL) and the ADC as close to each other as possible.
• Run two separate traces between VOUT_F, VOUT_S and the output capacitor, as shown in Figure 62.
• Short the GND_F and GND_S pins with a solid plane, and extend this plane to connect to the output
capacitor CL, as shown in Figure 62.
• Use a solid ground plane to help distribute heat and reduces electromagnetic interference (EMI) noise pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
CIN
RESR
AGND
ADC
VIN
EN
REF60xx
VOUT
RSS
REFM
REFP
CL
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AGND
CFILT
Figure 62. Layout Example
28
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SBOS708B – MAY 2016 – REVISED AUGUST 2016
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• ADS8881x 18-Bit, 1-MSPS, Serial Interface, microPower, Miniature, True-Differential Input, SAR Analog-toDigital Converter Data Sheet (SBAS547)
• ADS127L01 24-Bit, High-Speed, Wide-Bandwidth Analog-to-Digital Converter Data Sheet (SBAS607)
• REF6025EVM-PDK User's Guide (SBAU258)
• Voltage-Reference Impact on Total Harmonic Distortion (SLYY097)
13.2 Related Links
The following table lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
REF6025
Click here
Click here
Click here
Click here
Click here
REF6030
Click here
Click here
Click here
Click here
Click here
REF6033
Click here
Click here
Click here
Click here
Click here
REF6041
Click here
Click here
Click here
Click here
Click here
REF6045
Click here
Click here
Click here
Click here
Click here
REF6050
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
REF6025IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11KV
REF6025IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11KV
REF6030IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11LV
REF6030IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11LV
REF6033IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11MV
REF6033IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11MV
REF6041IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11NV
REF6041IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11NV
REF6045IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
13SG
REF6045IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
13SG
REF6050IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
13QV
REF6050IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
13QV
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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