SD001EVK

CLC018,LMH0001,LMH0002,LMH0024,LMH0026, LMH0034,LMH0036,LMH0040,LMH0044,LMH0046, LMH0051,LMH0056,LMH0070,LMH0071,LMH0074, LMH0202,LMH0302,LMH0303,LMH0307,LMH0340, LMH0341,LMH0344,LMH0346,LMH0356,LMH0384, LMH0387,LMH0394,LMH0395,LMH1981,LMH1982, LMH1983 Broadcast Video Owner's Manual Literature Number: SNLA188 Broadcast Video Owner’s Manual 1st Edition, Spring 2004 National Semiconductor The Sight & Sound of Information Broadcast Video Owner’s Manual Spring 2004 1st Edition NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor’s SDV Group Table of contents Chapter 1 - Introduction to broadcast video 1.1 1.2 1.3 1.4 Introduction Standards organizations Digital video signals Digital video data structures 1.4.1 Timing reference signals (TRS) 1.4.2 Serial data representation — standard-definition 1.4.3 Serial data representation — high-definition 1.4.4 Pathological data sequences 1.5 Serial digital interface electrical parameters 1.6 Serial digital interface mechanical parameters 1-1 1-1 1-1 1-2 1-4 1-4 1-5 1-5 1-7 1-7 Chapter 2 - System design elements 2.1 Power systems 2.1.1 Power and grounds 2.1.2 PCB layout for serial digital video systems 2.1.3 Voltage regulators and local supply regulation 2.1.4 Planes, pads, and vias 2.2 Transmission line systems 2.2.1 Network topologies 2.2.2 Differential lines 2.2.3 Termination 2.2.4 System-to-system transmission 2.3 Signal path inputs and outputs 2.3.1 Network component and layout guidelines 2.3.2 Bipolar cable driver inputs — CLC005, CLC006, and CLC007 2.3.3 Cable driver outputs — voltage mode 2.3.4 Cable driver outputs — current mode 2.3.5 ECL-compatible inputs 2.3.6 ECL-compatible outputs 2.3.7 CLC011 CMOS outputs 2.3.8 CLC012 and CLC014 Adaptive cable equalizer data inputs www.national.com/appinfo/interface/sdv.html 2-1 2-1 2-3 2-8 2-8 2-9 2-9 2-11 2-16 2-19 2-25 2-25 2-26 2-28 2-30 2-31 2-31 2-33 2-33 Broadcast Video Owner’s Manual Chapter 3 - Serial digital video integrated circuits 3.1 Adaptive cable equalizers 3.1.1 Basic operation 3.1.2 CLC014 3.1.3 CLC012 3.1.4 Typical application 3.1.5 Equalizer application tips 3.2 Reclockers 3.2.1 Basic operation 3.2.2 CLC016 3.2.3 Typical application 3.2.4 Reclocker application tips 3.3 Cable drivers 3.3.1 CLC001 3.3.2 Typical application 3.3.3 CLC005/CLC006/CLC007 3.3.4 Cable driver application tips 3.4 Serializers 3.4.1 Basic operation 3.4.2 CLC020 3.4.3 CLC021 3.4.4 Typical application 3.4.5 CLC020/CLC021 application tips 3.4.6 CLC030 3.4.7 Typical application 3.4.8 CLC030 application tips 3.5 Deserializers 3.5.1 Basic operation 3.5.2 CLC011 3.5.3 Typical application 3.5.4 CLC011 application tips 3.5.5 CLC031 3.5.6 Typical application 3.5.7 CLC031 application tips 3.6 Crosspoint switches 3.6.1 Basic operation 3.6.2 CLC018 4 3-2 3-2 3-3 3-4 3-4 3-6 3-9 3-9 3-10 3-10 3-12 3-12 3-12 3-13 3-13 3-14 3-15 3-15 3-17 3-17 3-17 3-19 3-19 3-19 3-20 3-20 3-20 3-22 3-22 3-22 3-22 3-22 3-23 3-23 3-23 3-24 National Semiconductor’s SDV Group Table of contents Chapter 4 - System testing 4.1 Digital video system testing 4.1.1 Test equipment 4.1.2 Signal generation 4.1.3 Signal and data analysis 4.1.4 Eye pattern testing 4.1.5 Digital stress testing 4.1.6 The SDI check field 4.1.7 EDH and CRC error testing 4.1.8 Jitter testing 4.2 The role of built-in self-test in SDV devices and systems 4.2.1 Digital video data basics 4.2.2 Device BIST architecture 4.2.3 BIST and TPG operation 4.3 Using BIST at the system level 4.3.1 Conclusions 4-1 4-1 4-1 4-1 4-2 4-3 4-3 4-4 4-4 4-4 4-5 4-6 4-7 4-8 4-11 Chapter 5 - SDV evaluation boards 5.1 SDV evaluation/demo boards 5.2 Adaptive cable equalizer evaluation boards 5.2.1 SD012EVK and SD014EVK — overview 5.3 Cable driver evaluation boards 5.3.1 SD001EVK/SD005EVK/SD006EVK/SD007EVK — overviews 5.4 SMPTE 295 serial digital video receiver (equalizer, retimer and decoder, and cable driver) 5.4.1 SD901EVK — overview 5.5 SD serializers 5.5.1 SD020EVK — overview 5.5.2 SD021-5EVK and SD021-3EVK — overview 5.6 SD/HD serializer and deserializers 5.6.1 SD130EVK/SD131EVK — overview 5.6.2 SD130EVK — CLC030 serializer 5.6.3 SD131EVK — CLC031 deserializer 5-1 5-2 5-2 5-3 5-3 5-4 5-4 5-5 5-5 5-5 5-6 5-6 5-6 5-7 Chapter 6 - RAPIDESIGNER slide rule 6.1 RAPIDESIGNER slide rule 6-1 Bibliography Books and publications Standards Useful websites Glossary Glossary www.national.com/appinfo/interface/sdv.html B-1 B-2 B-3 B-3 G-1 5 Chapter 1 Introduction to broadcast video 1.1 Introduction The production of television and film has been transformed through the use of digital production techniques. Improvements in digital imaging have spurred worldwide adoption of digital video transmission and processing. Many advantages accompany this change: lossless archiving and transmission, improved editing and special effects, greater picture definition, improved audio processing and quality, to mention but a few. The digital transition has not been without accompanying problems for the TV system and equipment design engineer. The new digital signal realm that he or she must contend with extends into portions of the electromagnetic spectrum considered as microwave but a few years ago. And the semiconductor devices that process these signals present a new array of design problems and challenges. National Semiconductor’s Broadcast Video Owner’s Manual addresses components and their application in digital video circuits and systems. It is intended as a guide to best practices and proven design techniques that will assist the video engineer in the design task. Many areas are covered including: signals and data coding, mechanical and electrical components, power supply systems, signal transmission systems, testing and device-specific issues. Also included are guides to other resources that will assist and inform the designer. 1.2 Standards organizations The specific requirements for digital television video are administered by several standards organizations: The Society of Motion Picture and Television Engineers (SMPTE) is the worldwide standards body for television and film production. Its standards, engineering guidelines and recommended practices address almost every aspect of signals, and data used in digital video. The International Telecommunications Union (ITU) is the standards body for Europe and much of the world other than the United States. Its standards embody or parallel those of SMPTE. The Digital Video Broadcast Consortium (DVB) is the standards body for European satellite and terrestrial broadcasting of video and other data that may contain compressed video originating as one of the above standards. A list of relevant standards is provided in the bibliography. 1.3 Digital video signals Digital video data signals may be transmitted and processed in parallel or serial format. Parallel data transmission formats are usually found inside equipment or between pieces of equipment where the transmission system length is relatively short, usually a few meters maximum, although certain standards allow links up to 50m. Transmission systems are usually differential between equipment. Cabling of these links is commonly multi-pair, shielded, or twisted pair. Single-ended transmission may be found within equipment and on printed circuit assemblies; however, differential transmission is also common, particularly for the higher data rates. Parallel format data coding is normally non-return to zero (NRZ). Data words may be 8- or 10-bits depending upon the originating equipment and overall data standard requirement. Parallel data is the form most convenient for manipulation such as editing, addition of other data or special effects. Serial data transmission is the preferred method of signaling between equipment over longer distances, usually greater than 10m to about 300m. Transmission distance depends upon several factors such as data rate, type of cable and the receive system’s capability to overcome or mitigate transmission system losses. Serial transmission is commonly single-ended using precision 75Ω coaxial cable for lowest signal loss. www.national.com/appinfo/interface/sdv.html 1-1 Broadcast Video Owner’s Manual Serial links using fiber optics and twisted pair are also found. The data signal format is polynomial encoded non-return to zero inverse (NRZI) and is polarity insensitive. Both the signal and its inverted polarity form represent the same data. Serial video data is transmitted in a continuous stream and is not packetized. The data is transmitted uncompressed within the television plant. This is termed “baseband data transmission.” 1.4 Digital video data structures Digital video data may originate as the digitized representation of analog video data or may be created directly from a digital data source such as computer-generated animation. In either case, the basic elements comprising the data are similar. Data derived from a video source, where all of the picture information including video and synchronizing signals is multiplexed in a single signal like NTSC, PAL or SECAM, is termed a composite digital video representation. Data from a source where the individual color components are represented by separate signals, like RGB or YCR’CB’, is termed a component digital video representation. When converted into digital representation, both have a common structure. The video signal is transmitted in the form of one luminance (Y) and two color-difference components, scaled versions of R_Y and B_Y. Digital video data may be represented as either 8- or 10-bit words or samples. Composite video usually uses 8-bit representations and component 10-bit. Regardless, transport and processing involve similar processes. Since equipment exists that support both 8- and 10-bit representations, all synchronizing signals (EAV, SAV, and ANC) are detected by reference only to the eight most significant bits. The composite video signal is carried at the 4 fsc representation as prescribed in SMPTE 244M at 14.32 MHz. Sampling is also at four times the color subcarrier frequency. The component video signal is transmitted at the 4:2:2 family level of ITU-R BT.601 (SMPTE 125M), with a nominal luminance sampling frequency of 13.5 MHz. The interface allows the transmission of appropriate ancillary signals that may be multiplexed into the data stream during video blanking intervals. 1-2 National Semiconductor’s SDV Group Introduction to broadcast video 719 720 721 736 857 0 1 2 360 368 0 1 855 428 856 428 857 0 0 0 1 359 Y CB Y CR Y CB Y CR Y 1 368 736 368 0 CB Y CR 368 719 360 720 360 721 360 Y CB Y CR Y 359 0 0 0 1 Y 1711 1712 1713 1714 1715 0 1 2 3 EAV CB Y CR Y CB Y CR 1472 1473 1474 719 Y 1439 1440 1441 1442 1443 855 Replaced by timing reference signal 368 736 368 Replaced by timing reference signal SAV Timing reference signals BVOM-021 Figure 1.1. Example of multiplex data structure Data originating from parallel sources may be manipulated easily and is the preferred format for editing, mixing and other special effects operations. The bits of the digital code words comprising the video signal are transmitted in a parallel arrangement using ten balanced conductor pairs. Each pair carries a multiplexed stream of bits of the same order or significance of each of the component signals. The bit-rate used in each pair for standard-definition formats may be 14.3 Mbps, 17.7 Mbps, 27 Mbps or 36 Mbps, depending on the particular picture format. An 11th conductor pair carries a clock signal at a frequency corresponding to the respective data rate in MHz. The signals may be transmitted point-to-point using balanced conductor pairs for a distance up to 50m without equalization and up to 300m with appropriate equalization. However, transport of parallel data presents difficulties, especially over long distances, because of timing skew and other signal distorting conditions. Parameters of the signal format were selected to facilitate conversion to and from a serial digital interface format. When data is to be moved long distances, it is converted into serial representation. Data is converted from 8-bit to 10-bit representation before serialization. www.national.com/appinfo/interface/sdv.html 1-3 Broadcast Video Owner’s Manual 1.4.1 Timing reference signals (TRS) Synchronization words are inserted into the data to serve a similar function to the synchronizing pulses in analog video. In composite data there is only one TRS: the sequence 3FFh, 000h, 000h, 000h. The position in the line data corresponds to the leading edge of analog sync. In component data the TRS sequence is more informative of the type of data present in the line. The sequence is 3FFh, 000h, 000h, XYZh. The XYZh sequence is replaced by protection state bits identifying such things as the beginning and ending of line data, the field being transmitted and position of lines in certain places in the raster. 1.4.2 Serial data representation — standard-definition Serial data is transmitted over single-ended coaxial interfaces at a data rate ten times that of the corresponding parallel data. Data is transmitted most significant bit (MSB) first. Both 4:2:2 component and 4 fsc composite sampled data may be converted to serial format. NTSC 525/60 and PAL 625/50 at both 4:3 and 16:9 raster aspect ratios can be handled by the existing standard-definition serial standard. The corresponding data rates are 270 Mbps (4:3 raster at 13.5 MHz sampling) and 360 Mbps (16:9 raster at 18 MHz sampling). Composite 14.3 MHz 17.7 MHz 143 Mb/s 177 Mb/s Component ATSC Standard definition Parallel source formats 27 MHz 36 MHz SMPTE 244M SMPTE 125M ITU-R BT.656 SMPTE 267M 270 Mbps 360 Mbps Serial transport standard SMPTE 259M ITU-R BT.601 704 x 480 4 960 x 576 704 x 480 (640 x 480) 720 x 576 3 9 16 720 x 576 BVOM-001 Figure 1.2. Relationship of SD parallel and serial formats to resulting raster Serialization requires that the data be encoded using a polynomial scrambling technique which attempts to eliminate long runs of 1’s or 0’s in the resulting serial data and achieve better DC balance. The selfsynchronized pseudo-random scrambling technique is used to improve the data transmission characteristics while maintaining the bandwidth. This technique is used in both standard- and high-definition data. After scrambling, the data is fed through a bi-stable which reduces the number of transitions and hence the effective frequency. The data is thus converted into NRZI representation. NRZI is similar to bi-phase mark or bi-phase space coding. This type of coding also makes the data polarity insensitive whereby both polarities represent the same data. This composite encoding is therefore given as G (x) = (x9 + x4 + 1) (x + 1). Naturally, the receiving system must perform the reverse operation in order to recover the unencoded data. 1-4 National Semiconductor’s SDV Group Introduction to broadcast video 1.4.3 Serial data representation — high-definition Serial data in high-definition systems may be carried over either coaxial cable or fiber optic cable. The two principal serial data rates are 1.485 Gbps and 1.483 Gbps. These correspond to parallel data and sampling rates of 74.25 MHz and 74.176 MHz (74.25/1.001). Component ATSC HDTV Parallel source formats 74.25 MHz 74.176 MHz SMPTE 274M SMPTE 296M ITU-R BT.709 SMPTE 260M 1.485 Gbps 1.485 Gbps Serial transport standard SMPTE 292M ITU-R BT.1120 1920 x 1080 I&P 1280 x 720 P 9 16 BVOM-002 Figure 1.3. Relationship of HD parallel and serial formats to resulting raster Encoding of SMPTE 292M data is similar to that of SMPTE 259M data in most respects. The main difference lies in the way in which the chrominance and luminance data are first interleaved from two or three simultaneous parallel, 10-bit data streams. The 20-bit system, where the color difference and luminance data are carried in separate 10-bit sample streams, is the most common interface. HDTV picture formats are also specified in both progressive scan (P) and interlaced (I) scan modes. All HD picture formats are 16:9 aspect ratio. HD data uses a line-by-line CRC method of reporting data errors. Individual video lines also include a line number after the EAV-TRS. 1.4.4 Pathological data sequences Data encoding schemes used for serial data communication systems generally attempt to maximize the density of data transitions and equalize the numbers of 1’s and 0’s. Despite the attempt to avoid long periods without transitions in the serial data, the scrambling and encoding process is not perfect in accomplishing this. The algorithm fails about 0.2% of possible times. It has been found that certain repeated parallel data sequences will produce extended periods with reduced transitions in the serial data. When repeated over significant portions of a video line, the result can be extended repeating runs of intervals of up to 20-bit times without transition. These originating data sequences are called pathological or stressing data conditions. Pathological data conditions can also occur during the ancillary data portion of the line and the TRS but are not considered as stressing conditions. In standard-definition data this interval can extend for 44-bit intervals and in highdefinition data, 59-bit intervals. These are sometimes referred to as “super-pathological conditions.” www.national.com/appinfo/interface/sdv.html 1-5 Broadcast Video Owner’s Manual It should be appreciated that the special data sequences used to produce pathological data conditions do not usually originate from cameras or other natural image sources. The instances of these pathological data conditions in these sources are infrequent or short-termed. There is usually enough naturally occurring noise in the signal to prevent serious situations from occurring. Pathological conditions are more likely to occur with synthetic image sources such as matte generators or graphics generators. Pathological conditions in the serial data can produce corruption of the video data when received and decoded. If the receiving system is not designed to cope with these conditions, poor picture quality can result from the lost or incorrectly decoded data. In particular, two main types of pathological conditions are to be guarded against: • The conditions affecting the cable equalizer • Those affecting the receiving system PLL and data recovery system Pathological conditions in serial digital video systems are explained in SMPTE EG 34. Test data suitable for pathological testing is defined in SMPTE RP 178 for standard-definition and RP 198 for high-definition systems. Stressing the automatic cable equalizer is done with a data pattern having long sequences of 1’s or 0’s and infrequent single-bit transitions of the opposite polarity. The bit ratio is 19:1 and occurs for both data polarities. This stressing condition with very high (or low) duty cycle also tests whether the AC coupling network has sufficient low-frequency response. In cases where LF response is lacking, the baseline DC level of the data is shifted up or down. Pulse width distortion will occur which can prevent proper data recovery. High-definition standard SMPTE 292M specifies the maximum DC shift in a line period for coaxial systems. SMPTE 259M (standard-definition) does not specify this parameter. The receiver PLL is stressed using a data sequence having maximum low-frequency content or maximum time between transitions. The bit ratio is 20:20 and occurs for both data polarities. Pathological data conditions can be avoided in synthetic image generation and sources by adding a small amount of noise in the form of dithering to the least significant bit of the digital video words. The noise breaks up the repetitive nature of the data feeding the scrambler and thus the repeated output that results. 1-6 National Semiconductor’s SDV Group Introduction to broadcast video 1.5 Serial digital interface electrical parameters1 Table 1.1. Serial digital interface electrical properties Parameter Serial system impedance Serial signal amplitude DC offset Rise/fall time, 20% to 80% Rise/fall time difference Amplitude overshoot Return loss at I/P or O/P connector, 5 MHz to clock SMPTE 259M 75Ω 800 mV ±10% p-p 0.0 ±0.5V 0.4 to 1.5 ns 0.5 ns 10% 15 dB SMPTE 292M 75Ω 800 mV ±10% p-p 0.0 ±0.5V W1 + W2 W W W1 W2 45° Bad Acceptable Good BVOM-015 Figure 2.13. Good, bad and acceptable trace intersections 2-14 National Semiconductor’s SDV Group System design elements Figure 2.13 illustrates several types of trace intersections in transmission lines. In the left-hand column are intersections that range from bad to worse. Right-angled corners, T-intersections and abrupt changes in line width are to be avoided in SDV transmission lines. Acute intersections are also to be avoided. In the center column, mitered trace corners and t-intersections where impedance integrity is maintained may be used. Though not preserving of impedance, mitering steps in transmission line width reduces the disturbance. If the difference in widths is small, acceptable signal integrity can usually be obtained. In the right column, better ways of transitioning and cornering in transmission lines are shown. These methods preserve impedance integrity except in the case of changing line widths. In the case of changing line widths, unless the trace to image plane spacing is also appropriately altered, the impedance will change with the width. 2.2.2.2 Trace and differential pair spacing W S >2S >3S Pair 1 Pair 2 Pair 3 Pair 4 TTL h BVOM-016 Figure 2.14. Differential line spacing Following from Figure 2.14 and using the edge-to-edge “S” distance between the traces of a pair, transmission line separation rules can be defined: • The distance between two pairs should be >2S. • The distance between an SDV pair and a TTL/CMOS signal should be >3S at a minimum. Even better, locate the TTL/CMOS signals on a different plane isolated by a ground plane or on the opposite side of the PCB from the SDV signals. • If a guard ground trace or ground fill is used, it should be >2S away. www.national.com/appinfo/interface/sdv.html 2-15 Broadcast Video Owner’s Manual 2.2.2.3 Crosstalk problems in SDV circuits Inductive and capacitive coupling between transmission lines causes crosstalk. The magnitude of the crosstalk voltage is proportional to the reciprocal of the square of the spacing between the conductors (strictly speaking, the ratio of line spacing to the distance separating the line from its image plane is s/t). The greater the spacing (or smaller distance to the image plane), the less possibility there is for crosstalk. The duration of a crosstalk signal is proportional to the length over which the lines are coupled together. Longer coupled lengths produce longer duration crosstalk signals. Crosstalk resulting from reverse coupling, or backward crosstalk, is considered the most disruptive since its amplitude is greater than that of forward crosstalk. For forward crosstalk to be a factor, the network’s electrical length must be much longer than the period of the pulses since the amplitude increases slowly with the distance traveled. Crosstalk can be reduced through some simple steps: • Space individual transmission lines, or groups of differential transmission line pairs, apart by at least twice the width of the widest conductor. See Figure 2.14. • Place a shield line or guard trace between or around conductors that are sensitive to interference such as those used in inputs to adaptive cable equalizers. Frequent ties to ground along the shield or guard trace are required. • Separate clock or other high-frequency signals away from other circuits and surround by ground floods or guard traces. • Use stripline for especially sensitive signal conditions. 2.2.3 Termination 2.2.3.1 Single-ended termination There are numerous termination schemes that may be used: series, parallel, AC parallel, and Thevenin terminations. AC parallel and series terminations are useful for low power applications since they do not consume any DC power. Parallel and Thevenin terminations can have relatively high DC power consumption. 2.2.3.2 No termination Transmission line systems used for the high data rates in SDV video data transmission must be terminated to preserve pulse and signal characteristics. The no termination situation is not used as it produces the worst possible signal distortion. Sometimes in non-critical, low speed TTL or CMOS logic networks, it can be used but line lengths must be kept short. The one-way propagation delay should not exceed about 1⁄2 of the signal risetime for the logic being used. 2-16 National Semiconductor’s SDV Group System design elements c. Parallel termination a. No termination b. Series termination d. AC parallel termination V+ e. Thevenin termination BVOM-023 Figure 2.15. Single-ended termination 2.2.3.3 Series termination Series terminations, Figure 2.15 (b), may be used in high-speed applications such as SDV systems where the load is located at the far end of the line. This situation is typically found in the coaxial transmission systems using cable drivers having so-called back-matched terminations. Generally, SDV networks have terminated load ends. When used for networks with loads located between the driver and the unterminated receiving end of the line, the intermediate loads will receive a two-step waveform. The first step will be the incident wave, VI. The amplitude is determined by the output equivalent generator resistance of the driver, the value of the series resistor, and the impedance of the line according to the formula: VI = V OUT Z 0 Z 0 + R S + R GEN The amplitude will be one-half the voltage swing if series resistance, RS, plus the driver output equivalent generator resistance, RGEN, is equal to the line impedance. RGEN for the cable drivers is about 5Ω. In the case of an unterminated load end, the second step of the waveform is the reflection from the destination end of the line. It will have an amplitude and polarity equal to that of the first step. All devices on the line will receive a valid level only after the wave has propagated down the line and returned to the driver. Therefore, all inputs will see the full voltage swing after a time equal to the round-trip delay of the line. www.national.com/appinfo/interface/sdv.html 2-17 Broadcast Video Owner’s Manual 2.2.3.4 Parallel termination Parallel terminations, Figure 2.15 (c), are commonly found in SDV circuits, both on PCBs and coaxial transmission systems. The resistor value is most commonly the value of the transmission line Z0. These terminations are not generally recommended for TTL or CMOS circuits because of their power consumption. Sometimes this can exceed the power consumption of the logic itself. Output circuit overloading is quite common if the resistor is not correctly sized. Power consumption of parallel terminations is a function of the resistor value and the signal duty cycle. Generally, the resistor cannot be made equal to the transmission line impedance because of this overloading. In addition, parallel termination affects the output bias of the driver towards either the positive supply or ground depending on to which it is returned. While this characteristic is not desirable when driving CMOS inputs, it can be useful when driving TTL inputs. 2.2.3.5 AC parallel termination AC parallel terminations, Figure 2.15 (d), work well in networks where delays caused by series terminations are unacceptable. The effectiveness of AC parallel terminations is similar to that of standard parallel terminations. The major difference is that the capacitor blocks any DC current path and helps to reduce power consumption. The capacitor is generally sized to be effective during the transitions. 2.2.3.6 Thevenin termination Thevenin terminations, Figure 2.15 (e), are common in SDV circuits. The principal drawback to their use is their power consumption that is typically 11 times that of a comparable parallel termination (in ECL circuits). Like the parallel termination, a DC path across the power supply exists due to the series connected terminating resistors. The power consumption of a Thevenin termination is not strictly a function of signal duty cycle. Thevenin terminations are often used in CMOS applications because they do not bias the output levels as do parallel terminations. 2.2.3.7 Differential termination Differential lines are most commonly terminated using a single resistor of a value equal to the characteristic differential impedance of the line. The main issue with differential terminations is where to locate the resistor. The principal concern is the stub created when connecting the load to the line. l Fly-by RT RT Stub length (a) Stub length l (b) BVOM-017 Figure 2.16. Differential termination location By way of illustrating the tradeoff, Figure 2.16 shows two conditions. In Figure 2.16 (a) the termination is located immediately ahead of the receiver input. The stub exists in the excess line connecting the termination to the receiver and the lead frame and bond wire inside the package. If long enough, this stub can cause ripples or overshoot in the transitioning edges of the signal. This is particularly troublesome in HDTV serial data links where the risetime is R0 = R0 = R0 = R0 Awful to different signals at each point on the line. Load signal excellent. NA 2 No Not generally useful. 0.5 VSS No Excellent fidelity 0.25 VSS Yes < R0 Load signal like a one shot. NA NA > R0 > R0 Exponential like signal waveforms. 0.5 VSS Yes > R0 = R0 Small signal amplitude and excellent fidelity. 0.5 VSS Yes > R0 < R0 Very small signal amplitudes, also ringing. NA NA www.national.com/appinfo/interface/sdv.html V SS RL Reduced power consumption over parallel termination. Greater tolerances on resistors allowed for same fidelity as parallel termination. Not generally useful for data, is useful as pulse generator. Low power consumption. Increased delay due to signal “rise” times. Produces only small signal voltages compared with other methods. Not generally useful. 2-23 Broadcast Video Owner’s Manual 2.2.4.3 Termination summary — the advantageous combinations In examining the basic combinations of source, line and load resistances, and typical waveforms characteristic of each case, advantageous combinations can be determined. The primary results are tabulated in Table 2.2. Those combinations generally used in voltage mode communications circuits are as follows: • Unterminated case (RS > R0). This situation provides low steady state power dissipation and large signal levels, but also shows pronounced “ringing” effects. The ringing can be reduced by controlling signal rise/fall time vs. time delay of the line, or by clamping (with diodes, for example) to limit load signal excursions. This case is representative of TTL/CMOS circuits and thus, is widely employed. • The parallel-terminated case (RS > R0) provides a low steady state power dissipation system for use with one receiver located at the load end of the line. The positive reflection coefficient of the load is used to approximately double the initial wave arriving at the load. Setting RS = R0 terminates the reflected wave when it arrives back at the source site after two line delays, and the line then assumes steady state conditions. The use of other receivers located along the line is not recommended, because they will not see the full driver signal swing until the reflection from the load passes their particular bridging points. Such receivers could malfunction, as they would see a voltage very close to their threshold, and perhaps even place the line receiver in its linear operating region. This could make the line receiver sensitive to oscillatory, parasitic feedback. If these constraints are acceptable, the series termination method can be used to good advantage in providing the same signal fidelity and signal amplitude as with the parallel termination method, while at the same time contributing a significant savings in steady state power consumption. • The fully matched case (RS = R0, RL = R0) not only provides excellent signal fidelity all along the line, but also has reduced signal amplitude over that of the parallel-terminated case. Additionally, the power consumption is somewhat less than the parallel-termination case and the power is divided equally by the source and load. The primary advantage of the fully matched system is that termination resistor tolerances can be relaxed somewhat without incurring large amounts of ringing. This is because both the source and load act as line terminations. 2-24 National Semiconductor’s SDV Group System design elements 2.3 Signal path inputs and outputs 2.3.1 Network component and layout guidelines This section includes a discussion of the specifics of particular signal path inputs and outputs. It is important to understand the layout of these networks. The networks generally serve relatively low-impedance 75Ω systems, where the individual properties of the components and their method of mounting can dramatically affect the integrity of the SDV data signal. The main guidelines are listed below: 1. Group input and output network components compactly to avoid excessive interconnect lengths. Coupling can occur between the bodies of components that can add unwanted parasitics to the network and affect impedances or signal waveforms. Therefore, maintain appropriate spacing between components to reduce this unwanted coupling. Generally, a spacing of at least twice the thickness (or height) of the component body is sufficient. 2. Use components of minimum physical size, but be sure that these have adequate power and voltage ratings. 3. When attempting to maintain the characteristic impedance and reduce parasitic effects, voids or clearance areas in the image power and ground planes directly under the affected components may be used. The void areas in the copper planes should be larger than the area of the components. The cleared area should include additional clearance (or “shrink-back” as it is often termed) all around of at least twice the thickness of the dielectric layer under the components. This will minimize stray capacitance to pads and lines. 4. The layout of differential inputs and outputs should be symmetrical or mirror-image. This equalizes the effect of parasitic elements and stray pickup effects on either inputs or outputs. 5. Surround sensitive inputs with ground rings or ground floods on the outer PCB layers to prevent pickup of EMI. This applies especially to the inputs of adaptive cable equalizers. Also, do not locate high-level outputs or other high-level signals adjacent to the inputs and input networks of these devices. 6. SDV serial signals are broadband RF signals. Grounding in networks carrying RF signals requires larger area conductors and more vias than is the case with other types of signals. Grounding considered adequate for audio, common digital and other lower frequency applications is not adequate for baseband SDV serial signals, especially at the HD rates. 7. Use only high quality RF-rated ceramic capacitors for coupling the SDV serial signal. Aluminum and tantalum electrolytic capacitors are not suitable for RF or digital signal coupling. Besides their large physical size which requires large mounting pads that can cause severe signal distortion, these are polarized devices that exhibit non-linear or diode-like effects in the presence of signals with a varying DC component. www.national.com/appinfo/interface/sdv.html 2-25 Broadcast Video Owner’s Manual 2.3.2 Bipolar cable driver inputs — CLC005, CLC006, and CLC007 The CLC005, CLC006 and CLC007 have high-impedance, emitter-follower buffered, differential inputs. These inputs accept both differential and single-ended signals. Either AC or DC coupling as shown in Figure 2.22 or Figure 2.23 may be used. Figure 2.22 shows how Thevenin-equivalent resistor networks are used to provide input termination and biasing. A method of low power biasing is shown in Figure 2.24 that reduces the supply current used by the bias network to about 1 mA. Transmission lines supplying input signals must be properly terminated close to the device. Input coupling network layouts should be kept compact with short interconnecting lines. The input DC common-mode voltage range of the CLC005, CLC006, and CLC007 is 0.8V to 2.5V below the positive power supply (VCC). Input signals plus bias must be kept within the specified common-mode range. For an 800 mV p-p input signal, typical input bias levels should range from 1.2V to 2.1V below the positive supply. VCC VIN± VIN+ To next stage VEE BVOM-056 Figure 2.21. CLC005, CLC006 or CLC007 input stage AC coupling capacitors must be sized for the particular data rate and data coding of the system in which the driver is used. For standard-definition SDV applications operating at 270 Mbps and 360 Mbps, a value of 1 µF is recommended. For applications operating at 143 Mbps and 177 Mbps, either 1 µF or 2.2 µF are recommended. For use at all standard-definition rates, 1 µF is adequate for pathological conditions. For other data codings such as 8B10B and others that are relatively DC balanced, 0.1 µF may be used. ECL output VCC ZO 1.0 µF R1 VCC R1 8 7 43 1 6 VEE ZO 5 1.0 µF R2 R2 VEE 2 CLC006 VEE VEE BVOM-057 Figure 2.22. AC coupling with Thevenin termination 2-26 National Semiconductor’s SDV Group System design elements Thevenin terminations are disadvantageous because of the large amount of supply power that they consume, typically as much as 11x that of the equivalent parallel termination. For this reason, lower power bias and termination schemes are preferred such as the one shown in Figure 2.24. Table 2.3 gives resistor values for a variety of common application situations. Table 2.3. Thevenin terminations Load type ECL, 50Ω, 5V, VT = 2V ECL, 50Ω, 5.2V, VT = 2V ECL, 75Ω, 5V, VT = 2V ECL, 75Ω, 5.2V, VT = 2V 800 mV p-p, 50Ω, 5V, VT = 1.6V 800 mV p-p, 75Ω, 5V, VT = 1.6V 800 mV p-p, 2.2kΩ, 5V, VT = 1.6V Resistor to VCC (R1) 82.5Ω 80.6Ω 124Ω 121Ω 75Ω 110Ω 3240Ω Resistor to VEE (R2) 124Ω 133Ω 187Ω 196Ω 154Ω 232Ω 6810Ω ECL output VCC ZO 7 8 4 31 6 ZO 5 R0 R0 VEE 2 CLC006 VEE BVOM-058 Figure 2.23. DC coupling with parallel termination The CLC005, CLC006, and CLC007 may be DC coupled to suitable sources. The source must have a DC output voltage range that meets the CLC005, CLC006, or CLC007 input common mode requirements. The termination may be either Thevenin or parallel according to the designer’s choice and the specific needs of the driver output. When the system is PECL, parallel loads should be returned to VCC. www.national.com/appinfo/interface/sdv.html 2-27 Broadcast Video Owner’s Manual VCC 1,300Ω 4.7 µF 35V + 3,650Ω 0.1 µF 825Ω VIN+ 7 82.5Ω 1.0 µF VIN+ 1 Q0 2 Q0 825Ω VIN± 6 82.5Ω 8 VCC 1.0 µF Q1 VIN2 VEE 0.1 µF Q1 CLC007 4 5 BVOM-029 Figure 2.24. AC coupling with low power termination It is desirable that input bias schemes be designed for low power consumption. Figure 2.24 shows one classical method. The input bias current required by the device is