DS90C241 Serializer and
DS90C124 Deserializer
Evaluation Kit
User’s Manual
NSID: SERDES24-35USB
Rev 1.5
National Semiconductor Corporation
Date: 2/27/2008
Page 1 of 39
Table of Contents
TABLE OF CONTENTS ........................................................................................................................................... 2
INTRODUCTION: ..................................................................................................................................................... 3
CONTENTS OF THE EVALUATION KIT:........................................................................................................... 4
DS90C241/124 SERDES TYPICAL APPLICATION:............................................................................................ 4
HOW TO SET UP THE EVALUATION KIT:........................................................................................................ 6
EVALUATION BOARD POWER CONNECTIONS: ............................................................................................ 6
DS90C241 TX SERIALIZER BOARD DESCRIPTION: ....................................................................................... 7
CONFIGURATION SETTINGS FOR THE TX EVALUATION BOARD ................................................................................. 8
TX LVCMOS AND LVDS PINOUT BY CONNECTOR ................................................................................................ 11
BOM (BILL OF MATERIALS) SERIALIZER PCB: ...................................................................................................... 12
DS90C124 RX DE-SERIALIZER BOARD DESCRIPTION: .............................................................................. 13
CONFIGURATION SETTINGS FOR THE RX EVALUATION BOARD .............................................................................. 14
RX LVDS PINOUT AND LVCMOS BY CONNECTOR ............................................................................................... 16
BOM (BILL OF MATERIALS) DE-SERIALIZER PCB: ................................................................................................ 17
TYPICAL CONNECTION AND TEST EQUIPMENT........................................................................................ 18
TYPICAL CONNECTION DIAGRAM TX – USER QUICK REFERENCE .................................................... 20
TYPICAL CONNECTION DIAGRAM RX – USER QUICK REFERENCE.................................................... 21
TROUBLESHOOTING DEMO SETUP ................................................................................................................ 22
APPENDIX................................................................................................................................................................ 24
SERIALIZER (TX) PCB SCHEMATIC:............................................................................................................... 24
DE-SERIALIZER (RX) PCB SCHEMATIC:........................................................................................................ 28
SERIALIZER (TX) PCB LAYOUT: ...................................................................................................................... 32
SERIALIZER (TX) PCB STACKUP: .................................................................................................................... 35
DESERIALIZER (RX) DEMO PCB LAYOUT: ................................................................................................... 36
DESERIALIZER (RX) PCB STACKUP:............................................................................................................... 39
National Semiconductor Corporation
Date: 2/27/2008
Page 2 of 39
Introduction:
National Semiconductor’s DS90C241/124 embedded clock SERDES evaluation kit
contains 1 - DS90C241 Serializer (Tx) board, 1 - DS90C124 De-serializer (Rx) board,
and 1 - two (2) meter high speed USB 2.0 cable.
Note: the evaluation boards are not for EMI testing. The evaluation boards were
designed for easy accessibility to device pins with tap points for monitoring or applying
signals, additional pads for termination, and multiple connector options.
The DS90C241/124 chipset supports a variety of display and general purpose
applications. The single embedded clock LVDSe interface is well-suited for any display
system interface. Typical applications include: navigation displays, automated teller
machines (ATMs), POS, video cameras, global positioning systems (GPS), portable
equipment/instruments, factory automation, etc.
The DS90C241 and DS90C124 can be used as a 24-bit general purpose LVDSe
Serializer and De-serializer chipset designed to transmit data at clocks speeds ranging
from 8 to 35 MHz.
The Serializer board accepts 3.3V_LVCMOS input signals. The Serializer converts the
3.3V_LVCMOS parallel inputs into a single serialized LVDSe data pair with an
embedded LVDS clock. The serial data stream toggles at 28 times the base clock rate.
With an input clock at 35 MHz, the transmission rate for the LVDSe line is 840Mbps.
The De-serializer board accepts the LVDSe serialized data stream with embedded clock
and converts the data back into parallel 3.3V_LVCMOS signals and clock. Note that
NO external reference clock is needed to prevent harmonic.
Suggested equipment to evaluate the chipset; a 3.3V_LVCMOS signal source such as a
video generator,word generator or pulse generator and an oscilloscope with a
bandwidth of at least 35 MHz will be needed.
The user needs to provide the proper 3.3V_LVCMOS/RGB inputs and
3.3V_LVCMOS/clock to the Serializer and also provide a proper interface from the Deserializer output to an LCD panel or test equipment. The Serializer and De-serializer
boards can also be used to evaluate device parameters. A cable conversion board or
harness scramble may be necessary depending on type of cable/connector interface
used on the input to the DS90C241 and to the output of the DS90C124.
Example of suggested display setup:
1) video generator with 3.3V_LVCMOS output
2) 18-bit LCD panel with a 3.3V_LVCMOS input interface.
National Semiconductor Corporation
Date: 2/27/2008
Page 3 of 39
Contents of the Evaluation Kit:
1) One DS90C241 Serializer board
2) One DS90C124 De-serializer board
3) One 2-meter high speed USB 2.0 cable (4-pin USB A to 5-pin mini USB)
4) Evaluation Kit Documentation (this manual)
5) DS90C241/124 Datasheet
DS90C241/124 SERDES Typical Application:
Figure 1a. Typical Application (18-bit RGB Color)
Figure 1b. Typical DS90C241/124 SERDES System Diagram
National Semiconductor Corporation
Date: 2/27/2008
Page 4 of 39
Figures 1a and 1b illustrate the use of the Chipset (Tx/Rx) in a Host to Flat Panel
Interface.
The chipsets support up to 18-bit color depth TFT LCD Panels.
Refer to the proper datasheet information on Chipsets (Tx/Rx) provided on each board
for more detailed information.
National Semiconductor Corporation
Date: 2/27/2008
Page 5 of 39
How to set up the Evaluation Kit:
The PCB routing for the Tx input pins (DIN) have been laid out to accept incoming
3.3V_LVCMOS signals from 2x25-pin IDC connector. The TxOUT/RxIN (DOUT/RIN)
interface uses a single twisted pair cable (provided). The PCB routing for the Rx output
pins (ROUT) are accessed through a 2x25-pin IDC connector. Please follow these steps
to set up the evaluation kit for bench testing and performance measurements:
1) A two (2) meter high speed USB 2.0 cable has been included in the kit. Connect the
1
2
3
4
A
4-pin USB A
side of cable harness to the serializer board and the
otherside 5-pin mini USB jack 1 2 3 4 MIN to the de-serializer board.
This
completes the LVDS interface connection.
NOTE: The DS90C241 and DS90C124 are NOT USB compliant and should not
be plugged into a USB device nor should a USB device be plugged into the
evaluation boards.
2) Jumpers and switches have been configured at the factory; they should not require
any changes for immediate operation of the chipset. See text on Configuration
settings for more details.
3) From the Video source, connect a flat cable (not supplied) to the Serializer board
and connect another flat cable (not supplied) from the De-serializer board to the
panel. Note: For non 50 ohm signal sources, provide 3.3V_LVCMOS input signal
levels into DIN[23:0] and TCLK and remove the 49.9 ohm parallel termination
resistors R1-R25 on the DS90C241 Serializer board.
4) Power for the Tx and Rx boards must be supplied externally through Power Jack
(VDD). Grounds for both boards are connected through Power Jack (VSS) (see
section below).
Evaluation Board Power Connections:
The Serializer and De-serializer boards must be powered by supplying power externally
through J4 (VDD) and J5 (VSS) on Serializer Board and J4 (VDD) and J5 (VSS) on Deserializer board. Note +4V is the MAXIMUM voltage that should ever be applied to the
Serializer (DS90C241) or De-serializer (DS90C124) VDD terminal. Damage to the
device(s) can result if the voltage maximum is exceeded.
National Semiconductor Corporation
Date: 2/27/2008
Page 6 of 39
DS90C241 Tx Serializer Board Description:
The 2x25-pin IDC connector J1 accepts 24 bits of 3.3V_LVCMOS RGB data along with
the clock input.
The Serializer board is powered externally from the J4 (VDD) and J5 (VSS) connectors
shown below. For the Serializer to be operational, the Power Down (S1-TPWDNB) and
Data Enable (S1-DEN) switches on S1 must be set HIGH. S1- RESVRDA, RESVRDB,
and VODSEL must be set LOW. Rising or falling edge reference clock is user selected
on S1-TRFB: HIGH (for rising edge strobing) or LOW (for falling edge strobing).
The USB connector P2 (USB-A side) on the bottom side of the board provides the
interface connection to the LVDS signals to the De-serializer board. Note: P1 (mini
USB) on the top side is un-stuffed and not to be used with the cable provided in the kit.
f J4, J5
Note:
VDD and VSS MUST
be applied externally
from here.
e
J1
d
S1
NOT FOR EMI TESTING
JP3, VR1
g
g
g
Note:
Connect cable
(USB A side)
to P2 on BACKSIDE.
c P2 BACKSIDE
c P1 TOPSIDE (UNSTUFFED)
g
Legend
c LVDS OUTPUTS
d LVCMOS INPUTS
e FUNCTION CONTROLS
f POWER SUPPLY
g 49.9Ω INPUT TERMINATION
e
(For 50Ω signal sources,
remove otherwise if populated.)
Figure 2. DS90C241 Tx Evaluation Board
National Semiconductor Corporation
Date: 2/27/2008
Page 7 of 39
Configuration Settings for the Tx Evaluation Board
Table 1.
S1: Serializer Input Features Selection
Reference
Description
Input = L
RESVRDA DCAOFF
MUST be
1
IMPORTANT
tied low for
See user note
normal
below
operation
(Default)
RESVRDB DCBOFF
MUST be
1
IMPORTANT
tied low for
See user note
normal
below
operation
(Default)
TPWDNB PoWerDowN Bar
Powers
Down
TRFB
Latch input data
Falling
on Rising or
Edge
Falling edge of
(Default)
TCLK
VODSEL
LVDS output VOD ≈350mV
SELect
(Default)
RESVRD
RESeRVeD
(* IMPORTANT
See user note
below)
DEN
UNUSED
Output Data
ENabled
UNUSED
Input = H
-
S1
-
Operational
(Default)
Rising Edge
≈700mV
MUST be
tied low for
normal
operation
(Default)
Disabled
Enabled
(Default)
Don’t care Don’t care
Note:
In user layout RESVRDA (pin 5), RESVRDB (pin 8), RESVRD (pin 13) MUST be tied
low for proper operation.
1
National Semiconductor Corporation
Date: 2/27/2008
Page 8 of 39
Table 2.
JP3,VR1: Pre-Emphasis Feature Selection
Reference
Description
JP3
Pre-Emphasis – helps to
increase the eye pattern
opening in the LVDS stream
JP3 &
VR1
Pre-Emphasis adjustment
(via screw)
JP3 MUST have a jumper to
use VR1 potentiometer.
VR1 = 0Ω to 20KΩ,
JP3 + VR1 =
3.01KΩ (minimum) to
23.01Ω (maximum).
IPRE = [1.2/(RPRE)] x 20,
RPRE (minimum) > 3KΩ
OPEN
(floating)
Disabled –
no jumper
(Default)
CLOSED
(Path to GND)
Enabled –
With jumper
Clockwise
CounterClockwise
increases
RPRE value
which
decreases
preemphasis
decreases
RPRE value
which
increases
preemphasis
Pre-emphasis user note:
Pre-emphasis must be adjusted correctly based on application frequency, cable quality,
cable length, and connector quality. Maximum pre-emphasis should only be used under
extreme worse case conditions; for example at the upper frequency specification of the
part and/or low grade cables at maximum cable lengths. Typically all that is needed is
minimum pre-emphasis. Users should start with no pre-emphasis first and gradually
apply pre-emphasis until there is clock lock and no data errors. The best way to monitor
the pre-emphasis effect is to hook up a differential probe to the 100Ω termination
resistor (R1) on the DS90UR124 Rx evaluation board (NOT to R27 on the DS90UR241
Tx evaluation board). The reason for monitoring R1 on the Rx side is because you want
to see what the receiver will see the attenuation signal AFTER the cable/connector.
National Semiconductor Corporation
Date: 2/27/2008
Page 9 of 39
Table 3.
JP1, JP2: USB Red and Black wire
Reference
Description
Power wire in USB cable
JP1
thru P2 (and P1 not
mounted) connector
Jumper RED to VSS –
recommended
VDD
VSS
Red wire tied Red wire
to VDD
tied to VSS
(Default)
OPEN
Red wire
floating
(not
recommended)
Black wire
tied to VDD
Black wire
floating
(not
recommended)
Note: Normally VDD in USB application
Power wire in USB cable
thru P2 (and P1 not
mounted) connector
Jumper BLACK to VSS –
recommended
JP2
Black wire
tied to VSS
(Default)
Note: Normally VSS in USB application
top side thru the board view
(mounted on solder side)
P2
pin 3
pin 4
USB A
BLACK WIRE
pin 2
+
_
pin 1
RED WIRE
National Semiconductor Corporation
Date: 2/27/2008
Page 10 of 39
Tx LVCMOS and LVDS Pinout by Connector
The following three tables illustrate how the Tx inputs are mapped to the IDC connector
J1, the LVDS outputs on the USB-A connector P2, and the mini USB P1 (not mounted)
pinouts. Note – labels are also printed on the evaluation boards for both the
3.3V_LVCMOS input and LVDS outputs.
J1
LVCMOS INPUT
P2
(bottom side)
P1
(topside)
LVDS OUTPUT
(not mounted)
pin
no.
name
name
pin
no.
1
GND
DIN0
2
pin no.
name
3
GND
DIN1
4
1
JP1
pin no.
name
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
GND
DIN2
GND
DIN3
GND
DIN4
2
3
4
DOUT+
DOUTJP2
GND
DIN5
GND
DIN6
5
4
3
2
1
JP2
NC
DOUTDOUT+
JP1
GND
DIN7
GND
DIN8
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
GND
DIN9
GND
DIN10
GND
DIN11
GND
DIN12
GND
DIN13
GND
DIN14
GND
DIN15
GND
DIN16
GND
DIN17
GND
DIN18
GND
DIN19
GND
DIN20
GND
DIN21
GND
DIN22
GND
DIN23
GND
TCLK
National Semiconductor Corporation
LVDS OUTPUT
Date: 2/27/2008
Page 11 of 39
BOM (Bill of Materials) Serializer PCB:
DS90C241 Tx USB Demo Board - Board Stackup Revised: Thursday, March 23, 2006
DS90C241 Tx USB Demo Board
Revision: 1
Bill Of Materials
March 23,2006
18:52:42
Item
Qty
Reference
Part
PCB Footprint
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
1
1
1
5
5
5
2
1
1
2
1
1
24
0.1uF
2.2uF
22uF
0.1uF
22uF
0.01uF
0.1uF
3-Pin Header
2-Pin Header
IDC2X25_Unshrouded
BANANA
mini USB 5pin_open
USB A
49.9ohm_open
CAP/HDC-0402
3528-21_EIA
CAP/N
CAP/HDC-1206
CAP/EIA-B 3528-21
CAP/HDC-0603
CAP/HDC-0603
Header/3P
Header/2P
IDC-50
CON/BANANA-S
mini_USB_surface_mount
USB_TYPE_A_4P
RES/HDC-0201
49.9ohm_open
5.76K (3.01K)
100 ohm,0402
0 Ohm,0402
10K
RES/HDC-0805
RES/HDC-0402
RES/HDC-0402
RES/HDC-0402
RES/HDC-0805
1
1
C1,C2
C3
C4
C5
C6,C9,C10,C13,C20
C7,C11,C15,C16,C19
C8,C12,C14,C17,C18
JP2,JP1
JP3
J1
J5,J4
P1
P2
R1,R2,R3,R4,R5,R6,R7,R8,
R9,R10,R11,R12,R13,R14,
R15,R16,R17,R18,R19,R20,
R21,R22,R23,R24
R25
R26
R27
R28,R30,R32,R33,R35
R38,R39,R40,R41,R42,R43,
R44,R45
S1
U1
15
16
17
18
19
1
1
1
5
8
20
21
SW DIP-8
DS90C241
1
VR1
DIP-16
48 ld TQFP
Surface Mount 4mm
Square
22
SVR20K
National Semiconductor Corporation
Date: 2/27/2008
Page 12 of 39
DS90C124 Rx De-serializer Board Description:
The USB connector J2 (mini USB) on the topside of the board provides the interface
connection for LVDS signals to the Serializer board. Note: J1 (mini USB) on the bottom
side is un-stuffed and not used with the cable provided in the kit.
The De-serializer board is powered externally from the J4 (VDD) and J5 (VSS)
connectors shown below. For the De-serializer to be operational, the Power Down
(RPWDNB) and Receiver Enable (REN) switches on S1 must be set HIGH. Rising or
falling edge reference clock is user selected by S1-RRFB: HIGH (for rising edge
strobing) or LOW (for falling edge strobing).
The 50 pin IDC Connector J3 provides access to the 24 bit 3.3V_LVCMOS and clock
outputs.
Note:
VDD and VSS MUST be
applied externally here
e S1
Note:
Connect cable
(mini USB side) to J2
on (TOPSIDE).
NOT FOR EMI TESTING
d J3
d JP3
c J2 (TOPSIDE)
c J1 BACKSIDE
(UNSTUFFED)
LEGEND
c LVDS INPUTS
d LVCMOS OUTPUTS
e FUNCTION CONTROLS
f POWER SUPPLY
Figure 3. DS90C124 Rx Evaluation Board
National Semiconductor Corporation
Date: 2/27/2008
Page 13 of 39
Configuration Settings for the Rx Evaluation Board
Table 4.
S1: De-serializer Input Features Selection
Reference
Description
RFB
Latch output data on Rising
or Falling Data Strobe of
RCLK
REN
Receiver Output ENabled
RPWDNB
PoWerDowN Bar
RESVRD
RESeRVeD
Input = L
Falling
(Default)
Input = H
Rising
Disabled
Enabled
(Default)
Operational
(Default)
Power
Down
(Disabled)
Don’t care
S1
Don’t care
2
IMPORTANT
See user note
below)
Table 5.
JP3: Output Lock Monitor
Reference
Description
Output = L
LOCK
Receiver PLL LOCK
unlocked
Note:
DO NOT PUT A SHORTING
JUMPER IN JP3.
Output = H
locked
JP3
Note:
In user layout RESVRD (pin 2) MUST be tied low for proper operation.
2
National Semiconductor Corporation
Date: 2/27/2008
Page 14 of 39
Table 6.
JP1, JP2: USB Red and Black wire
Reference
Description
Power wire in USB cable
JP1
thru J2 (and J1 not
mounted) connector
Jumper RED to VSS –
recommended
VDD
VSS
Red wire tied Red wire
to VDD
tied to VSS
(Default)
OPEN
Red wire
floating
(not
recommended)
Black wire
tied to VDD
Black wire
floating
(not
recommended)
Note: Normally VDD in USB application
JP2
Power wire in USB cable
thru J2 (and J1 not
mounted) connector
Jumper BLACK to VSS –
recommended
Black wire
tied to VSS
(Default)
Note: Normally VSS in USB application
mini USB
pin 1
RED WIRE
pin 2
+
_
pin 3
J2
NO connect
pin 4
pin 5
top side view
(mounted on component side)
BLACK WIRE
The following picture depicts a typical example of the LVDSe serial stream. This
snapshot was taken with a differential probe across the 100 ohm termination resistor R1
on the DS90C124 Rx evaluation board. R1 is the termination resistor to the RxIN +/-.
Note: The scope was triggered, with a separate probe, on TCLK, the input clock into the
DS90C241 Tx. To view the serial stream correctly, do not trigger on the probe
monitoring the serial stream.
National Semiconductor Corporation
Date: 2/27/2008
Page 15 of 39
Rx LVDS Pinout and LVCMOS by Connector
The following three tables illustrate how the Rx outputs are mapped to the IDC
connector J1, the mini USB LVDS connector J2, and the mini USB LVDS connector J3
pinouts. Note – labels are also printed on the evaluation boards for both the LVDS
inputs and 3.3V_LVCMOS outputs.
J1
J2
(topside)
J1
(bottom side)
LVDS OUTPUT
(not mounted)
LVCMOS OUTPUT
pin no.
name
name
pin no.
1
ROUT0
GND
2
pin no.
name
3
ROUT1
GND
4
1
JP1
pin no.
name
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
ROUT2
GND
ROUT3
GND
ROUT4
GND
ROUT5
GND
2
3
4
5
DOUT+
DOUTNC
JP2
ROUT6
GND
5
4
3
2
1
JP2
NC
DOUTDOUT+
JP1
ROUT7
GND
ROUT8
GND
ROUT9
GND
ROUT10
GND
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
ROUT11
GND
RCLK
GND
ROUT12
GND
ROUT13
GND
ROUT14
GND
ROUT15
GND
ROUT16
GND
ROUT17
GND
ROUT18
GND
ROUT19
GND
ROUT20
GND
ROUT21
GND
ROUT22
GND
ROUT23
GND
National Semiconductor Corporation
LVDS OUTPUT
Date: 2/27/2008
Page 16 of 39
BOM (Bill of Materials) De-serializer PCB:
DS90C124 Rx USB Demo Board - Board Stackup Revised: Thursday, March 23, 2006
DS90C124 Rx USB Demo Board
Revision: 1
Bill Of Materials
March 23,2006
19:19:22
Item
Qty
1
2
3
4
5
2
1
1
1
26
6
8
7
8
8
8
9
10
11
12
13
14
15
16
17
18
2
1
1
1
1
2
1
1
3
8
19
20
1
1
Reference
Part
PCB Footprint
C2,C1
C3
C4
C5
C6,C7,C8,C9,C10,C11,C12,
C13,C14,C15,C16,C17,C18,
C19,C20,C21,C22,C23,C24,
C25,C26,C27,C28,C29,C30,
C39
C31,C32,C33,C38,C43,C49,
C54,C55
C34,C37,C40,C44,C45,C48,
C52,C53
C35,C36,C41,C42,C46,C47,
C50,C51
JP2,JP1
JP3
J1
J2
J3
J4,J5
R1
R2
R3,R4,R5
R7,R8,R9,R10,R11,R12,R13,
R14
S1
U1
0.1uF
2.2uF
22uF
0.1uF
open0402
CAP/HDC-0402
3528-21_EIA
CAP/N
CAP/HDC-1206
CAP/HDC-0402
22uF
CAP/EIA-B 3528-21
0.1uF
CAP/HDC-0603
0.01uF
CAP/HDC-0603
3-Pin Header
2-Pin Header
mini USB 5pin_open
mini USB 5pin
IDC2X25_Unshrouded
BANANA
100 ohm,0402
10K_open
10K
0 Ohm,0402
Header/3P
Header/2P
mini_USB_surface_mount
mini_USB_surface_mount
IDC-50
CON/BANANA-S
RES/HDC-0402
RES/HDC-0805
RES/HDC-0805
RES/HDC-0402
SW DIP-4
DS90C124
DIP-4
48 pin TQFP
National Semiconductor Corporation
Date: 2/27/2008
Page 17 of 39
Typical Connection and Test Equipment
The following is a list of typical test equipment that may be used to generate signals for
the TX inputs:
1) Digital Video Source – for generation of specific display timing such as Digital Video
Processor or Graphics Controller with digital RGB (3.3V_LVCMOS) output.
2) Astro Systems VG-835 - This video generator may be used for video signal sources
for 18-bit Digital 3.3V_LVCMOS/RGB.
3) Any other signal / video generator that generates the correct input levels as specified
in the datasheet.
4) Optional – Logic Analyzer or Oscilloscope
The following is a list of typical test equipment that may be used to monitor the input
and output signals from the RX:
1) LCD Display Panel which supports digital RGB (3.3V_LVCMOS) inputs.
2) Logic Analyzer or Oscilloscope
3) Any SCOPE with a bandwidth of at least 35MHz for 3.3V_LVCMOS and/or 1GHz for
looking at the differential signal.
LVDS signals may be easily measured with high impedance / high bandwidth differential
probes such as the TEK P6247 or P6248 differential probes.
National Semiconductor Corporation
Date: 2/27/2008
Page 18 of 39
The picture below shows a typical test set up using a Graphics Controller and LCD
Panel.
Figure 4. Typical SERDES Setup of LCD Panel Application
The picture below shows a typical test set up using a generator and scope.
Transmitter
Board
DIGITAL
VIDEO
GENERATOR
DIGITAL VIDEO GENERATOR
Digital Video Source
Receiver
Board
Digital RGB
Digital RGB
LVDS Interface
Cable
Contents of Demo Kit
Logic Analyzer / Oscilloscope
Figure 5. Typical SERDES Test Setup for Evaluation
National Semiconductor Corporation
Date: 2/27/2008
Page 19 of 39
Typical Connection Diagram Tx – User Quick Reference
DS90C241 (SER)
VDDDR
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
LVCMOS
Parallel
Interface
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DIN23
3.3V
TPWDNB = System GPO
DEN = High (ON)
TRFB = High (Rising edge)
VODSEL = Low (400mV)
PRE = Rpre
RESRVD = Low
DCAOFF = Low
DCBOFF = Low
C1
C4
C2
C5
C3
C6
VDDPT0
VDDPT1
VDDIT
VDDL
VDDT
DOUT+
C7
DOUTTPWDNB
DEN
TRFB
DCAOFF
DCBOFF
VODSEL
PRE
RESRVD
Serial
LVDS
Interface
R1
TCLK
GPO
3.3V
VSSDR
VSSPT0
VSSPT1
VSST
VSSL
VSSIT
VSS
R2
C8
C1 to C3 = 0.1 F
C4 to C6 = 0.01 F
C7 = 100 nF; 50WVDC, NPO or X7R
C8 = 100 nF; 50WVDC, NPO or X7R
R1 = 100
R2 = Open (OFF) or Rpre 3 k (ON) (cable specific)
Note:
VDDs can be combined into a minimum of three (3) groupings as shown:
Analog-LVDS, Analog-PLL/VCO, Digital
Decoupling specified (C1-C6) is the minimum that should be used.
Figure 6. Typical DS90C241 Tx SERDES Hookup
National Semiconductor Corporation
Date: 2/27/2008
Page 20 of 39
Typical Connection Diagram Rx – User Quick Reference
DS90C124 (DES)
3.3V
VDDIR
C5
C6
VDDOR1
VDDOR2
VDDOR3
C7
C9
RIN+
Serial
LVDS
Interface
R1
RINC10
3.3V
RPWDNB
REN
RRFB
RPWDNB = System GPO
REN = High (ON)
RRFB = High (Rising edge)
RESRVD = Low
RESRVD
3.3V
C1
C2
C3
C4
VDDR0
VDDR1
C8
C1 to C8 = 0.1 F to 0.01 F
C9 = 100 nF; 50 WVDC, NPO or X7R
C10 = 100 nF; 50 WVDC, NPO or X7R
R1 = 100
GPO
VDDPR0
VDDPR1
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
LVCMOS
Parallel
Interface
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
ROUT21
ROUT22
ROUT23
RCLK
LOCK
Note:
VDDs can be combined into a minimum of four (4) groupings as shown above:
Analog-PLL/VCO, Digital-Logic, Analog-LVDS, Digital-LVCMOS O/P
Decoupling specified (C1-C8) is the minimum that should be used.
Figure 7. Typical DS90C124 Rx SERDES Hookup
National Semiconductor Corporation
Date: 2/27/2008
Page 21 of 39
Troubleshooting Demo Setup
NOTE: The DS90C241 and DS90C124 are NOT USB compliant and should not be
plugged into a USB device nor should a USB device be plugged into the
evaluation boards.
If the evaluation boards are not performing properly, use the following as a guide for
quick solutions to potential problems. If the problem persists, please contact the local
Sales Representative for assistance.
QUICK CHECKS:
1. Check that Powers and Grounds are connected to both Tx AND Rx boards.
2. Check the supply voltage (typical 3.3V) and also current draw with both Tx and Rx
boards. The Serializer board should draw about 40-50mA with clock and all data
bits switching at 35MHz. The De-serializer board should draw about 70-80mA with
clock and all data bits switching at 35MHz.
3. Verify input clock and input data signals meet requirements (VIL, VIH, tset, thold),
Also verify that data is strobed on the selected rising/falling (RFB pin) edge of the
clock.
4. Check that the Jumpers and Switches are set correctly.
5. Check that the cable is properly connected.
TROUBLESHOOTING CHART
Problem…
There is only the output clock.
Solution…
Make sure the data is applied to the correct input pin.
There is no output data.
Make sure data is valid at the input.
No output data and clock.
Make sure Power is on. Input data and clock are
active and connected correctly.
Power, ground, input data and
input clock are connected
correctly, but no outputs.
The devices are pulling more
than 1A of current.
After powering up the
evaluation boards, the power
supply reads less than 3V
when it is set to 3.3V.
Make sure that the cable is secured to both
evaluation boards.
Check the Power Down pins of both Serializer and
De-serializer boards to make sure that the devices
are enabled (/PD=VDD) for operation. Also check
DEN on the Serializer board and REN on the
Deserializer board is set HIGH.
Check for shorts in the cables connecting the TX and
RX boards.
Use a larger power supply that will provide enough
current for the evaluation boards, a 500mA minimum
power supply is recommended.
National Semiconductor Corporation
Date: 2/27/2008
Page 22 of 39
Note: Please note that the following references are supplied only as a courtesy to our
valued customers. It is not intended to be an endorsement of any particular equipment
or hardware supplier.
Equipment References
Digital Video Pattern Generator – Astro Systems VG-835 (or equivalent):
Astro Systems
425 S. Victory Blvd. Suite A
Burbank, CA 91502
Phone: (818) 848-7722
Fax: (818) 848-7799
www.astro-systems.com
Extra Component References
TDK Corporation of America
1740 Technology Drive, Suite 510
San Jose, CA 95110
Phone: (408) 437-9585
Fax: (408) 437-9591
www.component.tdk.com
Optional EMI Filters – TDK Chip Beads (or equivalent)
Cable References
The LVDS interface cable included in the kit is a standard off-the-shelf high-speed USB
2.0 with a 4-pin USB A type on one end and a 5-pin mini USB on the other end and is
included for demonstration purposes only.
NOTE: The DS90C241 and DS90C124 are NOT USB compliant and should not be
plugged into a USB device nor should a USB device be plugged into the
evaluation boards.
The inclusion of the USB cable in the kit is for:
1) Demonstrating the robustness of the LVDS link over ordinary twisted pair data cables.
2) Readily available and in different lengths without having custom cables made.
- For optimal performance, we recommend Shielded Twisted Pair (STP) 100Ω
differential impedance cable for high-speed data applications.
National Semiconductor Corporation
Date: 2/27/2008
Page 23 of 39
Appendix
Serializer (Tx) PCB Schematic:
National Semiconductor Corporation
Date: 2/27/2008
Page 24 of 39
National Semiconductor Corporation
Date: 2/27/2008
Page 25 of 39
National Semiconductor Corporation
Date: 2/27/2008
Page 26 of 39
National Semiconductor Corporation
Date: 2/27/2008
Page 27 of 39
De-serializer (Rx) PCB Schematic:
National Semiconductor Corporation
Date: 2/27/2008
Page 28 of 39
National Semiconductor Corporation
Date: 2/27/2008
Page 29 of 39
National Semiconductor Corporation
Date: 2/27/2008
Page 30 of 39
National Semiconductor Corporation
Date: 2/27/2008
Page 31 of 39
Serializer (Tx) PCB Layout:
TOP VIEW
BOTTOMSIDE VIEW
National Semiconductor Corporation
Date: 2/27/2008
Page 32 of 39
PRIMARY COMPONENT SIDE – LAYER 1
GROUND PLANE (VSS) – LAYER 2
POWER PLANE (VDD) – LAYER 3
SECONDARY COMP SIDE – LAYER 4
PRIMARY COMP SIDE – SOLDER MASK (LAYER 1)
SECONDARY COMP SIDE – SOLDER MASK (LAYER 4)
National Semiconductor Corporation
Date: 2/27/2008
Page 33 of 39
PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1)
PRIMARY COMP SIDE – SILKSCREEN (LAYER 1)
SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4)
SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4)
National Semiconductor Corporation
Date: 2/27/2008
Page 34 of 39
Serializer (Tx) PCB Stackup:
National Semiconductor Corporation
Date: 2/27/2008
Page 35 of 39
Deserializer (Rx) Demo PCB Layout:
TOP VIEW
BOTTOMSIDE VIEW
National Semiconductor Corporation
Date: 2/27/2008
Page 36 of 39
PRIMARY COMPONENT SIDE – LAYER 1
GROUND PLANE (VSS) – LAYER 2
SECONDARY COMP SIDE – LAYER 4
PRIMARY COMP SIDE – SOLDER MASK (LAYER 1)
National Semiconductor Corporation
POWER PLANE (VDD) – LAYER 3
SECONDARY COMP SIDE – SOLDER MASK (LAYER 4)
Date: 2/27/2008
Page 37 of 39
PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1) SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4)
PRIMARY COMP SIDE – SILKSCREEN (LAYER 1)
SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4)
National Semiconductor Corporation
Date: 2/27/2008
Page 38 of 39
Deserializer (Rx) PCB Stackup:
National Semiconductor Corporation
Date: 2/27/2008
Page 39 of 39
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