SM72240MF-3.08/NOPB

SM72240 www.ti.com SNIS154C – JANUARY 2011 – REVISED APRIL 2013 SM72240 SolarMagic 5-Pin Microprocessor Reset Circuit Check for Samples: SM72240 FEATURES DESCRIPTION • • • The SM72240 microprocessor supervisory circuit monitors the power supplies in microprocessor and digital systems. It provides a reset to the microprocessor during power-up, power-down, brown-out conditions, and manual reset. 1 2 • • • • • Renewable Energy Grade Precise monitoring of 5V supply voltages Fully specified over temperature – −40°C to +125°C 100 ms minimum Power-On Reset pulse width, 190 ms typical: – Active-Low RESET Open Drain Output RESET Output valid for VCC ≥ 1V Low Supply Current, 6µA typical Power supply transient immunity Compatible with MAX811/812 applications APPLICATIONS • • • • • Microprocessor Systems Computers Controllers Intelligent Instruments Portable/Battery-Powered Equipment The SM72240 asserts a reset signal whenever the supply decreases below the factory-programmed reset threshold. Reset will be asserted for at least 100ms even after VCC rises above the reset threshold. The SM72240 has an active-low open-drain RESET output. The SM72240 is suitable for monitoring 5V. With a low supply current of only 6µA, the SM72240 is ideal for use in portable equipment. The SM72240 is available in the 5-pin SOT-23 package. Typical Application Circuit VCC VCC VCC RL PP SM72240 MR PUSHBUTTON SWITCH RESET GND RESET INPUT GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated SM72240 SNIS154C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Connection Diagram 5 VCC GND 1 GND 2 RESET SM72240 3 4 MR Figure 1. 5-Pin SOT-23 Package See Package Number DBV PIN DESCRIPTIONS Pin Name Function 1 GND Ground reference 2 GND Ground reference, device substrate, connect to ground. 3 RESET 4 MR Active-low input. Reset is asserted whenever this pin is pulled low and remains asserted for 190 ms after the MR pin goes high. May be left open. 5 VCC Supply Voltage (+5V, nominal) Active-low output. RESET remains low while VCC is below the reset threshold voltage, and for 190 ms after VCC rises above the reset threshold voltage. Block Diagram Figure 2. SM72240 Block Diagram VCC Reset Comparator + 22k Low Line Comparator Reset Logic and One-Shot Timer RESET Manual Reset Comparator + MR 1.225V Reference These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SM72240 SM72240 www.ti.com SNIS154C – JANUARY 2011 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) −0.3V to 6.0V VCC, MR −0.3V to (VCC+ 0.3V) RESET, RESET Input Current, VCC Pin 20mA Output Current, RESET, RESET Pin 20mA ESD Rating (3) 2kV SOT-23 (4) Continuous Power Dissipation (TA = +70°C) 320mW −40°C to +125°C Operating Temperature Range Maximum Junction Temperature 125°C −65°C to +160°C Storage Temperature Range Lead Temperature (soldering, 10sec) (1) (2) (3) (4) +300°C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the device operates correctly. Operating ratings do not imply specified performance limits. For performance limits and associated test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. At elevated temperatures, devices must be derated based on package thermal resistance. The device must be derated at 4.5mW/°C at ambient temperatures above 70°C. The device has internal thermal protection. Electrical Characteristics Typical values are at TA = +25°C. Limits with standard typeface are for TA = +25°C, and limits in boldface type apply for the operating temperature range −40°C to +125°C , unless otherwise noted. (1) Symbol VCC ICC VTH VTH Tempco Parameter Conditions Min VCC Range Supply Current (ILOAD = 0A) 15 SM72240-3.08 VCC = 3.6V 7 10 SM72240-4.63 4.54 4.50 4.63 4.72 4.75 SM72240-3.08 3.03 3.00 3.08 3.14 3.15 VCC = VTH to (VTH − 100mV) tRP Reset Active Timeout Period 100 MR Minimum Pulse Width 10 tMD MR to Reset Propagation Delay MR Glitch Immunity (3) VIL MR Input Threshold VCC > VTH(MAX) MR Pull-Up Resistance VOL IIN (1) (2) (3) RESETOutput Voltage Low RESET Output Leakage Current (SM72240) V 8 tMR VIH Units 5.5 VCC = 5.5V Reset Threshold Temperature Coefficient VCC to Reset Delay (2) Max SM72240-4.63 Reset Threshold tRD Typ 1.0 µA V 30 ppm/°C 20 µs 190 560 µs 2 µs 100 ns 2.3 0.8 22 V kΩ VCC = VTH min, ISINK = 3.2 mA 0.4 VCC > 1V, ISINK = 50µA 0.3 VCC > VTH, RESET = 5.5V ms 0.5 V µA Production testing done at TA = +25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. RESET output. Glitches of 100 ns or less typically will not generate a reset pulse. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SM72240 3 SM72240 SNIS154C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Supply Current vs VCC Supply Current vs Temperature 10 9 VCC = 5.5V 8 6 ICC (PA) 8 SUPPLY CURRENT (PA) 7 5 4 3 2 6 VCC = 3.6V 4 VCC = 2.5V 2 1 0 -40 0 1 0 2 4 3 6 5 -15 35 60 TEMPERATURE (oC) Figure 3. Figure 4. Reset Timeout vs VCC 85 Reset Timeout vs Temperature 1.05 210 200 RESET TIMEOUT (ms) NORMALIZED RESET TIMEOUT 10 VCC (V) 1.025 1 0.975 190 180 170 160 150 -40 0.95 2 3 4 5 6 -20 0 20 40 60 80 TEMPERATURE (oC) VCC (V) Figure 5. Figure 6. Normalized VTH vs Temperature VOL vs Current 700 1.005 1.004 VCC = 2.5V 600 500 VCC = 3.3V 1.001 VOL (mV) NORMALIZED VTH 1.003 1.002 1.000 0.999 400 VCC = 5V 300 200 0.998 0.997 100 0.996 0.995 -40 -20 40 0 20 60 TEMPERATURE (oC) 80 Figure 7. 4 0 0.1 0.3 3.0 1.0 SINK CURRENT (mA) 10.0 Figure 8. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SM72240 SM72240 www.ti.com SNIS154C – JANUARY 2011 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Low VCC Characteristics 700 RESET VOLTAGE (mV) 600 10 k: Pull-Up Resistor 500 400 300 200 100 0 0.0 0.5 1.0 1.5 2.0 VCC (V) Figure 9. Timing Diagram Figure 10. CIRCUIT INFORMATION RESET OUTPUT The reset input of a µP initializes the device into a known state. The SM72240 microprocessor voltage monitoring circuit asserts a forced reset output to prevent code execution errors during power-up, power-down, and brownout conditions. RESET is valid for VCC ≥ 1V. Once VCC exceeds the reset threshold, an internal timer maintains the output for the reset timeout period. After this interval, reset goes high and the microprocessor initializes itself into a known state. RESET is active low. As VCC drops below the reset threshold (such as during a brownout), the reset activates (see the NEGATIVEGOING VCC TRANSIENTS section). When VCC again rises above the reset threshold, the internal timer starts. Reset holds until VCC exceeds the reset threshold for longer than the reset timeout period. After this time, reset releases. Additionally, the Manual Reset input (MR) will initiate a forced reset. See the MANUAL RESET INPUT (MR) section. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SM72240 5 SM72240 SNIS154C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com The SM72240 reset output ignores short duration glitches on VCC and MR. See the Applications Information section for details. RESET THRESHOLD The SM72240 is available with a reset voltage of 4.63V or 3.08V which are suitable for monitoring 5.0V or 3.3V supplies respectively. MANUAL RESET INPUT (MR) Many µP-based products require a manual reset capability, allowing the operator to initiate a reset. The MR input is fully debounced and provides an internal 22 kΩ pull-up. When the MR input is pulled below VIL (0.25VCC) for more than 100 ns, reset is asserted after a typical delay of 2 µs. Reset remains active as long as MR is held low, and releases after MR rises above VIH and the reset timeout period expires. Use MR with digital logic to assert reset or to daisy chain supervisory circuits. Applications Information BENEFITS OF PRECISION RESET THRESHOLDS A microprocessor supply supervisor must provide a reset output within a predictable range of the supply voltage. A common threshold range is between 5% and 10% below the nominal supply voltage. The SM72240 uses highly accurate circuitry to ensure that the reset threshold occurs only within this range (for 5.0V and 3.3V supplies). Table 1 shows how the standard reset threshold applies to 5.0V and 3.3V nominal supply voltages. Table 1. Monitored Tolerance Table Supply Voltage Reset Threshold 3.3V 5.0V 4.63 ± % 90.8-94.4% 3.08 ± % 91.8–95.2% ENSURING A VALID RESET OUTPUT DOWN TO VCC = 0V When VCC falls below 1V, the SM72240 RESET output is unable to sink the rated current. A high-impedance CMOS logic input connected to RESET can therefore drift to undetermined voltages. To prevent this situation, a 100kΩ resistor should be connected from the RESET output to ground, as shown in Figure 11. Figure 11. Circuit for RESET Valid from VCC = 0V OPEN DRAIN OUTPUT An open drain output allows easy paralleling of multiple microprocessor reset circuits without requiring additional logic gates. Open drain outputs also allow interfacing devices of differing logic levels or families, since the output pull-up resistor may be connected to any supply voltage up to 5.5V, regardless of VCC. The pull up resistor is calculated so that maximum current flow into RESET is less than 10 mA when activated. The resistor must be small enough so that the leakage current of all connected devices does not create an excessive voltage drop when the output is not activated. A resistor value of 100 kΩ will generally suffice. 6 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SM72240 SM72240 www.ti.com SNIS154C – JANUARY 2011 – REVISED APRIL 2013 NEGATIVE-GOING VCC TRANSIENTS The SM72240 is relatively immune to short negative-going transients or glitches on VCC. Figure 12 shows the maximum pulse width a negative-going VCC transient can have without causing a reset pulse. In general, as the magnitude of the transient increases, going further below the threshold, the maximum allowable pulse width decreases. Typically, a VCC transient that goes 125 mV below the reset threshold and lasts 40 µs or less will not cause a reset pulse. A 0.1 µF bypass capacitor mounted as close as possible to the VCC pin will provide additional transient rejection. 600 Overdrive (mV) 500 400 300 200 100 0 0 20 40 60 80 100 120 140 160 180 200 Max Transient Duration (Ps) Figure 12. Maximum Transient Duration without Causing a Reset Pulse vs. Reset Comparator Overdrive Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SM72240 7 SM72240 SNIS154C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 8 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 7 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SM72240 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SM72240MF-3.08/NOPB NRND SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 R133 SM72240MF-4.63/NOPB NRND SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2240 SM72240MFE-3.08/NOPB NRND SOT-23 DBV 5 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 R133 SM72240MFE-4.63/NOPB NRND SOT-23 DBV 5 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2240 SM72240MFX-3.08/NOPB NRND SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 R133 SM72240MFX-4.63/NOPB NRND SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2240 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of