SN65CML100DGKG4

SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES • • • • • • • • • • DESCRIPTION Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML Signaling Rates(1) up to 1.5 Gbps CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V Supplies Total Jitter < 70 ps Low 100 ps (Max) Part-To-Part Skew Wide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range Propagation Delay Times, 800 ps Maximum 3.3-V Supply Operation Available in SOIC and MSOP Packages APPLICATIONS • • • • • Level Translation 622-MHz Central Office Clock Distribution High-Speed Network Routing Wireless Basestations Low Jitter Clock Repeater (1) (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). A B 8 4 2 7 6 3 The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01-µF capacitor and limit the current sourcing or sinking to 400 µA. When not used, VBB should be left open. This device is characterized for operation from –40°C to 85°C. EYE PATTERN FUNCTIONAL DIAGRAM VCC This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50-Ω or 25-Ω loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA-644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion. VBB 1.5 Gbps 223-1 PRBS Y Z Vertical Scale = 500 mV/div 750 MHz Horizontal Scale = 200 ps/div VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 50 Ω Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–TBD, Texas Instruments Incorporated SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER PART MARKING PACKAGE STATUS CML100 SOIC Production NWB MSOP Production SN65CML100D SN65CML100DGK ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT VCC Supply voltage range (2) IBB Sink/source –0.5 V to 4 V ±0.5 mA Voltage range, (A, B, Y, Z) Electrostatic discharge 0 V to 4.3 V Human Body Model Charged-Device (3) Model (4) A, B, Y, Z, and GND ±5 kV All pins ±2 kV ±1500 V All pins Continuous power dissipation Tstg See Dissipation Rating Table Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) (4) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A.7. Tested in accordance with JEDEC Standard 22, Test Method C101. RECOMMENDED OPERATING CONDITIONS VCC MIN NOM MAX 3 3.3 3.6 3.3-V nominal supply at terminator 3 3.3 3.6 2.5-V nominal supply at terminator 2.375 2.5 2.625 1.8-V nominal supply at terminator 1.7 1.9 V 0.1 1 V Supply voltage VTT Terminator supply voltage |VID| Magnitude of differential input voltage Input voltage (any combination of common-mode or input signals) VBB Output current TA Operating free-air temperature 0 –40 UNIT 4 V µA 85 °C 2 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING DGK 425 mW 3.4 mW/°C 221 mW D 725 mW 5.8 mW/°C 377 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. Submit Documentation Feedback V 400 PACKAGE DISSIPATION RATINGS (1) V SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 DEVICE CHARACTERISTICS PARAMETER ICC Supply current, device only VBB Switching reference voltage (1) (1) MIN NOM MAX UNIT 9 12 mA 1890 1950 2010 mV VBB parameter varies 1:1 with VCC INPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER Positive-going differential input voltage threshold VIT+ mV –100 VID(HYS) Differential input voltage hysteresis,VIT+ – VIT– 25 VI = 0 V or 2.4 V, Second input at 1.2 V II Input current (A or B inputs) II(OFF) Power off input current (A or B inputs) –20 Input offset current (|IIA - IIB|) Ci Differential input capacitance (1) mV 20 VI = 4 V, Second input at 1.2 V 33 VCC = 1.5 V, VI = 0 V or 2.4 V, Second input at 1.2 V –20 20 VCC = 1.5 V, VI = 4 V, Second input at 1.2 V IIO UNIT 100 See Figure 1 and Table 1 Negative-going differential input voltage threshold VIT- MIN TYP (1) MAX TEST CONDITIONS µA µA 33 VIA = VIB, 0 ≤ VIA ≤ 4 V –6 6 VI = 0.4 sin (4E6πt) + 0.5 V 3 VCC = 0 V 3 µA pF All typical values are at 25°C and with a 3.3-V supply. OUTPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER voltage (2) VOH Output high VOL Output low voltage (2) |VOD| Differential output voltage magnitude VOH Output high voltage (3) VOL Output low voltage (3) |VOD| Differential output voltage magnitude VOH Output high voltage (2) VOL Output low voltage (2) |VOD| Differential output voltage magnitude VOH Output high voltage (3) VOL Output low voltage (3) |VOD| Differential output voltage magnitude Co Differential output capacitance (1) (2) (3) TEST CONDITIONS RT = 50 Ω, VTT = 3 V to 3.6 V or VTT = 2.5 V ±5%, See Figure 2 RT = 25 Ω, VTT = 3 V to 3.6 V or VTT = 2.5 V ±5%, See Figure 2 RT = 50 Ω, VTT = 1.8 V ±5%, See Figure 2 RT = 25 Ω, VTT = 1.8 V ±5%, See Figure 2 MIN TYP (1) MAX VTT–60 VTT–10 VTT mV VTT–1100 VTT–800 VTT–640 mV 640 780 1000 mV VTT–60 VTT–10 VTT mV VTT–550 VTT–400 VTT–320 mV 320 390 500 mV VTT–170 VTT–10 VTT mV VTT–1100 VTT–800 VTT–640 mV 570 780 1000 mV VTT–85 VTT–10 VTT mV VTT–500 VTT–400 VTT–320 mV 285 390 500 mV VI = 0.4 sin (4E6πt) + 0.5 V 3 VCC = 0 V 3 UNIT pF All typical values are at 25°C and with a 3.3-V supply. Outputs are terminated through 50-Ω resistors to VTT, CML level specifications are referenced to VTT and tracks 1:1 with variation of VTT. Outputs are terminated through 25-Ω resistors to VTT; CML level specifications are referenced to VTT and tracks 1:1 with variation of VTT. Submit Documentation Feedback 3 SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tr Differential output signal rise time (20%–80%) tf Differential output signal fall time (20%–80%) (|tPHL– tPLH|) (2) skew (3) RT = 50 Ω or RT = 25 Ω, SeeFigure 4 tsk(p) Pulse skew tsk(pp) Part-to-part tjit(per) Period jitter, rms (1 standard deviation) (4) 750 MHz clock input (5) tjit(cc) Cycle-to-cycle jitter (peak)(4) 750 MHz clock input (6) jitter(4) tjit(pp) Peak-to-peak tjit(det) Deterministic jitter, peak-to-peak(4) (1) (2) (3) (4) (5) (6) (7) (8) 4 MIN NOM ( MAX UNIT 250 800 ps 250 800 ps 300 ps 300 ps 1) 0 50 ps 100 ps 1 5 ps 8 27 ps input (7) 30 70 ps 1.5 Gbps 27–1 PRBS input (8) 25 65 ps VID = 0.2 V 1.5 Gbps 223-1 PRBS All typical values are at 25°C and with a 3.3-V supply. tsk(p) is the magnitude of the time difference between the tPLH and tPHL. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Jitter parameters are ensured by design and characterization. Measurements are made with a Tektronix TDS6604 oscilloscope runningTektronix TDSJIT3 software. Agilent E4862B stimulus system jitter 2 ps tjit(per), 16 ps tjit(cc), 25 ps tjit(pp), and 10 ps tjit(det) has beensubtracted from the values. VID = 200 mV, 50% duty cycle, VIC = 1.2 V, tr = tf ≤ 25 ns (20% to 80%), measured over 1000 samples. VID = 200 mV, 50% duty cycle, VIC = 1.2 V, tr = tf ≤ 25 ns (20% to 80%). VID = 200 mV, VIC = 1.2 V, tr = tf ≤ 0.25 ns (20% to 80%), measured over 100k samples. VID = 200 mV, VIC = 1.2 V, tr = tf ≤ 0.25 ns (20% to 80%). Deterministic jitter is sum of pattern dependent jitter and pulse width distortion. Submit Documentation Feedback SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION IIA A Y B Z VID VIA+VIB VIC VOD VIA VIB 2 VOY VOY+VOZ VOZ IIB 2 Figure 1. Voltage and Current Definitions Table 1. Maximum Receiver Input Voltage Threshold APPLIED VOLTAGES (1) RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE VID VIC OUTPUT (1) VIA VIB 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.2 V L 4.0 V 3.9 V 100 mV 3.95 V H 3.9 V 4. 0 V –100 mV 3.95 V L 0.1 V 0.0 V 100 mV 0.5 V H 0.0 V 0.1 V –100 mV 0.5 V L 1.7 V 0.7 V 1000 mV 1.2 V H 0.7 V 1.7 V –1000 mV 1.2 V L 4.0 V 3.0 V 1000 mV 3.5 V H 3.0 V 4.0 V –1000 mV 3.5 V L 1.0 V 0.0 V 1000 mV 0.5 V H 0.0 V 1.0 V –1000 mV 0.5 V L H H = high level, L = low level Y RT VOD RT Z VOY + _ VTT VOZ Figure 2. Output Voltage Test Circuit Y VOD Driver Device Receiver Device Z RT1 RT2 RT1 = RT2 = RT VTT Figure 3. Typical Termination for Output Driver Submit Documentation Feedback 5 SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 RT1 A Y 1 pF VID VIA B VOY Z VIB VTT RT2 VIA 1.4 V VIB 1V VID 0.4 V 0V -0.4 V RT1 = RT2 = RT VOZ tPHL tPLH 100% 0V 80% VOY - VOZ 20% tf 0% tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.Measurement equipment provides a bandwidth of 5 GHz minimum. Figure 4. Timing Test Circuit and Waveforms PIN ASSIGNMENTS D AND DGK PACKAGE (TOP VIEW) NC A B VBB 1 8 VCC 2 7 Y 3 6 Z 4 5 GND Table 2. PIN DESCRIPTIONS PIN FUNCTION A, B Differential inputs Y, Z Differential outputs VBB Reference voltage output VCC Power supply GND Ground NC No connect Table 3. FUNCTION TABLE DIFFERENTIAL INPUT (1) 6 OUTPUTS (1) VID = VA– VB Y Z VID ≥ 100 mV H L –100 mV < VID < 100 mV ? ? VID ≤ –100 mV L H Open ? ? H = high level, L = low level, ? = intermediate Submit Documentation Feedback SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS OUTPUT INPUT VCC VCC A VCC VCC B Y Z 7V 7V 7V 7V TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE 12 10 10 8 6 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 200 mV, RT = 50 Ω, VTT = 2.5 V 4 2 0 1000 8 6 VCC = 3.3 V, VIC = 1.2 V, VID = 200 mV, f = 750 MHz, RT = 50 Ω, VTT = 2.5 V 4 2 0 0 250 500 750 −40 1000 −20 0 20 40 60 80 900 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 200 mV, RT = 50 Ω VTT = 3.3 V 800 700 VTT = 1.7 V VTT = 2.5 V 600 500 100 100 TA − Free-Air Temperature − °C f − Frequency − MHz 200 300 400 500 600 f − Frequency − MHz 700 Figure 5. Figure 6. Figure 7. DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY PROPAGATION DELAY TIME vs COMMON-MODE INPUT VOLTAGE PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE VTT = 3.3 V 400 VTT = 2.5 V 350 VTT = 1.7 V 300 250 100 VCC = 3.3 V, TA = 25°C, VID = 200 mV f = 25 MHz, RT = 50 Ω, VTT = 2.5 V 475 450 t pd − Propagation Delay Time − ps t pd − Propagation Delay Time − ps 450 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 200 mV, RT = 25 Ω tPLH 425 tPHL 400 375 350 200 300 400 500 600 f − Frequency − MHz Figure 8. 700 800 800 500 500 500 V OD − Differential Output Voltage − mV DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY V OD − Differential Output Voltage − mV 12 I CC − Supply Current − mA I CC − Supply Current − mA SUPPLY CURRENT vs FREQUENCY 0 0.5 1 1.5 2 2.5 3 3.5 VIC − Common Mode Input Voltage − V Figure 9. Submit Documentation Feedback 4 475 450 425 VCC = 3.3 V, VIC = 1.2 V, VID = 200 mV, f = 25 MHz, RT = 50 Ω, VTT = 2.5 V tPHL tPLH 400 375 350 −40 −20 0 20 40 60 80 100 TA− Free-Air Temperature − °C Figure 10. 7 SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 TYPICAL CHARACTERISTICS (continued) PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE PEAK-TO-PEAK JITTER vs FREQUENCY 30 625 600 575 25 tPHL 550 35 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, RT = 50 Ω, VTT = 2.5 V, Input = Clock tPLH 20 15 VID = 0.3 V 10 VID = 0.5 V 5 525 500 −40 −20 0 20 40 60 80 VID = 0.8 V 25 20 VID = 0.5 V 15 10 VID = 0.3 V 5 0 100 100 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 0.8 V RT = 50 Ω, VTT = 2.5 V Input = 223−1 PRBS 30 Peak-To-Peak Jitter − ps VCC = 3.3 V, VIC = 1.2 V, VID = 200 mV, RT = 50 Ω, VTT = 1.7 V, f = 25 MHz Peak-To-Peak Jitter − ps 200 300 400 500 600 700 0 200 800 400 f − Frequency − MHz TA− Free-Air Temperature − °C 600 800 1000 1200 1400 1600 Data Rate − Mbps Figure 11. Figure 12. Figure 13. PEAK-TO-PEAK JITTER vs COMMON MODE INPUT VOLTAGE PEAK-TO-PEAK JITTER vs COMMON MODE INPUT VOLTAGE PEAK-TO-PEAK JITTER vs DATA RATE 60 30 VCC = 3.3 V, TA = 25°C, RT = 50 Ω, VTT = 2.5 V Input = Clock 20 50 Peak-To-Peak Jitter − ps 25 VID = 0.8 V 15 VID = 0.5 V 10 0 0.5 1 1.5 2 2.5 3 40 3.5 4 VID = 0.5 V 30 VID = 0.8 V 20 VIC − Common Mode Input Voltage − V Figure 14. 0.5 1 1.5 2 2.5 3 3.5 VIC − Common Mode Input Voltage − V 25 VTT = 1.7 V 20 15 VTT = 2.5 V 10 VTT = 3.3 V 5 200 0 0 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, |VID| = 200 mV, Input = 223−1 PRBS, RT = 50 Ω VID = 0.3 V 10 VID = 0.3 V 5 0 30 VCC = 3.3 V, TA = 25°C, RT = 50 Ω, VTT = 2.5 V Input = 223−1 PRBS Peak-To-Peak Jitter − ps t pd − Propagation Delay Time − ps 650 Peak-To-Peak Jitter − ps PEAK-TO-PEAK JITTER vs DATA RATE 4 400 600 800 1000 1200 1400 1600 Data Rate − Mbps Figure 15. Figure 16. PEAK-TO-PEAK JITTER vs DATA RATE Peak-To-Peak Jitter − ps 25 20 15 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 200 mV, Input = 223−1 PRBS, RT = 25 Ω 1.5 Gbps 223-1 PRBS VTT = 1.7 V Vertical Scale = 250 mV/div VTT = 2.5 V 10 750 MHz VTT = 3.3 V 5 200 400 600 800 Horizontal Scale = 200 ps/div 1000 1200 1400 1600 Data Rate − Mbps VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 25 Ω Figure 17. 8 Figure 18. Submit Documentation Feedback SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 TYPICAL CHARACTERISTICS (continued) 1.5 Gbps 223-1 PRBS 1.5 Gbps 223-1 PRBS Vertical Scale = 500 mV/div Vertical Scale = 250 mV/div 750 MHz 750 MHz Horizontal Scale = 200 ps/div VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 2.5 V, RT = 50 Ω Horizontal Scale = 200 ps/div VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 2.5 V, RT = 25 Ω Figure 19. Figure 20. 1.5 Gbps 223-1 PRBS 1.5 Gbps 223-1 PRBS Vertical Scale = 500 mV/div Vertical Scale = 250 mV/div 750 MHz 750 MHz Horizoontal Scale = 200 ps/div Horizoontal Scale = 200 ps/div VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 200 mV, VTT = 1.7 V, RT = 50 Ω VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 200 mV, VTT = 1.7 V, RT = 25 Ω Figure 21. Figure 22. Submit Documentation Feedback 9 SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 TYPICAL CHARACTERISTICS (continued) Power Supply 1 + 3.3 V - Power Supply 2 + VTT J3 DUT GND J2 EVM GND J1 VCC J4 J5 J6 100 Ω J7 50 Ω DUT Pattern Generator Matched Cables SMA to SMA 50 Ω Matched Cables SMA to SMA EVM Oscilloscope Figure 23. Jitter Setup Connections for SN65CML100 10 Submit Documentation Feedback SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 APPLICATION INFORMATION For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. When VBB is used, decouple VBB via a 0.01-µF capacitor and limit the current sourcing or sinking to 0.4 mA. When not used, VBB should be left open. TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.) 50 Ω 3.3 V or 5 V 3.3 V SN65CML100 A ECL B 50 Ω 50 Ω 50 Ω VTT = VCC -2 V VTT Figure 24. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) 50 Ω 3.3 V 3.3 V SN65CML100 A CML B 50 Ω VTT Figure 25. Current-Mode Logic (CML) 3.3 V 3.3 V 50 Ω SN65CML100 A ECL VBB B 50 Ω VTT VTT = VCC -2 V Figure 26. Single-Ended (LVPECL) 3.3 V or 5 V 50 Ω 3.3 V SN65CML100 A 100 Ω LVDS B 50 Ω Figure 27. Low-Voltage Differential Signaling (LVDS) Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 13-Jul-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN65CML100D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CML100 Samples SN65CML100DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NWB Samples SN65CML100DGKG4 ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NWB Samples SN65CML100DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NWB Samples SN65CML100DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CML100 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of