SN65DP149RSBR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN65DP149, SN75DP149 SLLSEL2C – SEPTEMBER 2015 – REVISED JULY 2016 SNx5DP149 3.4 Gbps DP++ to HDMI Retimer 1 Features 3 Description • The SNx5DP149 device is a dual mode[1] DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b output signals. The SNx5DP149 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link. The SNx5DP149 device supports data rate up to 3.4-Gbps per data lane to support Ultra HD (4K × 2K / 30-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP149 device can automatically configure itself as a re-driver at data rates 2-V 0.4 V I0 = 3 mA and VCC < 2-V 0.2 x VCC V VOL SCL/SDA_CTL, SCL/SDA_SRC low-level output voltage fSCL SCL clock frequency fast I2C mode for local I2C control 400 kHz Cbus Total capacitive load for each bus line (DDC and local I2C pins) 400 pF MAX UNIT 7.9 HPD Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VIH High-level input voltage HPD_SNK VIL Low-level input voltage HPD_SNK 0.8 V VOH High-level output voltage IOH = –50 µA; HPD_SRC 2.4 3.6 V VOL Low-level output voltage IOL = 500 µA; HPD_SRC 0 0.1 V ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; HPD_SNK = 5 V 40 μA IH_HPD High-level input current Device powered; VIH = 5 V; IH_HPD includes RpdHPD resistor current 40 μA IL_HPD Low-level input current Device powered; VIL = 0.8 V; IL_HPD includes RpdHPD resistor current 30 RpdHPD HPD input termination to GND VCC = 0 V Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: SN65DP149 SN75DP149 2.1 150 V 190 220 Submit Documentation Feedback kΩ 11 SN65DP149, SN75DP149 SLLSEL2C – SEPTEMBER 2015 – REVISED JULY 2016 www.ti.com 7.10 HDMI and DVI Main Link Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REDRIVER MODE DR Data rate (Automatic Mode) 250 1000 Mbps DR Data rate (full redriver mode) 250 3400 Mbps tPLH Propagation delay time (low to high) 250 600 ps tPHL Propagation delay time (high to low) 250 800 ps tT1 Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. tT2 tT3 SLEW_CTL = H; PRE_SEL = NC; OE = H; DR = 2.97 Gbps 75 SLEW_CTL = L; PRE_SEL = NC; OE = H; DR = 2.97 Gbps 75 SLEW_CTL = NC; PRE_SEL = NC; OE = H; DR = 2.97 Gbps; CLK 297MHz 100 ps tSK1(T) Intra-pair output skew SLEW_CTL = NC; PRE_SEL = NC; OE = H; DR = 2.97 Gbps; 40 tSK2(T) Inter-pair output skew SLEW_CTL = NC; PRE_SEL = NC; OE = H; DR = 2.97 Gbps; 100 tJITD1 Total output data jitter DR = 2.97 Gbps, HDMI_SEL/A1 = NC, EQ_SEL/A0 = NC; PRE_SEL = NC; SLEW_CTL = H OE = H. See Figure 7 at TTP3 0.2 Tbit tJITC1 Total output clock jitter CLK = 297 MHz 0.25 Tbit ps RETIMER MODE dR Data rate (Full retimer mode) 0.25 3.4 Gbps dR Data rate (Automatic mode) 1.0 3.4 Gbps 1.25 Gbps Measured with input signal applied from 0 to 200 mVpp dXVR Automatic redriver to retimer crossover fCROSSOVER Crossover frequency hysteresis PLLBW Data retimer PLL bandwidth tACQ Input clock frequency detection and retimer acquisition time IJT1 Input clock jitter tolerance tT3 tSK_INTRA tJITC1(1.4b) MHz 1 180 75 SLEW_CTL = L; PRE_SEL = NC; OE = H; DR = 3.4 Gbps 75 SLEW_CTL = NC; PRE_SEL = NC; OE = H; DR = 3.4 Gbps; CLK = 297 MHz 100 40% MHz μs 0.3 SLEW_CTL = H; PRE_SEL = NC; OE = H; DR = 3.4 Gbps OUT_CLK ± duty cycle tSK_INTER .4 Tested when data rate > 1.0 Gbps Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. tDCD 1.0 250 Default loop bandwidth setting tT1 tT2 .75 Tbit ps 50% 60% Inter-pair output skew Default setting for internal inter-pair skew adjust, HDMI_SEL/A1 = NC 0.2 Tch 0.15 Tbit Total output clock jitter CLK = 297 MHz 0.25 Tbit TYP MAX UNIT 40 120 ns 7.11 HPD Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN tPD(HPD) Propagation delay from HPD_SNK to HPD_SRC; rising edge and falling edge See Figure 10; not valid during switching time tT(HPD) HPD logical disconnected timeout See Figure 11 12 Submit Documentation Feedback 2 ms Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: SN65DP149 SN75DP149 SN65DP149, SN75DP149 www.ti.com SLLSEL2C – SEPTEMBER 2015 – REVISED JULY 2016 7.12 DDC and I2C Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP UNIT 300 ns 300 ns tr Rise time of both SDA and SCL signals tf Fall time of both SDA and SCL signals tHIGH Pulse duration, SCL high 0.6 μs tLOW Pulse duration, SCL low 1.3 μs tSU1 Setup time, SDA to SCL 100 ns Setup time, SCL to start condition 0.6 μs tHD,STA Hold time, start condition to SCL 0.6 μs tST,STO Setup time, SCL to stop condition 0.6 μs t(BUF) Bus free time between stop and start condition. 1.3 μs tPLH1 Source-to-sink: 100-kbps pattern; Propagation delay time, low-to-high-level output Cb(Sink) = 400-pF (1); See Figure 14 360 ns tPHL1 Propagation delay time, high-to-low-level output 230 ns tPLH2 Sink to Source: 100-kbps pattern; Propagation delay time, low-to-high-level output Cb(Source) = 100-pF (1); See Figure 15 250 ns tPHL2 Propagation delay time, high-to-low-level output 200 ns tST, (1) STA Vcc = 3.3-V MAX Cb = total capacitance of one bus line in pF. Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: SN65DP149 SN75DP149 Submit Documentation Feedback 13 SN65DP149, SN75DP149 SLLSEL2C – SEPTEMBER 2015 – REVISED JULY 2016 www.ti.com 7.13 Parameter Measurement Information VTERM 3.3V 50Q 50Q 75-200nF 50Q 50Q 0.5 pF D+ VD+ VID Y Driver Receiver VY D75-200nF Z VD- VID = VD+ - VD- VOD = VY - VZ VICM = (VD+ + VD-) 2 VOC = (VY + VZ) 2 VZ Figure 1. TMDS Main Link Test Circuit 2.2 V VTERM VID 1.8 V VID+ VID(pp) 0V VID± tPHL tPLH 80% 80% VOD VOD(pp) 0V 20% tf 20% tr Figure 2. Input and Output Timing Measurements tSK1(T) tSK1(T) TMDS_OUTxp 50% TMDS_OUTxn tSK2(T) TMDS_OUTyp TMDS_OUTyn Figure 3. HDMI and DVI Sink TMDS Output Skew Measurements VOC ûVOC(SS) Figure 4. TMDS Main Link Common Mode Measurements 14 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: SN65DP149 SN75DP149 SN65DP149, SN75DP149 www.ti.com SLLSEL2C – SEPTEMBER 2015 – REVISED JULY 2016 Parameter Measurement Information (continued) VOD(PP) PRE_SEL=Z Vsadj = 7.06