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SN65HVD1050
SLLS632C – DECEMBER 2005 – REVISED FEBRUARY 2015
SN65HVD1050 EMC Optimized CAN Bus Transceiver
1 Features
3 Description
•
•
•
•
The SN65HVD1050 meets or exceeds the
specifications of the ISO 11898 standard for use in
applications employing a Controller Area Network
(CAN).
1
•
•
•
Improved Replacement for the TJA1050
High Electromagnetic Immunity (EMI)
Very Low Electromagnetic Emissions (EME)
Meets or Exceeds the Requirements of
ISO 11898-2
CAN Bus-Fault Protection of –27 V to 40 V
Dominant Time-Out Function
Power-Up and Power-Down Glitch-Free CAN Bus
Inputs and Outputs
– High Input Impedance With Low VCC
– Monotonic Outputs During Power Cycling
2 Applications
•
•
•
•
•
Industrial Automation
– DeviceNet™ Data Buses (Vendor ID #806)
SAE J2284 High-Speed CAN Bus for Automotive
Applications
SAE J1939 Standard Data Bus Interface
ISO 11783 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
As a CAN transceiver, this device provides differential
transmit capability to the bus and differential receive
capability to a CAN controller at signaling rates up to
1 megabit per second (Mbps) (1).
The SN65HVD1050 is designed for operation in
especially harsh environments. As a result, the device
features cross-wire, overvoltage and loss of ground
protection from –27 V to 40 V, overtemperature
shutdown, a –12-V to 12-V common-mode range, and
will withstand voltage transients from –200 V to 200 V
according to ISO 7637.
Device Information(1)
PART NUMBER
SN65HVD1050
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(1)
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second)
Functional Block Diagram
Undervoltage
TXD 1
8
Mode Control
Overtemperature
Sensor
30µA
S
VCC (3)
VCC/2
VREF (5)
Vcc (3)
GND 2
30µA
7
CANH
3
6
CANL
RXD 4
5
VREF
VCC
Dominant
Time-Out
Driver
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD1050
SLLS632C – DECEMBER 2005 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
4
4
4
5
5
6
6
6
7
7
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Driver Electrical Characteristics ................................
Receiver Electrical Characteristics ...........................
Device Switching Characteristics..............................
Driver Switching Characteristics ...............................
Receiver Switching Characteristics...........................
Supply Current ........................................................
S-Pin Characteristics...............................................
VREF-Pin Characteristics .......................................
Typical Characteristics ............................................
8
9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 14
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
14
15
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
10.2 Typical Application ................................................ 19
10.3 System Example ................................................... 22
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Example .................................................... 25
13 Device and Documentation Support ................. 26
13.1 Trademarks ........................................................... 26
13.2 Electrostatic Discharge Caution ............................ 26
13.3 Glossary ................................................................ 26
14 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2010) to Revision C
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision A (May 2007) to Revision B
Page
•
Deleted The device is also qualified for use in ISO 11898-2 automotive applications in accordance with AEC-Q100."
and footnote, "The device is available with Q100 qualification as the SN65HVD1050Q."..................................................... 1
•
Changed VCC min/max range from 4.75-5.25V to 4.5-5.5V.................................................................................................... 4
•
Changed VIH max from 5.25V to 5.5V .................................................................................................................................... 4
•
Added rows for various parameters showing parameters with VCC ±5% and ±10% .............................................................. 4
•
Added Signaling Rate spec, min 20kbps................................................................................................................................ 4
•
Changed VIH min from 2 to 2.1V............................................................................................................................................. 4
•
Changed Bus output voltage (Dominant) CANH 4.5V < VCC < 5.5V from 4.75 to 5.2 ........................................................... 5
2
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5 Description (Continued)
Pin 8 provides for two different modes of operation: high-speed or silent mode. The high-speed mode of
operation is selected by connecting S (pin 8) to ground.
If a high logic level is applied to the S pin of the SN65HVD1050, the device enters a listen-only silent mode
during which the driver is switched off while the receiver remains fully functional.
In silent mode, all bus activity is passed by the receiver output to the local protocol controller. When data
transmission is required, the local protocol controller reverses this low-current silent mode by placing a logic-low
on the S pin to resume full operation.
A dominant time-out circuit in the SN65HVD1050 prevents the driver from blocking network communication with
a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge
is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the
next rising edge on TXD.
Vref (pin 5) is available as a VCC/2 voltage reference to stabilize the output common mode voltage point.
The SN65HVD1050 is characterized for operation from –40°C to 125°C.
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
SN65HVD1050
TXD
GND
VCC
RXD
1
8
2
7
3
6
4
5
S
CANH
CANL
Vref
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
TXD
1
I
GND
2
GND
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
VCC
3
Supply
RXD
4
O
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
VREF
5
O
Reference output voltage
CANL
6
I/O
Low level CAN bus line
CANH
7
I/O
High level CAN bus line
S
8
I
Device ground
Transceiver 5-V supply
Mode select pin (Logic LOW places the device in high-speed mode and logic HIGH places
the device in a listen-only silent mode)
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SLLS632C – DECEMBER 2005 – REVISED FEBRUARY 2015
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7 Specifications
7.1 Absolute Maximum Ratings (1)
VCC Supply voltage (2)
Voltage range at any bus terminal (CANH, CANL, Vref)
MIN
MAX
UNIT
–0.3
7
V
–27
40
V
20
mA
V
IO
Receiver output current
VI
Voltage input, transient pulse (3) (CANH, CANL)
–200
200
VI
Voltage input range (TXD, S)
–0.5
6
V
TJ
Junction temperature
–55
170
°C
Tstg Storage temperature
–40
125
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 5, 6, and 7.
7.2 ESD Ratings
VALUE
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
(1)
(2)
Electrostatic discharge
All pins
±8000
Bus pins vs GND
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
Machine Model, ANSI/ESDS5.2-1996
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VI or VIC
Voltage at any bus terminal (separately or common mode)
–12
12
V
VIH
High-level input voltage
2.1
VCC
V
VIL
Low-level input voltage
0
0.8
V
VID
Differential input voltage
–7
7
V
IOH
High-level output current
IOL
Low-level output current
TJ
Junction temperature
TXD, S
Driver
–70
Receiver
Driver
70
Receiver
4
2
See Absolute Maximum Ratings (1), 1-Mbps minimum
signaling rate with RL = 54 Ω
Signaling Rate
(1)
mA
–2
–40
20
150
mA
°C
kbps
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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7.4 Thermal Information
SN65HVD1050
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-air, Low-K thermal resistance (2)
211
Junction-to-air, High-K thermal resistance
131
RθJC(top)
Junction-to-case (top) thermal resistance
79
RθJB
Junction-to-board thermal resistance
53
ψJT
Junction-to-top characterization parameter
10.3
ψJB
Junction-to-board characterization parameter
56.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
112
Average power dissipation, VCC = 5.0V, Tj = 27°C, RL = 60 Ω, S at 0V, Input to TXD a
500 kHz, 50% duty cycle square wave. CL at RXD = 15 pF
170
Average power dissipation, VCC = 5.5V, Tj = 130°C, RL = 45 Ω, S at 0V, Input to TXD a
500 kHz, 50% duty cycle square wave. CL at RXD = 15 pF
170
Junction temperature, thermal shutdown (3)
190
PD
TJ_shutdown
(1)
(2)
(3)
°C/W
mW
°C
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.
Extended operation in thermal shutdown may affect device reliability, see APPLICATIONS INFORMATION.
7.5 Driver Electrical Characteristics
over recommended operating conditiions (unless otherwise noted)
PARAMETER
CANH
VO(D)
Bus output voltage (Dominant)
CANL
VO(R)
VOD(D)
MIN TYP (1)
TEST CONDITIONS
Bus output voltage (Recessive)
Differential output voltage (Dominant)
VOD(R)
Differential output voltage (Recessive)
VOC(ss)
Steady state common-mode output
voltage
3.4
MAX
4.75V < VCC < 5.25V
2.9
VI = 0V, S at 0V, RL = 4.5V < V < 5.5V
CC
60 Ω, See Figure 11
4.75V < VCC < 5.25V
and Figure 12
4.5V < VCC < 5.5V
2.75
5.2
0.8
1.5
VI = 3V, S at 0V, RL = 4.75V < VCC < 5.25V
60 Ω, See Figure 11
4.5V < VCC < 5.5V
and Figure 12
2
3
1.8
3
4.75V < VCC < 5.25V
1.5
3
4.5V < VCC < 5.5V
1.4
3
VI = 0V, RL = 45 Ω, S
at 0V, See Figure 11,
Figure 12, and
Figure 13
4.75V < VCC < 5.25V
1.4
3
4.5V < VCC < 5.5V
1.3
3
–0.012
0.012
–0.5
0.05
VI = 3V, S at 0V, No Load
4.75V < VCC < 5.25V
S at 0V, Figure 18
4.5V < VCC < 5.5V
2
2.3
1.9
3
3
ΔVOC(ss)
Change in steady-state common-mode
output voltage
IIH
High-level input current, TXD input
VI at VCC
–2
2
IIL
Low-level input current, TXD input
VI at 0V
–50
–10
IO(off)
Power-off TXD output current
VCC at 0V, TXD at 5V
30
Short-circuit steady-state output current
CO
Output capacitance
–105
VCANH = 12V, CANL Open, SeeFigure 21
VCANL = -12V, CANH Open, See Figure 21
VCANL = 12V , CANH Open, See Figure 21
(1)
V
V
V
V
mV
μA
1
VCANH = -12V, CANL Open, See Figure 21
IOS(ss)
V
1.6
2.3
VI = 0V, RL = 60 Ω, S
at 0V, See Figure 11,
Figure 12, and
Figure 13
VI = 3V, S at 0V, See Figure 11 and Figure 12
UNIT
4.5
–72
0.36
–1
1
–0.5
71
mA
105
See receiver input capacitance
All typical values are at 25°C with a 5-V supply.
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7.6 Receiver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
800
900
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ – VIT–)
VOH
High-level output voltage
IO = –2 mA, See
Figure 16
VOL
Low-level output voltage
IO = 2 mA, See Figure 16
0.2
0.4
V
II(off)
Power-off bus input current
CANH or CANL = 5V,
Other pin at 0V,
VCC at 0V, TXD at 0V
165
250
μA
IO(off)
Power-off RXD leakage current
VCC at 0V, RXD at 5V
20
μA
CI
Input capacitance to ground, (CANH or
CANL)
TXD at 3V,
VI = 0.4 sin (4E6πt) + 2.5V
CID
Differential input capacitance
TXD at 3V, VI = 0.4 sin (4E6πt)
RID
Differential input resistance
RIN
Input resistance, (CANH or CANL)
RI(m)
Input resistance matching
[1 – (RIN (CANH) / RIN (CANL))] x 100%
(1)
S at 0V, See Table 1
4.75V < VCC < 5.25V
4.5V < VCC < 5.5V
500
650
100
125
4
4.6
mV
V
3.8
13
pF
5
30
TXD at 3V, S at 0V
V(CANH) = V(CANL)
80
15
30
40
–3%
0%
3%
kΩ
All typical values are at 25°C with a 5-V supply.
7.7 Device Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
td(LOOP1)
Total loop delay, driver input to receiver output,
recessive to dominant
td(LOOP2)
Total loop delay, driver input to receiver output,
dominant to recessive
Figure 19, S at
0V
MIN
TYP MAX
4.75V < VCC < 5.25V
90
190
4.5V < VCC < 5.5V
85
195
4.75V < VCC < 5.25V
90
190
4.5V < VCC < 5.5V
85
195
UNIT
ns
7.8 Driver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tr
Differential output signal rise time
tf
Differential output signal fall time
ten
Enable time from silent mode to dominant
t(dom)
6
Dominant time-out
S at 0V, See Figure 14
MIN
TYP
MAX
25
65
120
25
45
90
25
UNIT
ns
50
See Figure 17
↓VI, See
Figure 20
1
4.75V < VCC < 5.25V
300
4.5V < VCC < 5.5V
280
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450
700
700
μs
μs
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7.9 Receiver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
tPHL
TEST CONDITIONS
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
S at 0V or VCC, See
Figure 16
MIN
TYP
MAX
4.75V < VCC < 5.25V
60
100
130
4.5V < VCC < 5.5V
60
4.75V < VCC < 5.25V
45
4.5V < VCC < 5.5V
45
UNIT
135
70
90
95
tr
Output signal rise time
8
tf
Output signal fall time
8
ns
7.10 Supply Current
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
5-V Supply current
TEST CONDITIONS
Silent mode
S at VCC, VI = VCC
Dominant
VI = 0V, 60 Ω Load, S at 0V
Recessive
VI = VCC, No Load, S at 0V
MIN
4.75V < VCC < 5.25V
TYP
MAX
6
10
50
70
4.5V < VCC < 5.5V
75
6
10
MIN
TYP
MAX
20
40
70
5
20
30
UNIT
mA
7.11 S-Pin Characteristics
over recommended operating conditiions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IIH
High level input current
S at 2V
IIL
Low level input current
S at 0.8V
UNIT
μA
7.12 VREF-Pin Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VREF
Reference output voltage
TEST CONDITIONS
–50 μA < IO < 50 μA
MIN
TYP
MAX
0.4VCC
0.5VCC
0.6VCC
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UNIT
V
7
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SLLS632C – DECEMBER 2005 – REVISED FEBRUARY 2015
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150
145
140
S at 0 V,
RL = 60 W,
CL = 100 pF,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz,
50% Duty Cycle Pulse
VCC = 4.75 V
135
130
VCC = 5 V
125
VCC = 5.25 V
120
−40
0
25
70
TA − Free-Air Temperature − °C
170
t LOOP2 − Dominant-to-Recessive Loop Time − ns
t LOOP1− Recessive-to-Dominant Loop Time − ns
7.13 Typical Characteristics
165
160
VCC = 5.25 V
155
145
−40
20
15
10
70
60
50
40
30
20
TA = 25°C,
VCC = 5 V,
S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
10
0
0
200
400
500
600
800
Signaling Rate − kbps
−10
1000
Figure 3. Supply Current (RMS) vs Signaling Rate
0
1
2
3
4
5
VOCANL − Low-Level Output Voltage − V
Figure 4. Driver Low-Level Output Voltage vs Low-Level
Output Current
3
TA = 25 C,
VCC = 5 V,
S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
Dominant Driver Differential Output Voltage − V
I OH − High-Level Output Current − mA
125
80
5
-50
-40
-30
-20
-10
-0
VCC = 5 V
2.5
VCC = 5.25 V
2
VCC = 4.75 V
1.5
1
S at 0 V,
RL = 60 Ω,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
0.5
0
0
1
2
3
4
5
VOCANH − High-Level Output Voltage − V
−40
Figure 5. Driver High-Level Output Voltage vs High-Level
Output Current
8
70
Figure 2. Dominant-to-Recessive Loop Time vs Free-Air
Temperature (Across VCC)
I OL − Low-Level Output Current − mA
I CC − RMS Supply Current − mA
25
-60
25
90
TA = 25°C,
VCC = 5 V,
S at 0 V,
RL = 60 Ω ,
RXD = 15 pF
30
-70
0
TA − Free-Air Temperature − °C
35
-80
VCC = 4.75 V
140
50
40
VCC = 5 V
150
125
Figure 1. Recessive-to-Dominant Loop Time vs Free-Air
Temperature (Across VCC)
45
S at 0 V,
RL = 60 W,
CL = 100 pF,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz,
50% Duty Cycle Pulse
0
25
70
TA − Free-Air Temperature − °C
125
Figure 6. Driver Differential Output Voltage vs Free-Air
Temperature (Across VCC)
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Typical Characteristics (continued)
45
40
35
6
TA = 25°C,
VCC = 5 V,
S at 0 V,
RL = 60 Ω,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
VIT+
VIT−
5
VO − Receiver Output Voltage − V
30
25
20
15
10
VCM = 12 V
4
VCM = 2.5 V
3
VCM = −12 V
2
TA = 25°C,
VCC = 5 V,
S at 0 V,
RXD = 15 pF
1
0
0.65
0.60
0.75
0.70
5.25
0.85
5
0.80
3
3.5
4
4.5
VCC − Supply Voltage − V
0.80
2
0.85
1
1
0.70
0
0.75
−1
0.60
5
0.65
I O − Differential Driver Output Current − mA
50
VID − Differential Input Voltage − V
Figure 7. Driver Output Current vs Supply Voltage
Figure 8. Receiver Output Voltage vs Differential Input
Voltage
80
dBm
DB mV
60
40
20
0
0.1
Figure 9. Frequency Spectrum of Common-Mode
Emissions
1
10
f − Frequency − MHz
100
1000
Figure 10. Direct Power Injection (DPI) Response vs
Frequency
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8 Parameter Measurement Information
Dominant
IO(CANH)
II
3.5 V
VO(CANH)
VO (CANH)
TXD
VOD
RL
VO(CANH) + VO(CANL)
Recessive
2.5 V
2
S
VI
I I(S)
+
VI(S)
_
VOC
I O(CANL)
V O(CANL)
1.5 V
Figure 11. Driver Voltage, Current, and Test
Definition
Figure 12. Bus Logic State Voltage Definitions
330
CANH
0V
TXD
VOD
1%
RL
+
_
S
VO(CANL)
CANL
330
−2 V
VTEST
7V
1%
Figure 13. Driver VOD Test Circuit
CANH
VCC
VI
TXD
RL = 60 W
±1%
VI
(See Note A)
VCC/2
0V
VO
tPLH
CL = 100 pF
(see Note B)
VO
S
VCC/2
tPHL
10%
CANL
VO(D)
90%
0.9 V
tr
tf
0.5 V
VO(R)
Figure 14. Driver Test Circuit and Voltage Waveforms
CANH
RXD
VI (CANH)
V
+ VI (CANL)
VIC = I (CANH)
2
VI (CANL)
IO
VID
CANL
VO
Figure 15. Receiver Voltage and Current Definitions
10
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Parameter Measurement Information (continued)
3.5 V
CANH
VI
V
RXD
1.5 V
tPLH
CANL
1.5 V
2.4 V
IO
I
(See Note A)
2V
S
CL = 15 pF + 20%
(See Note B)
VO
VO
tPHL
90%
0.7 VCC
10%
VOH
0.3 VCC
VOL
tf
tr
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 16. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
|VID|
–11.1V
–12V
900 mV
L
R
12V
11.1V
900 mV
L
–6V
–12V
6V
L
12V
6V
6V
L
–11.5V
–12V
500 mV
H
12V
11.5V
500 mV
H
–12V
–6V
6V
H
6V
12V
6V
H
Open
Open
X
H
VOL
VOH
DUT
CANH
0V
VI
TXD
S
RXD
+
VO
_
CL
VCC
VI
50 %
60 W
+1%
0V
VOH
CANL
NOTE: CL = 100 pF
includes
instrumentation
and fixture capacitance
within ±20%
15 pF +20%
50 %
VO
VOL
ten
NOTE: All VI input pulses are supplied by a generator having the
following characteristics: tr or tf ≤ 6 ns, Pulse Repetition Rate
(PRR) = 25 kHz, 50% duty cycle
Figure 17. TEN Test Circuit and Waveform
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27 W +1%
TXD
VI
DVOC(SS)
CANH
VOC
CANL
S
27 W +1%
47 nF V = VO(CANH) + VO(CANL)
+20% OC
2
NOTE: All VI input pulses are from 0V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 18. Common Mode Output Voltage Test and Waveforms
DUT
VCC
CANH
VI
TXD
60 W
±1%
CL
TXD Input
50%
0V
tloop1
tloop2
VOH
CANL
S
RXD Output
50%
50%
NOTE: CL = 100 pF
includes instrumentation
and fixture capacitance
within±20%
RXD
+
VOL
VO
_
15 pF ±20%
A.
All VI input pulses are from 0V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 19. T(LOOP) Test Circuit and Waveform
VCC
VI
TXD
RL = 60 W
+1%
VI
(See Note A)
S
0V
VOD
CL
(See Note B)
VOD(D)
VOD
900 mV
500 mV
CANH
0V
tdom
A.
All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
B.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
Figure 20. Dominant Time-Out Test Circuit and Waveforms
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| IOS(SS) |
| IOS(P) |
IOS
200 ms
CANH
TXD
0V
0 V or VCC
12 V
S
CANL
VIN
−12 V or 12 V
Vin
0V
or
0V
10 ms
Vin
−12 V
Figure 21. Driver Short-Circuit Current Test and Waveform
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9 Detailed Description
9.1 Overview
The SN65HVD1050 CAN tranceivers is compatible with the ISO1189-2 High Speed CAN (Controller Area
Network) physical layer standard. It is designed to interface between the differential bus lines in controller area
network and the CAN protocol controller at data rates up to 1 Mbps.
9.2 Functional Block Diagram
Undervoltage
Mode Control
Overtemperature
Sensor
30µA
8
S
5
VREF
7
CANH
6
CANL
VCC (3)
VCC/2
Vcc (3)
30µA
TXD
RXD
1
Dominant
Time-Out
Driver
4
9.3 Feature Description
9.3.1 Mode Control
9.3.1.1 Normal Mode
Select the normal mode of the device operation by setting the S pin low. The CAN bus driver and receiver are
fully operational and the CAN communication is bidirectional. The driver is translating a digital input on TXD to a
differential output on CANH and CANL. The receiver is translating the differential signal from CANH and CANL to
a digital output on RXD.
9.3.1.2 Silent Mode
Activate silent mode (receive only) by setting the S pin high. The CAN driver is turned off while the receiver
remains active and RXD outputs the received bus data.
NOTE
Silent mode may be used to implement babling idiot protection, to ensure that the driver
does not disrupt the network during a local fault. Silent mode may also be used in
redundant systems to select or deselect the redundant transceiver (driver) when needed.
9.3.2 TXD Dominant Timeout (DTO)
During normal mode, the mode where the CAN driver is active, the TXD DTO circuit prevents the transceiver
from blocking network communication in the event of a hardware or software failure where TXD is held dominant
longer than the timeout period tTXD_DTO. The DTO circuit is triggered on a falling edge on the driver input, TXD.
The DTO circuit disables the CAN bus driver if no rising edge is seen on TXD before the timeout period expires.
This frees the CAN bus for communication between other nodes on the network. The CAN driver is re-enabled
when a rising edge is seen on the drvier input, TXD, thus clearing the TXD DTO condition. The receiver and
RXD pin still reflect the CAN bus, and the bus pins are biased to recessive level during a TXD DTO.
14
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Feature Description (continued)
NOTE
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate on the device. The CAN protocol allows a maximum of
eleven successive dominant bits (on TXD) for the worst case, where five successive
dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO
minimum, limits the minimum data rate. Calculate the minimum transmitted data rate
using: Minimum Data Rate = 11 / tTXD_DTO
9.3.3 Thermal Shutdown
The SN65HVD1050 has a thermal shutdown feature that turns off the driver outputs when the junction
temperature nears 190°C. This shutdown prevents catastrophic failure from bus shorts, but does not protect the
circuit from possible damage. The user should strive to maintain recommended operating conditions and not
exceed absolute-maximum ratings at all times. If an SN65HVD1050 is subjected to many, or long-duration faults
that can put the device into thermal shutdown, it should be replaced.
9.3.4 VREF
A reference voltage of VCC/2 is available through the VREF output pin. The VREF voltage should be tied to the
common mode point in a split termination network to help stabilize the output common mode voltage. See
Figure 27 for more application specific information on properly terminating the CAN bus.
If the VREF output pin is not used it can be left floating.
9.3.5 Operating Temperature Range
The SN65HVD1050 is characterized for operation from –40°C to 125°C.
9.4 Device Functional Modes
Table 2. Driver
INPUTS
(1)
OUTPUTS
BUS STATE
TXD (1)
S (1)
CANH (1)
CANL (1)
L
L or Open
H
L
DOMINANT
H
X
Z
Z
RECESSIVE
Open
X
Z
Z
RECESSIVE
X
H
Z
Z
RECESSIVE
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
Table 3. Receiver
(1)
DIFFERENTIAL INPUTS
VID = V(CANH) – V(CANL)
OUTPUT RXD (1)
BUS STATE
VID ≥ 0.9V
L
DOMINANT
0.5V < VID < 0.9V
?
?
VID ≤ 0.5V
H
RECESSIVE
Open
H
RECESSIVE
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
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Table 4. Parametric Cross Reference With the TJA1050
TJA1050
(1)
PARAMETER
HVD1050
TRANSMITTER SECTION
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
Driver IIH
IIL
Low-level input current
Driver IIL
ILI
Power-off bus input current
Receiver II(off)
IO(SC)
Short-circuit output current
Driver IOS(SS)
VO(dom)
Dominant output voltage
Driver VO(D)
Vi(dif)(th)
Differential input voltage
Receiver VIT and recommended VID
Vi(dif)(hys)
Diffrential input hysteresis
Receiver Vhys
VO(reces)
Recessive output voltage
Driver VO(R)
VO(dif)(bus)
Differential bus voltage
Driver VOD(D) and VOD(R)
Ri(cm)
CANH, CANL input resistance
Receiver RIN
Ri(dif)
Differential input resistance
Receiver RID
Ri(cm)(m)
Input resistance matching
Receiver RI (m)
Ci
Input capacitance to ground
Receiver CI
Ci(dif)
Differential input capacitance
Receiver CID
BUS SECTION
RECEIVER SECTION
IOH
High-level output current
Recommended IOH
IOL
Low-level output current
Recommended IOL
Vref PIN SECTION
Vref
Reference output voltage
VO
TIMING SECTION
td(TXD-BUSon)
Delay TXD to bus active
Driver tPLH
td(TXD-BUSoff)
Delay TXD to bus inactive
Driver tPHL
td(BUSon-RXD)
Delay bus active to RXD
Receiver tPHL
td(BUSoff-RXD)
Delay bus inactive to RXD
Receiver tPLH
td(TXD-BUSon) + td(BUSon-RXD)
Device tLOOP1
td(TXD-BUSoff) + td(BUSoff-RXD)
Device tLOOP2
Dominant time out
Driver t(dom)
tdom(TXD)
S PIN SECTION
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
IIH
IIL
Low-level input current
IIL
(1)
16
From TJA1050 Product Specification, Philips Semiconductors, 2002 May 16.
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TXD Input
Vcc
RXD Output
Vcc
25 W
4.3 kW
Output
Input
6V
6V
CANL Input
CANH Input
Vcc
Vcc
10 kW
10 kW
20 kW
20 kW
Input
Input
10 kW
40 V
10 kW
40 V
CANH and CANL Outputs
S Input
Vcc
Vcc
CANH
4.3 kW
Input
6V
CANL
40 kW
40 V
40 V
Vref Output
Vcc
2 kW
Output
2 kW
40 V
Figure 22. Equivalent Input and Output Schematic Diagrams
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Typical Bus Voltage (V)
2
3
4
The CAN bus has two states during powered operation of the device; dominant and recessive. A dominant bus
state is when the bus is driven differentially, corresponding to a logic low on the D and R pin. A recessive bus
state is when the bus is biased to VCC/2 via the high-resistance internal resistors RIN and RID of the receiver,
corresponding to a logic high on the D and R pins. See Figure 23 and Figure 24.
CANH
Vdiff(D)
Vdiff(R)
1
CANL
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
Time, t
Figure 23. Bus States
CANH
VCC/2
RXD
CANL
Figure 24. Simplified Recessive Common Mode Bias and Receiver
These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the
link layer portion of the CAN protocol. The different nodes on the network are typically connected through the use
of a 120-Ω characteristic impedance twisted-pair cable with termination on both ends of the bus.
18
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10.2 Typical Application
VIN
VCC
3
VIN
VOUT
S
5-V Voltage
Regulator
(such as TPS76350)
S (8)
CANH (7)
5V MCU
VREF (5)
RXD
TXD
RXD (4)
TXD (1)
CANL (6)
GND (2)
Optional:
Terminating
Node
Figure 25. Typical Application Schematic
10.2.1 Design Requirements
10.2.1.1 Bus Loading, Length, and Number of Nodes
The ISO 11898 Standard specifies up to 1 Mbps data rate, maximum bus length of 40 meters, maximum drop
line (stub) length of 0.3 meters and a maximum of 30 nodes. However, with careful network design, the system
may have longer cables, longer stub lengths, and many more nodes to a bus. Many CAN organizations and
standards have scaled the use of CAN for applications outside the original ISO 11898 standard. They have made
system level trade-offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these
specifications are ARINC825, CANopen, CAN Kingdom, DeviceNet and NMEA200.
Node n
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
SN65HVD251 CAN
Transceiver
SN65HVD1050 CAN
Transceiver
SN65HVD233 CAN
Transceiver
(with termination)
MCU or DSP
CAN
Controller
SN65HVD257 CAN
Transceiver
RTERM
RTERM
Figure 26. Typical CAN Bus
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Typical Application (continued)
A high number of nodes requires a transceiver with high input impedance and wide common mode range such
as the SN65HVD1050 CAN transceiver. ISO 11898-2 specifies the driver differential output with a 60-Ω load (two
120-Ω termination resistors in parallel) and the differential output must be greater than 1.5 V. The SN65HVD1050
device is specified to meet the 1.5-V requirement with a 60-Ω load, and additionally specified with a differential
output voltage minimum of 1.2 V across a common mode range of –2 V to 7 V via a 330-Ω coupling network.
This network represents the bus loading of 90 SN65HVD1050 transceivers based on their minimum differential
input resistance of 30 kΩ. Therefore, the SN65HVD1050 supports up to 90 transceivers on a single bus segment
with margin to the 1.2-V minimum differential input voltage requirement at each node.
For CAN network design, margin must be given for signal loss across the system and cabling, parasitic loadings,
network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes may be
lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 meters by careful system
design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to
1-km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898 CAN standard.
10.2.1.2 CAN Termination
The ISO 11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (ZO ). Resistors equal to the characteristic impedance of the line should be used to
terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes
to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the
cable or in a node, but if nodes may be removed from the bus the termination must be carefully placed so that it
is not removed from the bus.
Termination is typically a 120-Ω resistor at each end of the bus. If filtering and stabilization of the common mode
voltage of the bus is desired, then split termination may be used (see Figure 27). Split termination uses two 60-Ω
resistors with a capacitor in the middle of these resistors to ground. Split termination improves the
electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common mode voltages
at the start and end of message transmissions.
Care should be taken when determining the power ratings of the termination resistors. A typical worst case fault
condition is if the system power supply and ground were shorted across the termination resistance which would
result in much higher current through the termination resistance than the CAN transceiver's current limit.
Standard Termination
Split Termination
CANH
CANH
RTERM/2
CAN
Transceiver
RTERM
CAN
Transceiver
RTERM/2
CANL
CANL
Figure 27. CAN Termination
10.2.1.2.1 Loop Propagation Delay
Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the
driver input (TXD pin) to the differential outputs (CANH and CANL pins), plus the delay from the receiver inputs
(CANH and CANL) to its output (RXD pin). A typical loop delay for the SN65HVD1050 transceiver is displayed in
Figure 29.
20
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Typical Application (continued)
10.2.2 Detailed Design Procedure
10.2.2.1 ESD Protection
A typical application that employees a CAN bus network may require some form of ESD, burst, and surge
protection to shield the CAN transceiver against unwanted transients that can potential damage the transceiver.
To help shield the SN65HVD1050 transceiver against these high energy transients, transient voltage
suppressors can be implemented on the CAN differential bus terminals. These devices will help absorb the
impact of a ESD, burst, and/or surge strike.
10.2.2.2 Transient Voltage Suppresser (TVS) Diodes
Transient voltage suppressors are the preferred protection components for a CAN bus due to their low
capacitance, which allows them to be designed into every node of a multi-node network without requiring a
reduction in data rate. With response times of a few picoseconds and power ratings of up to several kilowatts,
TVS diodes present the most effective protection against ESD, burst, and surge transients.
Transient
Clamp
Voltage
SN65HVD1050
Transient
Current
Figure 28. Effect of Transient Voltage Supressor
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Typical Application (continued)
10.2.3
Application Curve
Figure 29 shows the typical loop delay for the SN65HVD1050.
Figure 29. tLOOP Delay Waveform
10.3 System Example
10.3.1 ISO 11898 Compliance of SN65HVD1050 5-V CAN Transceiver
10.3.1.1 Introduction
The SN65HVD1050 CAN transceiver is a 5-V CAN transceiver that meets or exceeds the specification of the ISO
11898 standard for applications employing a controller area network.
10.3.1.2 Differential Signal
CAN is a differential bus where complementary signals are sent over two wires and the voltage difference
between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage
difference and outputs the bus state with a single ended logic level output signal.
22
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System Example (continued)
Figure 30. Differential Output Waveform
The CAN driver creates the differential voltage between CANH and CANL in the dominant state. The dominant
differential output of the SN65HVD1050 is greater than 1.5 V and less than 3 V across a 60-Ω load as defined by
the ISO 11898 standard. Figure 30 shows CANH, CANL, and the diferential dominanat state level for the
SN65HVD1050.
A CAN receiver is required to output a recessive state when less than 500 mV of differential voltage exists on the
bus, and a dominant state when more than 900 mV of differential voltage exists on the bus. The CAN receiver
must do this with common-mode input voltages from –2 V to 7 V.
10.3.1.3 Common-Mode Signal
A common-mode signal is an average voltage of the two signal wires that the differential receiver rejects. The
common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. Because the bias
voltage of the recessive state of the device is dependent on VCC, any noise present or variation of VCC will have
an effect on this bias voltage seen by the bus. The SN65HVD1050 CAN transceiver has the recessive bias
voltage set to 0.5 × VCC to comply with the ISO 11898-2 CAN standard.
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11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100nF ceramic capacitor located as close as possible to the VCC supply pins as possible. The SN65HVD1050 is a
linear voltage regulator suitable for the 5-V supply rail.
12 Layout
12.1 Layout Guidelines
In order for the PCB design to be successful, start with design of the protection and filtering circuitry. Because
ESD and EFT transients have a wide frequency bandwidth from approximately 3-MHz to 3-GHz, high frequency
layout techniques must be applied during PCB design. On chip IEC ESD protection is good for laboratory and
portable equipment but is usually not sufficient for EFT and surge transients occurring in industrial environments.
Therefore robust and reliable bus node design requires the use of external transient protection devices at the bus
connectors. Placement at the connector also prevents these harsh transient events from propagating further into
the PCB and system.
Use VCC and ground planes to provide low inductance.
NOTE
High frequency current follows the path of least inductance and not the path of least
resistance.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device. An example placement of the Transient Voltage
Suppression (TVS) device indicated as D1 (either bidirectional diode or varistor solution) and bus filter capacitors
C5 and C7 are shown in Figure 25.
The bus transient protection and filtering components should be placed as close to the bus connector, J1, as
possible. This prevents transients, ESD and noise from penetrating onto the board and disturbing other devices.
Bus termination: Figure 27 shows split termination. This is where the termination is split into two resistors, R5
and R6, with the center or split tap of the termination connected to ground via capacitor C6. Split termination
provides common mode filtering for the bus. When termination is placed on the board instead of directly on the
bus, care must be taken to ensure the terminating node is not removed from the bus as this will cause signal
integrity issues of the bus is not properly terminated on both ends.
Bypass and bulk capacitors should be placed as close as possible to the supply pins of transceiver, examples
C2, C3 (VCC).
Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize
trace and via inductance.
To limit current of digital lines, serial resistors may be used. Examples are R1, R2, R3 and R4.
To filter noise on the digital IO lines, a capacitor may be used close to the input side of the IO as shown by C1
and C4.
Because the internal pullup and pulldown biasing of the device is weak for floating pins, an external 1-kΩ to 10kΩ pullup or pulldown resistor should be used to bias the state of the pin more strongly against noise during
transient events.
Pin 1: If an open-drain host processor is used to drive the TXD pin of the device an external pullup resistor
between 1 kΩ and 10 kΩ should be used to drive the recessive input state of the device.
Pin 5: VREF should be connected to the center point of a split temrination scheme to help stabalize the common
mode volatge to VCC/2. If VREF is unused it should be left floating.
Pin 8: Is shown assuming the mode pin, S, will be used. If the device will only be used in normal mode, R3 is not
needed and the pads of C4 could be used for the pulldown resistor to GND.
24
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12.2 Layout Example
TXD
R1
R3
C4
GND
2
7
R5
R2
6
4
5
R6
J1
RXD
3
C7
VCC
C6
VREF
D1
C3
C2
U1
SN65HVD1050
VCC /GND
C5
8
C1
1
R4
Figure 31. Layout Example
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Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVD1050
25
SN65HVD1050
SLLS632C – DECEMBER 2005 – REVISED FEBRUARY 2015
www.ti.com
13 Device and Documentation Support
13.1 Trademarks
DeviceNet is a trademark of Open DeviceNet Vendors Association, Inc.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVD1050
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65HVD1050D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VP1050
SN65HVD1050DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VP1050
SN65HVD1050DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VP1050
SN65HVD1050DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VP1050
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD1050 :
• Automotive: SN65HVD1050-Q1
• Enhanced Product: SN65HVD1050-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Oct-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65HVD1050DR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Oct-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD1050DR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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