SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
ControlNet™ TRANSCEIVER
Check for Samples: SN65HVD61
FEATURES
1
•
•
•
•
•
•
•
2
•
•
•
Compatible With the ControlNet Standard
I/O Operates From 2.5-V to 5-V Supply
Receiver thresholds within –120mV to 120mV
Receiver hysteresis >50mV
Low Power Standby Mode
Thermal Shutdown Protection
Power-Up/Down Glitch-free Bus Inputs and
Outputs
Short-Circuit Protection on Outputs
RoHS Compliant
ControlNet Vendor ID 806
The third signal receiver function (SIG) provides a
scaled analog output which is proportional to the
differential voltage between XF1 and XF3. This output
can be used for diagnostic purposes.
APPLICATIONS
•
•
•
Industrial Networks
Programmable Controllers
Industrial Drives
FUNCTIONAL DIAGRAM
Vcc
14
VDD
3
1
DESCRIPTION
RX
The SN65HVD61 is designed to meet the
requirements for the driver and receiver circuitry of
the ControlNet coaxial-based physical layer.
These devices are single-channel circuits with one
transceiver for single node operation or distributed
stand-alone applications.
-+
2
CD
CHEN
The pull-or-pull transmitter circuit is designed to sink
current from a center-tapped transformer, providing
galvanic isolation from the shared bus.
4
8
SIG
These devices incorporate a differential receiver (RX)
with the 120 mV sensitivity needed by ControlNet
industrial applications.
TX
0.1
- +
5
12
XF1
TSD
TXEN
A secondary receiver (CD) detects the presence of a
valid positive differential signal.
TX
7
6
10
9
DGND
XF3
11, 13
CGND
RX
CD
CHEN
ControlNet
MAC
TXEN
HVD61
ControlNet Bus
TX
TXBAR
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ControlNet is a trademark of ODVA.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2011, Texas Instruments Incorporated
SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE (1)
PART NUMBER
SN65HVD61
(1)
(2)
MARKED AS
D
65HVD61
DR (2)
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
R suffix indicates tape and reel
ABSOLUTE MAXIMUM RATINGS (1)
VCC
Supply voltage (2)
VDD
Supply voltage (4)
(3)
Logic input voltage range (TX, TXBAR , TXEN, CHEN)
VALUE
UNIT
–0.3 to 6
V
–0.3 to 6
V
–0.5 to 6
V
Bus terminal voltage range (XF1, XF3)
–22 to +22
V
Logic input current, (TX, TXBAR , TXEN, CHEN)
–20 to 20
mA
Bus terminal current (XF1, XF3)
Internally limited
Receiver output current (RX, CD)
Bus pins (XF1, XF3)
Human Body Model (4)
Electrostatic discharge
Machine Model
TJ
(1)
(2)
(3)
(4)
(5)
(6)
(7)
All other pins
Charged Device Model
Junction temperature (see
(7)
(5)
All pins
(6)
below regarding thermal shutdown)
±15
mA
16
kV
4
kV
1500
V
200
V
170
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DGND and CGND should be connected to a common ground plane external to the device. All voltage values, except differential I/O bus
voltages, are with respect to the ground plane
VCC and VDD lower limits are DC conditions, see application information regarding start-up transients.
Tested in accordance JEDEC Standard 22, Test Method A114-A.
Tested in accordance JEDEC Standard 22, Test Method C101.
Tested in accordance JEDEC Standard 22, Test Method A115-A.
If the internal junction temperature exceeds 170°C, a thermal shutdown function will disable the transmitter.
DISSIPATION RATINGS
(1)
(2)
2
CIRCUIT BOARD
MODEL (1)
TA ≤ 25°C
DERATING FACTOR (2)
ABOVE TA = 25°C
TA = 65°C
TA = 100°C
Low-K
625 mW
5 mW/°C
425 mW
250 mW
High-K
1180 mW
9.5 mW/°C
800 mW
475 mW
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. For
additional information about JEDEC thermal models, see Texas Instruments Application Note Thermal Characteristics of Logic and
Linear Packages using JEDEC PCB Designs (SZZA017).
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
Copyright © 2007–2011, Texas Instruments Incorporated
SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
VCC
Analog supply voltage (1)
VDD
Input/Output supply voltage (2)
VIH
High-level logic input voltage
VIL
Low-level logic input voltage
Bus pin common-mode voltage
TX, TXBAR, TXEN, CHEN
(VXF1 + VXF3 ) / 2
Voltage at any bus terminal (XF1, XF3)
MIN
NOM
MAX
4.5
5
5.5
V
2.375
5.5
V
0.7×VDD
VDD
0
0.3×VDD
4.5
5.5
V
–10
15
V
150
mA
Transmitter peak output current (XF1, XF3)
IOH
High-level logic output current
IOL
Low-level logic output current
Output current
TA
TJ
Operating free-air temperature
RX, CD
8
–1
1
4.75 V ≤ VCC ≤ 5.25 V
–40
100
4.5 V ≤ VCC ≤ 5.5 V
–30
100
SIG
Junction temperature
Signaling rate
Relative humidity (non-condensing)
(1)
(2)
130
–8
UNIT
V
mA
mA
°C
150
10
Mbps
95%
A power-shutdown feature keeps the device disabled when the voltage at VCC is below 2.1 V.
The I/O ring voltage for this device (VDD) should be the same as the power supply voltage for the controller with which it interfaces. In
the case where the voltages are different, designers must consider the logic threshold compatibility between devices.
Copyright © 2007–2011, Texas Instruments Incorporated
3
SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
0.9
1.2
VCC–0.05
VCC
UNIT
BUS PINS (XF1, XF3)
VOL(TX)
Transmitter output low voltage
VOH(TX)
Transmitter output high voltage
VO(OFF)
Transmitter off noise level,
|XF3-XF1|
RL = 37.5 Ω, 0 to 20 MHz BW, TX and TXBAR
inputs idle, CHEN and TXEN inputs LO
VSW(PP)
Receiver-to-bus reflection, peak-to-peak
R1=R2=50 Ω, C1=C2=15pF, See Figure 3
VTH+
Positive-going differential input threshold
voltage
4.5V < Vcm < 5.5V
VTH-
Negative-going differential input threshold
voltage
4.5V < Vcm < 5.5V
Vhys
Hysteresis voltage (VTH+ – VTH-)
4.5V < Vcm < 5.5V, RX output
50
70
VCD
Carrier detect threshold voltage, (XF3–XF1)
4.5V < Vcm < 5.5V
23
175
II
Bus terminal input leakage current
Connect to VCC through
37.5 Ω, ±1% resistor
35
–120
5
mV
200
mV
120
mV
–35
VI = 10V, TXEN at 0V,
Other input at –10V to 10V
V
mV
mV
255
mV
1.2
mA
VI = –10V, TXEN at 0V
Other input at –10V to 10V
–1.7
II(off)
Bus terminal input leakage current
VCC < 2V, VI = -10V to 10V
Other input at –10 V to 10 V
–1.7
1.2
mA
IOS
Short-circuit output current
0 < VO < VCC
–400
400
mA
RIN
Bus terminal input resistance
VI = –10V to 10V, Other input at CGND, DC
Differential input capacitance (XF1-to-XF3)
10 MHz AC test frequency, 1VPP amplitude using
HP4194A or equivalent impedance analyzer,
VCC = 0V
CIN
12
kΩ
7
11
pF
100
μA
LOGIC INPUTS (TX, TXBAR, TXEN,CHEN)
–100
II
Logic input current
TX, TXBAR, TXEN, CHEN
II(off)
Logic input power-off current
VDD at 0 V, TX,TXBAR, TXEN, CHEN
–100
μA
100
LOGIC OUTPUTS (RX, CD)
CL = 15 pF
VOH
Logic output voltage, high level
VOL
Logic output voltage, low level
IOZ
Logic output high-impedance-state current
RX, CD, 0 < VO < VDD
IO(off)
Logic output power-off current
VDD at 0 V, 0 < VO < 5.5V
0.8×VDD
IO = –4 mA, VDD > 3V
V
2.4
CL = 15 pF
0.2×VDD
IO = 4 mA
0.4
V
–20
20
μA
–1
1
mA
SIGNAL STRENGTH PIN (SIG)
VSIG(0)
SIG output voltage with zero differential
input voltage
RL = 5 kΩ
GAIN
SIG gain ΔVO/ΔVID
VID switching at 10 Mbps,
VO measured with 20 MHz
bandwidth, See Figure 10
1.125
1.25
1.375
4.75V ≤ VCC ≤ 5.25V
120
4.5V ≤ VCC ≤ 5.5V
140
V
mV/V
POWER SUPPLY PINS (VCC, CGND, VDD, DGND)
ICC
IDD
(1)
4
Analog supply current (dynamic)
CHEN and TXEN at logic high, No load
36
65
Analog supply current, chip disabled
CHEN at logic low
1.8
3
Analog supply current,
Lowest power conditions
CHEN at DGND, TX and TXBAR at VDD
0.8
2
I/O supply current, I/O, dynamic
CHEN at logic high, no load
I/O supply current, I/O, chip disabled
CHEN at logic low
mA
5
mA
105
μA
All typical values are at 25°C and with a 5 V supply. For typical values with a 3.3V supply, refer to the TYPICAL CHARACTERISTICS
curves.
Copyright © 2007–2011, Texas Instruments Incorporated
SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
SWITCHING CHARACTERISTICS
over operating recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRANSMITTER
tr
Output rise time (10%-to-90%) differential
20
30
tf
Output fall time (90%-to-10%) differential
20
30
tPLH
Propagation delay time, low-to-high-level differential output
22
50
tPHL
Propagation delay time, high-to-low-level differential output
24
50
tsk(p)
Pulse skew, differential (XF3-XF1)
| tPLH – tPHL|
2
5
tOUT
Output delay skew, tpON – tpOFF, single-ended outputs
0
7
12
0
9
12
SKEW
tON-tOFF Symmetry, turn-on-time-to-turn-off-time, 10%/90%, each
single-ended output
RL = 37.5 Ω, CL = 15 pF, CHEN and
TXEN at logic high, See Figure 1 (1)
RL = 37.5 Ω, CL = 15 pF, CHEN and
TXEN at logic high, See Figure 2
tPZL
Propagation delay time, disabled-to-low-level output
tPLZ
Propagation delay time, low-level-to-disabled-output
tPZL
Propagation delay time, disabled-to-low-level output
tPLZ
Propagation delay time, low-level-to-disabled-output
SR
Output differential slew rate
See Figure 1
Transmit jitter, differential
10 Mbps Manchester-code
RL = 37.5 Ω,
CL = 15 pF, See
Figure 4
TXEN changing,
CHEN at VDD
250
CHEN changing,
TXEN at VDD
400
400
ns
ns
ns
400
0°C < T < 85°C
1
2.5
V/ns
ns
RECEIVERS (RX and CD)
tr
Output rise time (10%-to-90%)
2
20
tf
Output fall time (90%-to-10%)
2
20
tPLH
Propagation delay time, low-to-high-level output
25
40
tPHL
Propagation delay time, high-to-low-level output
25
40
tsk(p)
Pulse skew |tPLH – tPHL|
0.2
4.5
tPZL
Propagation delay time,high-impedance-to-low-level output
tPLZ
Propagation delay time,low-level-to-high-impedance output
tPZH
Propagation delay time, high-impedance-to-high-level output
tPHZ
Propagation delay time, high-level-to-high- impedance output
Receive jitter
(1)
VID = ±2.5V,
RL = 1 kΩ,
CL = 15 pF,
See Figure 5
RX
CD
7
VID = –2.5V, RL = 1kΩ, CL = 15 pF,
See Figure 6
1000
VID = 2.5V, RL = 1kΩ, CL = 15 pF,
See Figure 7
1000
10 Mbps Manchester-code
ns
55
55
ns
ns
0.5
30 ns maximum represents the worst-case allowable rise/fall time when connected to a transformer-coupler network.
Copyright © 2007–2011, Texas Instruments Incorporated
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SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VDD
VCC
VCC
VDD
VDD
Complimentary
Inputs
VXF3
XF3
37.5 W
CHEN
TXEN
VCC
TX
37.5 W
TXBAR
0.5
VDD
TX
15 pF
15 pF
+
VOD
0+/-0.5 ns
VDD
-
0.5
VDD
TXBAR
VXF1
XF1
0V
0+/-0.5 ns
DGND CGND
0V
tpLH
tpHL
VPHY_1
90%
VOD
SR = dVOD/dt
50%
10%
VPHY_0
tr
VOC
tf
VOC(PP)
Figure 1. Transmitter Differential Switching Characteristics
VDD
TX
0+/-0.5 ns
0+/-0.5 ns
0.5 VDD
TXBAR
0V
tpON
tpOFF
tON(XFI)
tOFF(XFI)
XF1
90%
10%
XF3
tOUT SKEW(1)
tOUT SKEW(2)
tOFF(XF3)
tON(XF3)
Figure 2. Transmitter Single-Ended Switching Characteristics
6
Copyright © 2007–2011, Texas Instruments Incorporated
SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VBUS
1:1:1 XFRM
XF3
R1
Signal
Generator
RX
+
V
+
V
VRX
C1
5V
CD
R2
VCD
XF1
5V
CHEN
C2
TXEN
VID
VSW(PP)
Figure 3. Receiver-to-Bus Reflection Measurement
VDD
TXEN
or
CHEN
0.5 VDD
VCC
0V
VCC
VDD
VDD
tpLZ
XF3
37.5 W
CHEN
TXEN
+
15 pF
VCC
VDD
TX
VDD
TXBAR
37.5 W
15 pF
XF1
DGND CGND
tpZL
VCC
VOD
-
VXF1
or
VXF3
50%
10%
VOL(TX)
Figure 4. Transmitter Enable/Disable Test Circuits and Characteristics
Copyright © 2007–2011, Texas Instruments Incorporated
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SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
2.5 V
VID 50%
VDD
-2.5 V
VCC
0V
0V
tpHL
VCC
VDD
Test Input
Signal
CL
CHEN
+
VID
XF3
-
XF1
RL
RL
CL
tpLH
VOH
RX
CD
VRX
or
VCD
DGND CGND
50%
50%
0V
Figure 5. Test Circuit and Signal Waveforms, Receiver and Carrier Detect
VDD
0.5 VDD
CHEN
VDD
VCC
0V
VDD
VDD
tpLZ
VCC
Test Input
Signal
+
VID
-
CHEN
XF3
CL
RL
CL
tpZL
RL
RX
CD
XF1
DGND CGND
VRX
or
VCD
50%
10%
VOL
Figure 6. Test Circuit and Signal Waveforms, Receiver Enable and Disable With Low Bus Input
8
Copyright © 2007–2011, Texas Instruments Incorporated
SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VDD
0.5 VDD
CHEN
VDD
0V
VCC
0V
0V
Test Input
Signal
CHEN
+
XF3
VID
-
XF1
tpZH
tpHZ
VCC
CL
RL
RL
CL
VOH
RX
90%
CD
VRX
or
VCD
DGND CGND
50%
0V
Figure 7. Test Circuit and Signal Waveforms, Receiver Enable and Disable With High Bus Input
Table 1. FUNCTION TABLES
TRANSMITTER
INPUTS
OUTPUTS
CHEN
TXEN
TX
TXBAR
XF1
XF3
L or OPEN
X
X
X
Z
Z
L or OPEN
H
H
X
X
Z
Z
L or OPEN
L or OPEN
Z
Z
L or OPEN
H
Z
L
H
L or OPEN
L
Z
H(1)
H(1)
L(1)
L(1)
H (1)
(1)
This combination is not supported and should be avoided in ControlNet applications
RECEIVER
INPUTS
OUTPUT
CHEN
XF1, XF3
CONDITION
RX
L or OPEN
X
Chip disabled
Z
(VXF3 – VXF1) < VTH–
Negative signal
L
H
VTH– < (VXF3 – VXF1) < VTH+
No signal
?
VTH+ < (VXF3 – VXF1)
Positive signal
H
CARRIER DETECT
INPUTS
OUTPUT
CHEN
XF1, XF3
CONDITION
CD
L or OPEN
X
Chip disabled
Z
(VXF3 – VXF1) < VCD
Carrier not detected
L
VCD < (VXF3 – VXF1)
Carrier detected
H
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SN65HVD61
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www.ti.com
TYPICAL CHARACTERISTICS
CD VOLTAGE
vs
INPUT VOLTAGE
RX VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
5
4.5
VDD = 5 V
4.5
VRX - Receiver Output Voltage - V
VCD - Carrier Detect Output Voltage - V
5
4
3.5
VDD = 3.3 V
3
2.5
2
VDD = 2.5 V
1.5
1
4
3.5
3
VDD = 3.3 V
2.5
VDD = 2.5 V
2
1.5
1
0.5
0.5
0
-400
VDD = 5 V
-200
0
200
VID - Input Differential Voltage - mV
0
-200
400
-150 -100 -50
0
50
100 150 200
VID - Receiver Input Differential Voltage - mV
Figure 8.
Figure 9.
SIG VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
10 Mbps Signaling Rate
VSIG - Output Voltage - V
2
1.5
1
0.5
0
-5
-4
-3
-2
-1
0
1
2
3
4
5
VID - Differential Input Voltage - V
Figure 10.
10
Copyright © 2007–2011, Texas Instruments Incorporated
SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
APPLICATION INFORMATION
THERMAL SHUTDOWN
In most cases, the device’s internal junction temperature will not reach the thermal shutdown temperature if
operated within the recommended operating conditions. However, during fault conditions, such as driver
short-circuit, the junction temperature may reach the thermal shutdown limit. This also depends on the thermal
characteristics of the device mounting, the circuit board, and environmental factors. After the device reaches the
thermal shutdown temperature, the driver outputs will be disabled, and the device will cool down. If the
short-circuit is still present when the drivers are re-enabled, this thermal shutdown cycle will repeat until the
short-circuit fault is removed.
For long-term reliability, the package power dissipation must not exceed the values in the data sheet POWER
DISSIPATION RATINGS for extended periods.
POWER-UP TRANSIENTS
The absolute maximum ratings for Vcc and Vdd specify the limits for these supplies. During initial power-on,
these supply voltages may instantaneously drop below the given lower limit. Designers should consider that
diodes in the circuitry will begin to turn on if the voltage becomes too negative, and that damage may occur if
these diodes dissipate significant power internal to the device. The actual threshold for possible damage is a
function of both undervoltage magnitude and undervoltage transient duration. Further, the allowable undervoltage
transient conditions depend on factors such as device junction temperature and power supply source impedance.
THERMAL CHARACTERISTICS OF IC PACKAGES
Junction-to-Ambient Thermal Resistance (θJA) is defined as the difference in junction temperature to ambient
temperature divided by the operating power. θJA is NOT a constant and is a strong function of
• the PCB design (50% variation)
• altitude (20% variation)
• device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board
gives best case in-use condition and consists of 2 1-oz buried power planes with a single trace layer 25 mm long
with 2-oz thick copper. A 4% to 50% difference in θJA can be measured between these two test cards
Junction-to-case thermal resistance (θJC) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force
heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to
predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a
non-standard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
Junction-to-board thermal resistance (θJB ) is defined to be the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate
structure. θJB is only defined for the high-k test card.
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θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of
package system.
JEDEC High-K Model
JEDEC Low-K Model
105.7°C/W
199.5°C/W
θJA
θJB
52.3
52.3
θJC
56.32°C/W
56.32°C/W
Ambient Node
qCA Calculated
Surface Node
qJC Calculated/Measured
Junction
qJB Calculated/Measured
PC Board
Figure 11. Thermal Resistance
Additional information about thermal metrics for integrated circuits is available in the Texas Instruments
Application Note IC Package Thermal Metrics (SPRA953).
ControlNet APPLICATION
In a typical ControlNet application, several nodes will be connected to a common bus, as shown in Figure 12. At
any time, only one node should actively drive the bus; all active nodes continually receive the bus state. The
node which is actively driving the bus will sink current through either the XF1 or XF3 terminal, causing the
voltage on the bus to be either differential high or differential low.
PASSIVE
TAP
(Impedance
Matching)
HVD61
1:1:1 XFRM
PASSIVE
TAP
(Impedance
Matching)
75 Ohm Coax
HVD61
Vcc
75 Ohm Coax
HVD61
Vcc
75 Ohm
75 Ohm Coax
75 Ohm Coax
75 Ohm Coax
75 Ohm
PASSIVE
TAP
(Impedance
Matching)
Vcc
1:1:1 XFRM
1:1:1 XFRM
Figure 12. Typical ControlNet Application
12
Copyright © 2007–2011, Texas Instruments Incorporated
SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
SYSTEM-LEVEL EMC PROTECTION
The ControlNet network is intended to operate reliably in harsh industrial environments. At a system level, the
network is tested according to several international electromagnetic compatibility (EMC) standards. The
requirements are summarized in the Table 2 and Figure 13.
Table 2. EMC Standard Requirements
EMC STANDARD
DESCRIPTION OF TEST METHOD
LEVEL
IEC 61000-4-2
Electro Static Discharge (ESD) Immunity
6 kV Contact
8 kV Air-Gap
IEC 61000-4-3
Radiated Radio Frequency (RF) Immunity
10V/m at 80 MHz to 2.7GHz
IEC 61000-4-4
Fast Transients / Burst Immunity
1 kV
IEC 61000-4-5
Surge Immunity
1 kV
IEC 61000-4-6
Conducted Radio Frequency (RF) Immunity
10V at 150 kHz to 80 MHz
1kHz AM 80% modulation
Vcc
1:1:1 XFRM
XF1
HVD61
Passive
ImpedanceMatching
Tap
RG-6 Coax
Vcc
XF3
1M
2.2nF
0.01uF
30V
MOV
IEC stimuli applied here
10uF
Figure 13. Simplified Test Set-Up for EMC Standards
DRIVER FUNCTIONS
The ControlNet standard requires the transmitter to generate a signal with nominal amplitude of 8.2Vpp into a
37.5 Ω load. This applies to the double-terminated coax bus as shown in Figure 12. Rise and fall times should
not exceed 30 nsec, and the signal slew rate should not exceed 1 V/nsec. Transmit signal distortion (ringing,
droop, overshoot) should not exceed 10% of the peak-to-peak amplitude.
RECEIVER FUNCTIONS
The function of the primary receiver (RX) and the carrier detect (CD) depends on the signals XF1 and XF3. The
purpose of RX is to indicate the status of the two ControlNet bus lines, based on the signals XF1 and XF3. If the
voltage at XF3 is greater than the voltage at XF1, then the bus state is positive, and RX should output a HIGH
voltage. This corresponds to a Phy_1 symbol. If the voltage at XF3 is less than the voltage at XF1, then the bus
state is negative, and RX should output a LOW voltage. This corresponds to a Phy_0 symbol. See Figure 14.
Note that the allowable variation in VTH–, VTH+, and VCD is specified in the ELECTRICAL CHARACTERISTICS
table.
Copyright © 2007–2011, Texas Instruments Incorporated
13
SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
V TH NEGATIVE
0
NO VALID SIGNAL
V TH+
V CD+
WEAK
POSITIVE
STRONG POSITIVE
RX
CD
VXF3 – VXF1
Figure 14. RX and CD Functions
SIGNAL STRENGTH OUTPUT
Vsig should be sampled at the beginning of a transmission in the preamble portion of the ControlNet Frame. This
portion is the same for all nodes with the exception of the amplitude. Sampling Vsig in the preamble will provide
the most consistent measurement. Further oversampling coupled with multiple frame sampling may provide
further cable diagnostics such as identifying reflections due to cable breaks. By sampling multiple times in the
preamble of a packet the distance to the break or short may be calculated.
14
Copyright © 2007–2011, Texas Instruments Incorporated
SN65HVD61
SLLS770D – JANUARY 2007 – REVISED JUNE 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers of current version may differ from previous versions.
Changes from Revision C (May 2007) to Revision D
Page
•
Changed ControlNet is a trademark of ControlNet International, Ltd to ControlNet is a trademark of ODVA ..................... 1
•
Changed Vcc MIN from "4.75V" to "4.5V" and changed Vcc MAX from "5.25V" to "5.5V" in the ROC table ...................... 3
•
Changed VDD spec. MAX voltage from "5.25V" to "5.5V" in the ROC table ......................................................................... 3
•
Changed Bus pin common-mode voltage MIN spec. from "4.75V to "4.5V" and MAX spec. from "5.25V to "5.5V" in
the ROC table ....................................................................................................................................................................... 3
•
Added second TA spec and condiitions in the ROC table .................................................................................................... 3
•
Changed VTH+ spec. Test Conditions from "4.75V < Vcm < 5.25V" to "4.5V < Vcm < 5.5V" ............................................... 4
•
Changed VTH- spec. Test Conditions from "4.75V < Vcm < 5.25V" to "4.5V < Vcm < 5.5V" ............................................... 4
•
Changed Vhys spec. Test Conditions from "4.75V < Vcm < 5.25V" to "4.5V < Vcm < 5.5V" ................................................ 4
•
Changed VCD spec. Test Conditions from "4.75V < Vcm < 5.25V" to "4.5V < Vcm < 5.5V" ................................................ 4
•
Changed IO(off) spec. Test Conditions maximum voltage from "5.25V" to "5.5V" .................................................................. 4
•
Added second GAIN spec with conditions of 4.5V ≤ VCC ≤ 5.5V in the ELEC CHARA TABLE, and added 140 mV/V
to the MAX column ............................................................................................................................................................... 4
•
Changed IDD (chip disabled) spec MAX from "10" to "105" µA ............................................................................................. 4
•
Added "0°C < T < 85°C" to Test Conditions for SR spec. .................................................................................................... 5
•
Deleted minimum spec value (1 ns) for Receivers (RX and CD) "Output rise time, tr and Output fall time, tf" .................... 5
•
Changed RECEIVERS (RX and CD) tPLH spec and tPHL spec MAX value from "35" tp "40" ns. .......................................... 5
•
Changed tsk(p) spec MAX value from "3.5" to 4.5" for RX test condition ............................................................................... 5
•
Changed RECEIVER tPLZ spec and tPHZ spec MAX value from "40" to "55" ns. .................................................................. 5
Copyright © 2007–2011, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN65HVD61D
NRND
SOIC
D
14
50
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
-40 to 100
65HVD61
SN65HVD61DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 100
65HVD61
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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