SN65HVS882
www.ti.com ........................................................................................................................................................................................................ SLAS601 – MAY 2008
INDUSTRIAL 8-DIGITAL-INPUT SERIALIZER
FEATURES
APPLICATIONS
• Eight Inputs
– High Input Voltage – up to 34 V
– Selectable Debounce Filters – 0 ms to 3 ms
– Flexible Input Current Limit – 0.2 mA to 5.2
mA
– Field Pins Protected to 15-kV HBM ESD
• Output Drivers for External Status LEDs
• Cascadable in Multiples of Eight Inputs
• SPI-Compatible Interface
• Regulated 5-V Output for External Isolator
• Over-Temperature Indicator
•
1
2
•
•
•
Sensor Inputs for Industrial Automation and
Process Control
High Channel Count Digital Input Modules for
PC and PLC Systems
Decentralized I/O Modules
Motion Control Systems
DESCRIPTION
The SN65HVS882 is an eight channel, digital-input serializer for high-channel density digital input modules in
industrial automation. In combination with galvanic isolators the device completes the interface between the high
voltage signals on the field-side and the low-voltage signals on the controller side. Input signals are
current-limited and then validated by internal debounce filters.
With the addition of a few external components, the input switching characteristics can be configured in
accordance with IEC61131-2 for Type 1, 2, and 3 sensor switches.
Upon the application of load and clock signals, input data is latched in parallel into the shift register and
afterwards clocked out serially.
Cascading of multiple devices is possible by connecting the serial output of the leading device with the serial
input of the following device, enabling the design of high-channel count input modules. Multiple devices can be
cascaded through a single serial port, reducing both the isolation channels and controller inputs required.
Input status can be visually indicated via constant current LED outputs. The current limit on the inputs is set by a
single external precision resistor. An integrated voltage regulator provides a 5-V output to supply low-power
isolators. An on-chip temperature sensor provides diagnostic information for graceful shutdown and system
safety.
The SN65HVS882 is available in a 28-pin PWP PowerPAD™ package, allowing for efficient heat dissipation. The
device is characterized for operation at temperatures from -40°C to 125°C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
SN65HVS882
SLAS601 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
Voltage
Regulator
VCC
Debounce Select
DB0:DB1
Serial Input
5V
8
8
8
SERIALIZER
LED Outputs
RE0:RE7
2
Signal
Conditioning
Field Inputs
IP0:IP7
5 V Out
IREF Adj: RLIM
Field Ground
3
Control Inputs
LD, CE, CLK
Serial Output
DB0
DB1
IP0
RE0
IP1
RE1
IP2
RE2
IP3
RE3
IP4
RE4
RLIM
VCC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
SIP
LD
CLK
CE
SOP
IP7
RE7
IP6
RE6
IP5
RE5
TOK
5VOP
FUNCTIONAL BLOCK DIAGRAM
Voltage
Regulator
VCC
5VOP
5V
Temperature
Sensor
TOK
Debounce
Select
DB0
Supply
Monitor
GND
RE0
IP0
Adj. Current
Thresholds
SIP
Current
Sense
&
Voltage
Sense
RE7
IP7
DB1
Debounce
Filter
LD
CE
Channel 0
SERIALZER
RLIM
CLK
Channel 7
SOP
2
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Product Folder Link(s): SN65HVS882
SN65HVS882
www.ti.com ........................................................................................................................................................................................................ SLAS601 – MAY 2008
TERMINAL FUNCTIONS
TERMINAL
PIN NO.
NAME
DESCRIPTION
1, 2
DB0, DB1
3, 5, 7, 9,
11, 18, 20, 22
Debounce select inputs
IPx
Input channel x
4, 6, 8, 10,
12, 17, 19, 21
REx
Return path x (LED drive)
13
RLIM
Current limiting resistor
14
VCC
15
5VOP
Field supply voltage
5-V output to supply low power isolators
16
TOK
Temperature okay
23
SOP
Serial data output
24
CE
Clock enable input
25
CLK
Serial clock input
26
LD
Load pulse input
27
SIP
Serial data input
28
GND
Field ground
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3
SN65HVS882
SLAS601 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
–0.3 to 36
V
IPx
–0.3 to 36
V
Voltage at any logic input
DB0, DB1, CLK, SIP, CE, LD
–0.5 to 6
V
Output current
TOK, SOP
±8
mA
All pins
±4
IPx,VCC
±15
VCC
Field power input
VIPx
Field digital inputs
VID
IO
Human-Body Model (2)
VESD
Electrostatic discharge
PTOT
Continuous total power
dissipation
TJ
Junction temperature
(1)
(2)
(3)
(4)
kV
Charged-Device Model (3)
All pins
±1
kV
Machine Model (4)
All pins
±100
V
170
°C
See Thermal Characteristics
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
JEDEC Standard 22, Method A114-A.
JEDEC Standard 22, Method C101
JEDEC Standard 22, Method A115-A
THERMAL CHARACTERISTICS
PARAMETER
θJA
Junction-to-air thermal resistance
θJB
Junction-to-board thermal
resistance
θJC
Junction-to-case thermal
resistance
PD
Device power dissipation
TEST CONDITIONS
MIN
High-K JEDEC thermal resistance model
IP0-IP7 =
ICC and IIP-LIM = worst case with
IP0-IP7 =
RLIM = 25 kΩ, ILOAD = 50 mA on 5VOP,
IP0-IP7 =
RE0-RE7 = GND, fIP = 100 MHz
IP0-IP7 =
TYP MAX
UNIT
35
°C/W
15
°C/W
4.27
°C/W
VCC = 34 V
VCC = 30 V
2600
VCC = 24 V
mW
VCC = 12 V
RECOMMENDED OPERATING CONDITIONS
MIN
TYP MAX
10
34
V
0
4
V
5.5
34
V
0
0.8
V
VCC
Field supply voltage
VIPL
Field input low-state input voltage
VIPH
Field input high-state input voltage
VIL
Logic low-state input voltage
VIH
Logic high-state input voltage
2.0
RLIM
Current limiter resistor
17
fIP (1)
Input data rate (each field input)
TA
Free-air temperature, see Thermal Characteristics
TJ
(1)
4
0
25
5.5
V
500
kΩ
1
VCC ≤ 34 V
–40
85
VCC ≤ 27 V
–40
105
VCC ≤ 18 V
–40
125
Junction temperature
UNIT
150
Mbps
°C
°C
Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = GND), and RIN = 0 Ω
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SN65HVS882
www.ti.com ........................................................................................................................................................................................................ SLAS601 – MAY 2008
ELECTRICAL CHARACTERISTICS
Over full-range of recommended operating conditions, unless otherwise noted
PARAMETER
TERMINAL
TEST CONDITIONS
MIN
TYP MAX
UNIT
FIELD INPUTS
VTH–(IP)
Low-level input threshold voltage
VTH+(IP)
High-level input threshold voltage
VHYS(IP)
Input hysteresis
VTH–(IN)
Low-level input threshold voltage
VTH+(IN)
High-level input threshold voltage
VHYS(IN)
Input hysteresis
Measured at
field side of
RIN
RIP
Input resistance
IP0–IP7
3 V < VIPx < 6 V, RLIM = 25 kΩ
IIP-LIM
Input current limit
IP0–IP7
RLIM = 25 kΩ
tDB
IRE-on
Debounce times of input channels
RE on-state current
4.0
IP0–IP7
RLIM = 25 kΩ
4.3
5.2
5.5
V
10
V
0.9
IP0–IP7
RE0–RE7
6
18 V < VCC
1 µF
CL
Temperature Sensor
An on-chip temperature sensor monitors the device temperature and signals a fault condition if the internal
temperature reaches 150°C. If the internal temperature exceeds this trip point, the TOK output switches to an
active low state. If the internal temperature continues to rise, passing a second trip point at 170°C, all device
outputs are put in a high-impedance state.
A special condition occurs, however, when the chip temperature exceeds the second temperature trip point due
to an output short. Then the output buffer becomes three-state, thus separating the buffer from the external
circuitry. An internal 100-kΩ pull-down resistor, connecting the TOK pin to ground, is used as a cooling down
resistor, which continues to provide a logic low level to the external circuitry.
12
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SN65HVS882
www.ti.com ........................................................................................................................................................................................................ SLAS601 – MAY 2008
APPLICATION INFORMATION
System-Level EMC
The SN65HVS882 is designed to operate reliably in harsh industrial environments. At a system level, the device
is tested according to several international electromagnetic compatibility (EMC) standards. In addition to the
device internal ESD structures, external protection circuitry, as shown in Figure 15, can be used to absorb as
much energy from burst- and surge-transients as possible.
R1
VSUP = 24 V
R1
56-Ω, 1/3-W MELF resistor
D1
33–36-V fast Zener diode, ZSMB36
C1
10-μF, 60-V ceramic capacitor
RIN
1.2-kΩ, 1/4-W MELF resistor
VCC
CS
C1
D1
DS
SN65HVS882
FE
GND
0V
RIN
IP0–IP7
IPx
CIN
22-nF, 60-V ceramic capacitor
CS
4.7-nF, 2-kV polypropylene capacitor
DS
39-V transient voltage suppressor, SM15T39CA
D2
Super rectifier: BYM10-1000 or
General purpose rectifier: 1N4007
CIN
GND
0V
CS
D2
FE
Figure 15. Typical EMC Protection Circuitry for Supply and Signal Inputs
Input Channel Switching for IEC61131-2 PLC Applications
The input stage of the SN65HVS882 is designed so that with a 24-V supply on VCC and an input resistor RIN =
1.2 kΩ, the trip point for signaling an ON-condition is at 9.4 V at 3.6 mA. This trip point satisfies the switching
requirements of IEC61131-2 type-1 and type-3 switches.
Type 2
Type 3
30
30
30
25
25
25
15
10
5
ON
20
VIN (V)
ON
20
VIN (V)
VIN (V)
Type 1
15
10
5
OFF
0
–30
5
10
IIN (mA)
15
10
5
OFF
0
–3
15
ON
20
0
5
10
15
OFF
0
–3
20
25
IIN (mA)
30
0
5
10
IIN (mA)
15
Figure 16. Switching Characteristics for IEC1131-2 Type 1, 2, and 3 Proximity Switches
For a type-2 switch application two inputs are connected in parallel. The current limiters then add to a total
maximum current of 7.2 mA. While the return-path (RE-pin), of one input might be used to drive an indicator
LED, the RE-pin of the other input channel should be connected to ground (GND).
Paralleling input channels reduces the number of available input channels from an octal Type 1 or Type 3 input
to a quad Type 2 input device. Note, that in this configuration output data of an input channel is represented by
two shift register bits.
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SN65HVS882
SLAS601 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
RIN
RIN
IP0
IP0
CIN
CIN
RE0
RE0
RIN
RIN
IP1
IP1
CIN
CIN
RE1
RE1
Figure 17. Paralleling Two Type 1 or Type 3 Inputs Into One Type 2 Input
Digital Interface Timing
The digital interface of the SN65HVS882 is SPI compatible and interfaces, isolated or non-isolated, to a wide
variety of standard microcontrollers.
SN65HVS882
VCC
5V
VREG
IP0
IP7
SERIALIZER
SIP
HOST
CONTROLLER
ISO7241
LD
OUTA
INA
CE
OUTB
INB
CLK
OUTC
INC
SOP
IND
OUTD
LOAD
STE
SCLK
SOMI
Figure 18. Simple Isolation of the Shift Register Interface
Upon a low-level at the load input, LD, the information of the field inputs, IP0 to IP7 is latched into the shift
register. Taking LD high again blocks the parallel inputs of the shift register from the field inputs. A low-level at
the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial output, SOP. Data
is clocked at the rising edge of CLK. Thus after eight consecutive clock cycles all field input data have been
clocked out of the shift register and the information of the serial input, SIP, appears at the serial output, SOP.
14
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SN65HVS882
www.ti.com ........................................................................................................................................................................................................ SLAS601 – MAY 2008
CLK
CE
high
SIP
LD
PIP0–PIP6
PIP7
SOP don’t care
IP 6
IP7
IP 5
IP4
inhibit
IP3
IP2
IP1
IP 0
SIP
Serial shift
Figure 19. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register
Cascading for High Channel Count Input Modules
Designing high-channel count modules requires cascading multiple SN65HVS882 devices. Simply connect the
serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the
processor interface.
HOST
CONTROLLER
ISO7241
4 X SN65HVS882
OUTA
INA
LOAD
OUTB
INB
STE
OUTC
INC
CLK
SCLK
SOMI
SOP
CE
LD
IP7
SIP
OUTD
SERIALIZER
IP0
IP7
SOP
CE
CLK
LD
SERIALIZER
IP0
IP7
SIP
CLK
SOP
CE
LD
SIP
SERIALIZER
IP0
CLK
IP7
IP0
SERIALIZER
SOP
LD
CE
SIP
IND
Figure 20. Cascading Four SN65HVS882 for a 32-Channel Input Module
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SN65HVS882
SLAS601 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
Typical Digital Input Module Application
SM15T39CA
24V1
(Logic)
24 V
5V
5V-ISO
SM15T39A
(Sensors) 24V2
Isolated
DC/DC
4.7 nF
2 kV
4.7 nF
2 kV
GND2
0V
Power
Supply
4.7 nF
2 kV
GND1
0V-ISO
56 Ω MELF
FE
Srew Terminals
Z2SMB36
10 mF
60 V
1N4007
1 mF
0.1 mF
SN65HVS882
1.2 kΩ
MELF
22 nF
S0
VCC
5VOP
IP0
TOK
RE0
1.2 kΩ
MELF
VCC1
HOST
CONTROLLER
SIP
EN2
EN1
VCC
LD
OUTA
INA
LOAD
CLK
OUTB
INB
SCLK
CE
INC
OUTC
INT
RE7
SOP
IND
OUTD
SOMI
RLIM
DB0
GND2
GND1
DGND
GND
DB1
IP7
22 nF
S7
ISO7242
VCC2
24.9 kΩ
Figure 21. Typical Digital Input Module Application
16
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65HVS882PWP
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVS882
SN65HVS882PWPR
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVS882
SN65HVS882PWPRG4
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVS882
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of