SN65LV1023/SN65LV1224
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SLLS527H – FEBRUARY 2002 – REVISED FEBRUARY 2007
30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
FEATURES
•
•
•
300-Mbps to 660-Mbps Serial LVDS Data
Payload Bandwidth at 30-MHz to 66-MHz
System Clock
Pin-Compatible Superset of NSM
DS92LV1023/DS92LV1224
Chipset (Serializer/Deserializer) Power
Consumption 6 cycles, another 1026 SYNC pattern
transmission initiates.
13
TCLK_R/F
LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a TCLK rising-edge data
strobe.
14
TCLK
LVTTL-level reference clock input. The SN65LV1023 accepts a 30-MHz to 66-MHz clock. TCLK strobes
parallel data into the input latch and provides a reference frequency to the PLL.
15, 16
3-12
DESERIALIZER
1, 12, 13
AGND
Analog circuit ground (PLL and analog circuits)
4, 11
AVCC
Analog circuit power supply (PLL and analog circuits)
14, 20, 22
DGND
Digital circuit ground
21, 23
DVCC
Digital circuit power supply
10
LOCK
LVTTL level output. LOCK goes low when the deserializer PLL locks onto the embedded clock edge.
7
PWRDN
LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a high-impedance state,
putting the device into a low-power mode.
2
RCLK_R/F
LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an RCLK rising-edge data
strobe.
9
RCLK
LVTTL level output recovered clock. Use RCLK to strobe ROUTx.
3
REFCLK
LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL frequency.
8
REN
LVTTL logic input. Low places ROUT0-ROUT9 and RCLK in the high-impedance state.
5
RI+
Serial data input. Noninverting LVDS differential input
6
RI-
Serial data input. Inverting LVDS differential input
15-19, 24-28 ROUT0–ROUT9 Parallel LVTTL data outputs
6
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SLLS527H – FEBRUARY 2002 – REVISED FEBRUARY 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC to GND
–0.3 V to 4 V
LVTTL input voltage
–0.3 V to (VCC + 0.3 V)
LVTTL output voltage
–0.3 V to (VCC + 0.3 V)
LVDS receiver input voltage
–0.3 V to 3.9 V
LVDS driver output voltage
–0.3 V to 3.9 V
LVDS output short circuit duration
Electrostatic discharge
10 ms
HBM
Up to 6 kV
MM
Up to 200 V
Junction temperature
150°C
Storage temperature
–65°C to 150°C
Lead temperature (soldering, 4 seconds)
260°C
Maximum package power dissipation, TA = 25°C
1.27 W
Package derating
(1)
10.3 mW/°C above 25°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
VCC (1)
VCM
MIN
NOM
MAX
Supply voltage
3
3.3
3.6
V
Receiver input voltage range
0
2.4
V
ǒ Ǔ
V
V
V
Receiver input common mode range
ID
2
2.4 –
Supply noise voltage
TA
(1)
Operating free-air temperature
–40
25
ID
2
UNIT
100
mVPP
85
°C
By design, DVCC and AVCC are separated internally and does not matter what the difference is for |DVCC–AVCC|, as long as both are
within 3 V to 3.6 V.
ELECTRICAL CHARACTERISTICS
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (1)
VIH
High-level input voltage
2
VCC
V
VIL
Low-level input voltage
GND
0.8
V
VCL
Input clamp voltage
–0.86
–1.5
V
±100
200
µA
IIN
Input current
(2)
ICL = –18 mA
VIN = 0 V or 3.6 V
–200
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (3)
VIH
High-level input voltage
2
VCC
V
VIL
Low-level input voltage
GND
0.8
V
VCL
Input clamp voltage
ICL = –18 mA
–1.5
V
IIN
Input current (pull-up and pull-down
resistors on inputs)
VIN = 0 V or 3.6 V
200
µA
VOH
High-level output voltage
IOH = –5 mA
VOL
Low-level output voltage
IOL = 5 mA
(1)
(2)
(3)
–0.62
–200
2.2
3
VCC
V
GND
0.25
0.5
V
Apply to DIN0-DIN9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN
High IIN values are due to pull-up and pull-down resistors on the inputs.
Apply to pins PWRDN, RCLK_R/F, REN, REFCLK = inputs; apply to pins ROUTx, RCLK, LOCK = outputs
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IOS
Output short-circuit current
VOUT = 0 V
–15
–47
–85
mA
IOZ
High-impedance output current
PWRDN or REN = 0.8 V, VOUT = 0 V or VCC
–10
±1
10
µA
350
450
SERIALIZER LVDS DC SPECIFICATIONS (Apply to pins DO+ and DO–)
VOD
Output differential voltage (DO+)–(DO–)
RL = 27 Ω, See Figure 2
∆VOD Output differential voltage unbalance
VOS
Offset voltage
1.1
∆VOS Offset voltage unbalance
IOS
Output short circuit current
D0 = 0 V, DINx = high,PWRDN and DEN = 2.4 V
IOZ
High-impedance output current
PWRDN or DEN = 0.8 V, DO = 0 V or VCC
IOX
Power-off output current
VCC = 0 V, DO = 0 V or 3.6 V
CO
Output single-ended capacitance
1.2
mV
35
mV
1.3
V
4.8
35
mV
–10
-90
mA
–10
±1
10
µA
–20
±1
25
µA
1±20%
pF
50
mV
DESERIALIZER LVDS DC SPECIFICATIONS (Apply to pins RI+ and RI–)
VTH
Differential threshold high voltage
VTL
Differential threshold low voltage
IIN
Input current
CI
Input single-ended capacitance
VCM = 1.1 V
–50
mV
VIN = 2.4 V, VCC = 3.6 V or 0 V
–10
±1
15
VIN = 0 V, VCC = 3.6 V or 0 V
–10
±0.05
10
0.5±20%
µA
pF
SERIALIZER SUPPLY CURRENT (Applies to pins DVCC and AVCC)
ICCD
RL = 27 Ω, See Figure 3
Serializer supply current worst case
ICCXD Serializer supply current
f = 30 MHz
30
45
f = 66 MHz
55
70
200
500
f = 30 MHz
40
50
f = 66 MHz
80
95
0.36
1
PWRDN = 0.8 V
mA
µA
DESERIALIZER SUPPLY CURRENT (Applies to pins DVCC and AVCC)
ICCR
Deserializer supply current, worst case
CL = 15 pF, See Figure 4
ICCXR Deserializer supply current, power down
PWRDN = 0.8 V, REN = 0.8 V
1000
900
800
VOD
VOD IN - mV
700
600
500
400
300
200
100
0
0
20
40
60
80
100
Termination (RL) - W
Figure 2. Typical VOD Curve
8
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120
140
mA
mA
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SERIALIZER TIMING REQUIREMENTS
for TCLK over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER
MIN
TYP
MAX
UNIT
15.15
T
33.33
ns
Transmit clock high time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit clock low time
0.4T
0.5T
0.6T
ns
tt(CLK)
TCLK input transition time
3
6
tJIT
TCLK input jitter
tTCP
Transmit clock period
tTCIH
TEST CONDITIONS
See Figure 18
ns
150
ps (RMS)
SERIALIZER SWITCHING CHARACTERISTICS
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
RL = 27 Ω, CL = 10 pF to GND,
See Figure 5
TYP
MAX
0.2
0.4
ns
0.25
0.4
ns
tTLH(L)
LVDS low-to-high transition time
tLTHL(L)
LVDS high-to-low transition time
tsu(DI)
DIN0–DIN9 setup to TCLK
tsu(DI)
DIN0–DIN9 hold from TCLK
td(HZ)
DO± high-to-high-impedance-state delay
2.5
5
td(LZ)
DO± low-to-high-impedance-state delay
2.5
5
td(ZH)
DO±
high-to-high-impedance-state-to-high
delay
5
10
td(ZL)
DO±
high-to-high-impedance-state-to-low
delay
6.5
10
tw(SPW)
SYNC pulse duration
t(PLD)
Serializer PLL lock time
td(S)
Serializer delay
tDJIT
Deterministic
jitter
tRJIT
Random jitter
See Figure 8
0.5
ns
4
ns
RL = 27 Ω, CL = 10 pF to GND,
See Figure 9
See Figure 11
66 MHz
6×tTCP
ns
ns
t
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TCP ) 3.6
2
230
RL = 27 Ω, CL = 10 pF to GND
RL = 27 Ω, CL = 10 pF to GND
ns
1026×tTCP
See Figure 12
30 MHz
UNIT
150
10
ns
ps
19 ps (RMS)
9
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DESERIALIZER TIMING REQUIREMENTS
for REFCLK over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER
tRFCP
REFCLK period
tRFDC
REFCLK duty cycle
tt(RF)
REFCLK transition time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
15.15
T
33.33
ns
30%
50%
70%
3
6
ns
DESERIALIZER SWITCHING CHARACTERISTICS
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER
t(RCP)
Receiver out clockperiod
tTLH(C)
CMOS/TTL low-to-high transition
time
tTHL(C)
CMOS/TTL high-to-low transition
time
td(D)
Deserializer delay,
See Figure 13
t(ROS)
ROUTx data valid before RCLK
TEST CONDITIONS
RCLK
CL = 15 pF,
See Figure 6
ROUT0–ROUT9,
LOCK, RCLK
Room temperature, 3.3 V
See Figure 14
t(ROH)
ROUTx data valid after RCLK
t(RDC)
RCLK duty cycle
td(HZ)
High-to-high-impedance state
delay
td(LZ)
Low-to-high-impedance state
delay
td(HR)
High-impedance state-to-high
delay
td(ZL)
High-impedance-state-to-low
delay
t(DSR1)
Deserializer PLL lock time from
PWRDN(with SYNCPAT)
t(DSR2)
Deserializer PLL lock time from
SYNCPAT
td(ZHLK)
High-impedance-state to-high
delay(power up)
tRNM
Deserializer noise margin
(1)
(2)
10
PIN/FREQ
t(RCP) = t(TCP),
See Figure 12
See Figure 15
MIN
TYP
15.15
UNIT
33.33
ns
1.2
2.5
1.1
2.5
ns
30 MHz
2×tRCP + 7
2.833×tRCP + 11
66 MHz
2×tRCP + 4
2.833×tRCP + 7
ns
RCLK 30 MHz
0.4×tRCP
RCLK 66 MHz
0.4×tRCP
0.5×tRCP
0.5×tRCP
30 MHz
–0.4×tRCP
–0.5×tRCP
66 MHz
–0.4×tRCP
–0.5×tRCP
40%
50%
60%
6.5
8
ns
4.7
8
ns
5.3
8
ns
4.7
8
ns
ns
ROUT0–ROUT9
See Figure 16, Figure 17,
and Note (1)
30 MHz
(1024+26)tRFCP
66 MHz
(1024+26)tRFCP
30 MHz
0.3
66 MHz
0.2
LOCK
See Figure 18 and Note
MAX
(2)
3
30 MHz
1380
66 MHz
540
µs
ns
ps
t(DSR1) represents the time required for the deserializer to register that a lock has occurred upon powerup or when leaving the
powerdown mode. t(DSR2) represents the time required to register that a lock has occurred for the powered up and enabled deserializer
when the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify
deserializer PLL performance tDSR1 and tDSR2 are specified with REFCLK active and stable and specific conditions of SYNCPATs.
tRNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur.
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TIMING DIAGRAMS AND TEST CIRCUITS
TCLK
ODD DIN
EVEN DIN
Figure 3. Worst-Case Serializer ICC Test Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 4. Worst-Case Deserializer ICC Test Pattern
10 pF
tTLH(L)
DO+
tTHL(L)
RL
80%
Vdiff
20%
80%
20%
DO10 pF
Vdiff = (DO+) - (DO-)
Figure 5. Serializer LVDS Output Load and Transition Times
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Deserializer
CMOS/TTL Output
tTHL(C)
tTLH(C)
80%
15 pF
80%
20%
20%
Figure 6. Deserializer CMOS/TTL Output Load and Transition Times
tt(CLK)
tt(CLK)
90%
TCLK
3V
90%
10%
10%
0V
Figure 7. Serializer Input Clock Transition Time
tTCP
1.5 V
TCLK
1.5 V
For TCLK_R/F = Low
1.5 V
th(DI)
tsu(DI)
DIN [9:0]
1.5 V
Setup
Hold
1.5 V
Figure 8. Serializer Setup/Hold Times
Parasitic Package and
Trace Capacitance
3V
DEN
1.5 V
1.5 V
0V
td(HZ)
DO+
VOH
13.5 Ω
50%
1.1 V
DODEN
DO±
td(LZ)
50%
1.1 V
td(ZL)
13.5 Ω
1.1 V
50%
VOL
Figure 9. Serializer High-Impedance-State Test Circuit and Timing
12
td(ZH)
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50%
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2V
PWRDN
0.8 V
1026 Cycles
td(HZ) or td(LZ)
TCLK
td(ZH) or td(ZL)
tPLD
DO±
3-State
Output Active
3-State
Figure 10. Serializer PLL Lock Time and PWRDN High-Impedance-State Delays
REN
PWRDN
TCLK
tw(SP)
SYNC1
or
SYNC2
DO±
DATA
SYNC Pattern
TCLK
SYNC1
or
SYNC2
tw(SP) Min. Timing Met
DO±
SYNC Pattern
DATA
Figure 11. SYNC Timing Delays
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DIN
DIN0 - DIN9 SYMBOL N
DIN0 - DIN9 SYMBOL N+1
td(S)
TCLK
Timing for TCLK_R/F = High
Start
D00 - D09 SYMBOL N-1
Bit
Stop Start
Bit Bit
D00 - D09 SYMBOL N
Stop
Bit
DO
Figure 12. Serializer Delay
Start
Bit
D00 - D09 SYMBOL N
Stop Start
Bit Bit
D00 - D09 SYMBOL N+1
Stop Start
Bit Bit
D00 - D09 SYMBOL N+2
Stop
Bit
RI
1V
tDD
RCLK
Timing for TCLK_R/F = High
ROUT
ROUT0 - ROUT9 SYMBOL N-1
ROUT0 - ROUT9 SYMBOL N+1
ROUT0 - ROUT9 SYMBOL N
Figure 13. Deserializer Delay
tLow
tHigh
RCLK
RCLK_R/F = Low
tHigh
tLow
RCLK
RCLK_R/F = High
tROH
tROS
ROUT [9:0]
1.5 V
Data Valid
Before RCLK
Data Valid
After RCLK
1.5 V
Figure 14. Deserializer Data Valid Out Times
14
1.2 V
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VOH
7 V x (LZ/ZL), Open (HZ/ZH)
REN
500 Ω
450 Ω
1.5 V
1.5 V
VOL
Scope
td(ZL)
td(LZ)
VOL + 0.5 V
50 Ω
VOL + 0.5 V
VOL
ROUT[9:0]
td(ZH)
td(HZ)
VOH
VOH - 0.5 V
VOH - 0.5 V
Figure 15. Deserializer High-Impedance-State Test Circuit and Timing
PWRDN
2V
0.8 V
REFCLK
1.5 V
t(DSR1)
DATA
RI±
Not Important
td(ZHL)
LOCK
SYNC Patterns
3-State
3-State
td(HZ) or td(LZ)
td(ZH) or td(ZL)
ROUT[9:0]
3-State
3-State
SYNC Symbol or DIN[9:0]
RCLK
3-State
3-State
RCLK_R/F = Low
REN
Figure 16. Deserializer PLL Lock Times and PWRDN 3-State Delays
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3.6 V
3V
VCC
0V
PWRDN
0.8 V
REFCLK
t(DSR2)
DATA
1.2 V
RI±
Not Important
1V
SYNC Patterns
LOCK
3-State
td(ZH) or td(ZL)
ROUT[9:0]
td(HZ) or td(LZ)
3-State
3-State
SYNC Symbol or DIN[9:0]
RCLK
3-State
3-State
REN
Figure 17. Deserilaizer PLL Lock Time From SyncPAT
1.2 V
VTH
RI±
VTL
1V
tDJIT
tDJIT
tRNM
tRNM
tSW
Ideal Sampling Position
tSW: Setup and Hold Time (Internal Data Sampling Window)
tDJIT: Serializer Output Bit Position Jitter That Results From Jitter on TCLK
tRNM: Receiver Noise Margin Time
Figure 18. Receiver LVDS Input Skew Margin
16
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DO+
RL
10
DIN
Parallel-to-Serial
DO> TCLK
VOD = (DO+) - (DO-)
Differential Output Signal Is Shown as (DO+) - (DO-)
Figure 19. VOD Diagram
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN65LV1023DB
Package Type Package Pins Package
Drawing
Qty
NRND
SSOP
DB
28
SN65LV1023DBG4
NRND
SSOP
DB
28
SN65LV1224DB
LIFEBUY
SSOP
DB
28
SN65LV1224DBG4
NRND
SSOP
DB
28
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TBD
Call TI
Call TI
-40 to 85
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TBD
Call TI
Call TI
-40 to 85
Device Marking
(4/5)
LV1023
LV1224
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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6-Apr-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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