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SN65LVCP1412RLHT

SN65LVCP1412RLHT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    WQFN-24_5X4MM-EP

  • 描述:

    IC REDRIVER 2CH 14.2GBPS 24WQFN

  • 数据手册
  • 价格&库存
SN65LVCP1412RLHT 数据手册
SN65LVCP1412 www.ti.com SLLSED2 – SEPTEMBER 2012 14.2-GBPS Dual Channel, Dual Mode Linear Equalizer Check for Samples: SN65LVCP1412 FEATURES 1 • • • • • • • • • Dual Channel, Uni-Directional, Multi-Rate, Dual-Mode Linear Equalizer with Operation up to 14.2Gbps Serial Data Rate for Backplane and Cable Interconnects Linear Equalization Increases Link Margin for Systems Implementing Decision Feedback Equalizers (DFE) 18dB Analog Equalization at 7.1GHz with 1dB Step Control for Backplane Mode or Cable Mode Output Linear Dynamic Range: 1200mV Bandwidth: >20GHz – Typical Better than 15dB Return Loss at 7.1GHz Supports Out-of-Band (OOB) Signaling Low Power: Typically 75mW per Channel at 2.5V VCC 24-Terminal QFN (Quad Flatpack, No-Lead) 4mm x 5mm x 0.75mm; 0.5mm Terminal Pitch • • • • • • Excellent Impedance Matching to 100Ω Differential PCB Transmission Lines GPIO or I2C Control 2.5V and 3.3V±5% Single Power Supply 2kV ESD (HBM) Flow-Through Pin-Out Provides Ease of Routing Small Package Size Saves Board Space APPLICATIONS • • High Speed Links in Telecommunication and Data communication Backplane and Cable Interconnects for 10GbE, 16GFC,10G SONET, SAS, SATA, CPRI, OBSAI, Infiniband, 10GBase-KR, and XFI/SFI DESCRIPTION The SN65LVCP1412 is an asynchronous, protocol-agnostic, low latency, two-channel linear equalizer optimized for use up to 14.2Gbps and compensates for losses in backplane or active cable applications. The architecture of SN65LVCP1412 is designed to work with an ASIC or a FPGA with digital equalization employing Decision Feedback Equalizers (DFE). SN65LVCP1412 linear equalizer preserves the shape of the transmitted signal ensuring optimum DFE performance. SN65LVCP1412 provides a low power solution while at the same time extending the effectiveness of DFE. SN65LVCP1412 is configurable via I2C or GPIO interface. Using the I2C interface of the SN65LVCP1412 enables the user to control independently the Equalization, Path Gain, and Output Dynamic Range for each individual channel. In GPIO mode, Equalization, Path Gain, and Output Dynamic Range can be set for all channels using the GPIO Input pins. SN65LVCP1412 outputs can be disabled independently via I2C. The SN65LVCP1412 operates from a single 2.5V or 3.3V power supply. The package for the SN65LVCP1412 is a 24 pin 4mm x 5mm x 0.75mm QFN (Quad Flatpack, No-lead) lead-free package with 0.5mm pitch, and characterized for operation from –40°C to 85°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated SN65LVCP1412 SLLSED2 – SEPTEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Backplane Application TX ASP Serdes ASIC RX LVCP1412 RX ASP Serdes TX ASIC LVCP1412 Figure 1. Typical Backplane Application – Trace Mode Cable Application Active Cable SN65LVCP1412 TX RX SN65LVCP1412 ASP Serdes ASIC RX TX ASP Serdes ASIC Figure 2. Typical Cable Application – Cable Mode 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 SN65LVCP1412 www.ti.com SLLSED2 – SEPTEMBER 2012 BLOCK DIAGRAM (GPIO or I2C Mode) A simplified block diagram of the SN65LVCP1412 is shown in Figure 3 for GPIO or I2C input control mode. This compact, low power, 14.2Gbps dual-channel dual-mode linear analog equalizer consists of two high-speed data paths and an input GPIO pin logic-control block and a two-wire interface with a control-logic block. VCC GND VBB 50 VCC 50 Input Buffer with Selectable Equalizer Output Driver 50 50 IN[1:0]_P OUT[1:0]_P IN[1:0]_N OUT[1:0]_N Power-On Reset Band-Gap Voltage Reference and Bias Current Generation REXT 1.2 k VCC 200 k 200 k DRV_PK#/SCL DRV_PK#/SCL SDA SDA PWD# VOD/CS 6 Bit Register General Setting 3 Bit Register EQ Control 4 Bit Register Channel Enable 1 Bit Register VOD Swing 1 Bit Register DC Gain 2 Bit Register AC Gain PWD# EQ0/ADD0 EQ0/ADD0 VOD/CS EQ1/ADD1 EQ1/ADD1 2-Wire Interface & Control Logic 200 k EQ_MODE/ADD2 EQ_MODE/ADD2 GAIN GAIN I2C_EN I2C_EN 200 k 200 k Figure 3. Simplified Block Diagram of the SN65LVCP1412 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 3 SN65LVCP1412 SLLSED2 – SEPTEMBER 2012 www.ti.com PACKAGE VCC 1 IN0_P 2 IN0_N 3 VCC 4 IN1_P PWD# GAIN EQ_MODE/ADD2 EQ1/ADD1 EQ0/ADD0 24 23 22 21 20 The package pin locations and assignments are shown in Figure 4. The SN65LVCP1412 is packaged in a 4mm x 5mm x 0.75mm, 24 pin, 0.5mm pitch lead-free QFN. 19 VCC 18 OUT0_P 17 OUT0_N 16 VCC 5 15 OUT1_P IN1_N 6 14 OUT1_N VCC 7 13 VCC SN65LVCP1412 Pinout 24 pin QFN (RLH) Package 4mm x 5mm with 0.5mm pitch REXT 12 VOD/CS 11 I2C_EN 10 9 DRV_PK#/SCL SDA 8 It is required for thermal pad to be soldered to ground Figure 4. Package Drawing (Top View) PIN DESCRIPTIONS PINS NAME NO. DIRECTION TYPE SUPPLY DESCRIPTION DIFFERENTIAL HIGH-SPEED I/O IN0_P IN0_N 2 3 Input, (with 50 Ω termination to input common mode) Differential input, lane 0 IN1_P IN1_N 5 6 Input, (with 50 Ω termination to input common mode) Differential input, lane 1 OUT0_P OUT0_N 18 17 Output Differential output, lane 0 OUT1_P OUT1_N 15 14 Output Differential output, lane 1 CONTROL SIGNALS SDA 8 Input Output, Open drain GPIO mode No action needed I2C mode I2C data. Connect a 10kΩ pull-up resistor externally DRV_PK#/SCL 9 Input. (with 200kΩ pull-up) GPIO mode HIGH: disable Driver peaking LOW: enables Driver 6dB AC peaking I2C mode I2C clock. Connect a 10kΩ pull-up resistor externally I2C_EN 10 Input, (wtih 200kΩ pull-down) 2.5V/3.3V CMOS Configures the device operation for I2C or GPIO mode: HIGH: enables I2C mode LOW: enables GPIO mode 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 SN65LVCP1412 www.ti.com SLLSED2 – SEPTEMBER 2012 PIN DESCRIPTIONS (continued) PINS NAME NO. DIRECTION TYPE SUPPLY DESCRIPTION I2C mode HIGH: acts as Chip Select LOW: disables I2C interface VOD/CS 11 Input, (with 200kΩ pull-down) 2.5V/3.3V CMOS GPIO mode HIGH: set high VOD range LOW: set low VOD range REXT 12 Input, Analog External Bias Resistor: 1,200 Ω to GND EQ0/ADD0 20 Input, 2.5V/3.3V CMOS - 3-state GPIO mode Working with EQ1 to determine input EQ gain. I2C mode ADD0 along with pins ADD1 and ADD2 comprise the three bits of I2C slave address. ADD2:ADD1:ADD0:XXX EQ1/ADD1 21 Input, 2.5V/3.3V CMOS - 3-state GPIO mode Working with EQ0 to determine input EQ gain steps of approximately 2dB I2C mode ADD1 along with pins ADD0 and ADD2 comprise the three bits of I2C slave address ADD2:ADD1:ADD0:XXX EQ1 EQ0 EQ GAIN GND GND 000 GND HiZ 000 GND VCC 001 HiZ GND 010 HiZ HiZ 011 HiZ VCC 100 VCC GND 101 VCC HiZ 110 VCC VCC 111 EQ1 and EQ0 work with AC_GAIN and DC_GAIN to determine final EQ gain as this: EQ1/ EQ0 GAIN DC GAIN (dB) EQ GAIN (dB) 000 ~ 111 LOW -6 1~9 000 ~ 111 HiZ -6 7 ~ 17 000 ~ 111 HIGH 0 1~9 EQ_MODE/ ADD2 22 Input, (with 200kΩ pull-down), 2.5V/3.3V CMOS GPIO mode HIGH: Trace mode LOW: Cable mode I2C mode ADD2 along with pins ADD1 and ADD0 comprise the three bits of I2C slave address. ADD2:ADD1:ADD0:XXX GAIN 23 Input, 2.5V/3.3V CMOS - 3-state GPIO mode Work with EQ1/EQ0 to set total EQ Gain. See table above. I2C mode No action needed PWD# 24 Input, (with 200kΩ pull-up), 2.5V/3.3V CMOS HIGH: Normal Operation LOW: Powers down the device, inputs off and outputs disabled, resets I2C Power Power supply 2.5V±5%, 3.3V±5% Ground The ground center pad is the metal contact at the bottom of the package. This pad must be connected to the GND plane. At least 9 PCB vias are recommended to minimize inductance and provide a solid ground. Refer to the package drawing (RLH-package) for the via placement. POWER SUPPLY VCC GND Center Pad 1, 4, 7, 13, 16, 19 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 5 SN65LVCP1412 SLLSED2 – SEPTEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUES UNIT –0.3 to 4 V ±2.5 V VCC Supply voltage range VIN,DIFF Differential Voltage between INx_P and INx_N VIN+, IN– Voltage at Inx_P and fINx_N –0.5 V to VCC+0.5 V VIO Voltage on Control IO pins –0.5 V to VCC+0.5 V IIN+ IIN– Continuous Current at high speed differential data inputs (differential) –25 to 25 mA IOUT+ IOUT– Continuous Current at high speed differential data outputs –25 to 25 mA 2.0 kV 500 V ESD Human Body Model (3) (All Pins) Charged-Device Model (4) (All Pins) Moisture Sensitivity level 2 24 Months at 12” (9dB loss at 5GHz) See Figure 10 DJ3 Residual Deterministic Jitter at 14.2 Gbps Transmit Side Application Tx launch Amplitude = 0.6Vpp, EQ=0, ACGain and DCgain = Low and VOD = High, Trace Mode Test Channel -> 0”. See Figure 11 DJ4 Residual Deterministic Jitter at 14.2 Gbps Receive Side Application Tx launch Amplitude = 0.6Vpp, EQ=7, ACGain and VOD = High and DCGain = High, Trace Mode Test Channel -> 8” (9dB loss at 7GHz) See Figure 10 (2) (3) (4) (5) 8 15 0.016 UIp-p 0.11 UIp-p 0.041 UIp-p 0.13 UIp-p Rise and Fall measurements include board and channel effects of the test environment, refer to Figure 10 and Figure 11 tSK(O) is the magnitude of the time difference between the channels. tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. All noise sources added. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 SN65LVCP1412 www.ti.com SLLSED2 – SEPTEMBER 2012 PARAMETER MEASUREMENT INFORMATION OUT+ OUT- 49.9 . W VOCM 49.9 W 1 pF Figure 5. Common Mode Output Voltage Test Circuit VID = 0 V IN tPLH tPHL VOD = 0 V OUT Figure 6. Propagation Delay Input to Output Figure 7. Output Rise and Fall Time OUTx tSK(0) OUTy Figure 8. Output Inter-Pair Skew Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 9 SN65LVCP1412 SLLSED2 – SEPTEMBER 2012 www.ti.com V1 V3 V2 0V V5 Not drawn to scale V6 V4 Figure 9. Vpre and Vpost (The test pattern is 1111111100000000 (8-1s, 8-0s)) TEST CHANNEL CHARACTERIZATION BOARD SN65LVCP1412 PATTERN GENERATOR L = 2" RX + EQ OUT L = 2" OSCILLOSCOPE Figure 10. Receive Side Performance Test Circuit TEST CHANNEL CHARACTERIZATION BOARD SN65LVCP1412 PATTERN GENERATOR L = 2" RX + EQ OUT OSCILLOSCOPE L = 2" Figure 11. Transmit Side Performance Test Circuit 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 SN65LVCP1412 www.ti.com SLLSED2 – SEPTEMBER 2012 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC IN+ RT(SE) = 50 W Gain Stage +EQ VCC RBBDC RT(SE) = 50 W INLineEndTermination VBB ESD Self-Biasing Network Figure 12. Equivalent Input Circuit Design VCC VCC 200 kΩ ESD IN ESD 200 kΩ Figure 13. 3-Level Input Biasing Network Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 11 SN65LVCP1412 SLLSED2 – SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS Typical operating condition is at VCC = 2.5V and TA = 25°C, no interconnect line at the output, and with default device settings (unless otherwise noted). Amplitude (dB) 24 22 20 18 16 14 12 10 8 6 4 2 0 −2 −4 −6 −8 0.1 EQ=0, ACGAIN=HIGH, DCGAIN=LOW, VOD=HIGH EQ=7, ACGAIN=HIGH, DCGAIN=LOW, VOD=HIGH EQ=0, ACGAIN=HIGH, DCGAIN=LOW, VOD=LOW EQ=0, ACGAIN=LOW, DCGAIN=LOW, VOD=LOW EQ=3, ACGAIN=HIGH, DCGAIN=LOW, VOD=LOW EQ=3, ACGAIN=LOW, DCGAIN=LOW, VOD=LOW EQ=7, ACGAIN=HIGH, DCGAIN=LOW, VOD=LOW EQ=7, ACGAIN=LOW, DCGAIN=LOW, VOD=LOW 1 10 100 Frequency (GHz) G001 Figure 14. Typical EQ Gain Profile Curve 0 0 −5 −5 −10 −10 Amplitude (dB) Amplitude (dB) −15 −15 −20 −20 −25 −30 −25 −35 −30 −35 −40 0 2 4 6 8 Frequency (GHz) 10 12 14 −45 0 G002 Figure 15. Differential Input Return Loss 12 2 4 6 8 Frequency (GHz) 10 12 14 G003 Figure 16. Differential to Common Mode Conversion Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 SN65LVCP1412 www.ti.com SLLSED2 – SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 2.5V and TA = 25°C, no interconnect line at the output, and with default device settings (unless otherwise noted). 0 0 −5 −5 −10 −10 −15 SCC22 (dB) Amplitude (dB) −15 −20 −25 −20 −25 −30 −30 −35 −35 −40 −45 0 2 4 6 8 Frequency (GHz) 10 12 −40 14 0 2 4 6 8 Frequency (GHz) 10 12 14 G004 G005 Figure 17. Differential Output Return Loss Figure 18. Common Mode Output Return Loss 0 0.25 3 meter 6 meter 6 meter (See Note A) 3 meter 6 meter 6 meter (See Note A) −5 0.2 −10 Magnitude (dB) Amplitude (mV) −15 0.15 0.1 −20 −25 −30 −35 0.05 −40 0 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k Time (ps) 2k −45 0 2 4 6 Frequency (GHz) 8 G006 A. With SN65LVCP1412 -> EQ = 4, VOD = High, ACGain = HiZ, DCGain = Low Figure 19. Cable Mode – Symbol Response 10 G007 A. With SN65LVCP1412 -> EQ = 4, VOD = High, ACGain = HiZ, DCGain = Low Figure 20. Cable Mode – Frequency Domain Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 13 SN65LVCP1412 SLLSED2 – SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 2.5V and TA = 25°C, no interconnect line at the output, and with default device settings (unless otherwise noted). 0.35 0 3 meter 6 meter 6 meter (See Note A) 0.3 3 meter 6 meter 6 meter (See Note A) −5 −10 −15 Magnitude (dB) Amplitude (mV) 0.25 0.2 0.15 −20 −25 −30 −35 0.1 −40 0.05 −45 0 0 200 400 600 800 1k 1k Time (ps) 1k 2k 2k −50 2k 0 2 4 6 Frequency (GHz) 8 10 G008 G009 A. With SN65LVCP1412 -> EQ = 7, VOD = High, ACGain = High, DCGain = Low Figure 21. Trace Mode – Symbol Response A. With SN65LVCP1412 -> EQ = 7, VOD = High, ACGain = High, DCGain = Low Figure 22. Trace Mode - Frequency Domain Table 1. Control Settings Descriptions MODE DCGAIN ACGAIN EQ DC GAIN (dB) EQ GAIN (dB) 0 0 00 000 to 111 –6 1 to 9 Short Input Trace; Large Input Swing 0 0 11 000 to 111 –6 7 to 17 Long Input Trace; Large Input Swing 0 1 01 000 to 111 0 1 to 9 Short Input Trace; Small Input Swing 0 1 11 000 to 111 0 2 to 10 Short Input Trace; Small Input Swing 1 0 00 000 to 111 –6 1 to 9 Short Input Cable; Large Input Swing 1 0 11 000 to 111 –6 7 to 17 Long Input Cable; Large Input Swing 1 1 01 000 to 111 0 1 to 9 Short Input Cable; Small Input Swing 1 1 11 000 to 111 0 2 to 10 Short Input Cable; Small Input Swing APPLICATION Table 2. Control Settings Descriptions 14 GAIN DC GAIN ACGAIN Low 0 00 HighZ 0 11 High 1 01 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 SN65LVCP1412 www.ti.com SLLSED2 – SEPTEMBER 2012 TWO-WIRE SERIAL INTERFACE AND CONTROL LOGIC The SN65LVCP1412 uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCL, are driven, respectively, by the serial data and serial clock from a microcontroller, for example. The SDA and SCK pins require external 10kΩ pull-ups to VCC. The 2-wire interface allows write access to the internal memory map to modify control registers and read access to read out control and status signals. The SN65LVCP1412 is a slave device only which means that it cannot initiate a transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The master device provides the clock signal as well as the START and STOP commands. The protocol for a data transmission is as follows: 1. START command 2. 7 bit slave address (0000ADD[2:0]) followed by an eighth bit which is the data direction bit (R/W). A zero indicates a WRITE and a 1 indicates a READ. The ADD[2:0] address bits change with the status of the ADD2, ADD1, and ADD0 device pins, respectively. If the pins are left floating or pulled down, the 7 bit slave address is 0000000. 3. 8 bit register address 4. 8 bit register data word 5. STOP command Regarding timing, the SN65LVCP1412 is I2C compatible. The typical timing is shown in Figure 9 and a complete data transfer is shown in Figure 10. Parameters for Figure 9 are defined in Table 3. Bus Idle: Both SDA and SCL lines remain HIGH Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition (S). Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate on the bus, it can generate a repeated START condition and address another slave without first generating a STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver doesn’t acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition. Figure 23. Two-wire Serial Interface Timing Diagram Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 15 SN65LVCP1412 SLLSED2 – SEPTEMBER 2012 www.ti.com Table 3. Two-Wire Serial Interface Timing Diagram Definitions SYMBOL PARAMETER MIN MAX UNIT 400 kHz fSCL SCL clock frequency tBUF Bus free time between START and STOP conditions 1.3 μs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.6 μs tLOW Low period of the SCL clock 1.3 μs tHIGH High period of the SCL clock 0.6 μs tSUSTA Setup time for a repeated START condition 0.6 μs tHDDAT Data HOLD time 0 μs tSUDAT Data setup time 100 ns tR Rise time of both SDA and SCL signals 300 tF Fall time of both SDA and SCL signals 300 tSUSTO Setup time for STOP condition 0.6 ns ns μs Figure 24. Two-wire Serial Interface Data Transfer 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 SN65LVCP1412 www.ti.com SLLSED2 – SEPTEMBER 2012 REGISTER MAPPING The register mapping for read/write register addresses 0 (0x00) through 22 (0x18) are shown in Table 4. Table 5 describes the circuit functionality based on the register settings. Table 4. SN65LVCP1412 Register Mapping Information Register 0x00 (General Device Settings) R/W bit 7 bit 6 bit 5 RSVD PWRDOWN SYNC_01 bit 4 RSVD bit 3 SYNC_ALL bit 2 EQ_MODE bit 1 bit 0 RSVD bit 4 bit 3 bit 2 LN_EN_CH1 bit 1 LN_EN_CH0 bit 0 Register 0x05 (Channel 0 Control Settings) R/W bit 7 bit 6 bit 5 RSVD EQ2 EQ1 bit 4 EQ0 bit 3 VOD_CTRL bit 2 DC_GAIN bit 1 AC_GAIN1 bit 0 AC_GAIN0 Register 0x06 (Channel 0 Enable Settings) R/W bit 7 bit 6 bit 5 bit 4 bit 3 Register 0x01 (Channel Enable) R/W bit 7 bit 6 bit 5 bit 2 bit 1 bit 0 DRV_PEAK EQ_EN DRV_EN Register 0x08 (Channel 1 Control Settings) R/W bit 7 bit 6 bit 5 RSVD EQ2 EQ1 bit 4 EQ0 bit 3 VOD_CTRL bit 2 DC_GAIN bit 1 AC_GAIN1 bit 0 AC_GAIN0 Register 0x09 (Channel 1 Enable Settings) R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 DRV_PEAK bit 1 EQ_EN bit 0 DRV_EN bit 5 RSVD bit 4 RSVD bit 3 RSVD bit 2 RSVD bit 1 RSVD bit 0 RSVD bit 6 RSVD bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Register 0x0F Read Only bit 7 bit 6 RSVD RSVD Register 0x11 R/W bit 7 Register 0x12 R/W bit 7 RSVD Table 5. SN65LVCP1412 Register Description REGISTER BIT SYMBOL FUNCTION DEFAULT 7 RSVD Fot TI use only 6 PWRDOWN Power down the device: 0 = Normal operation 1 = Powerdown 5 SYNC_01 All settings from channel 1 will be used for channel 0 and 1: 0 = channel 0 tracking channel 1 settings 1 = no tracking tracking 4 RSVD For TI use only 3 SYNC_ALL All settings from channel 1 will be used on all channels: 0 = all channels tracking channel 1 1 = no channel tracking Overwrites SYNC_01 2 EQ_MD Set EQ Mode: 0 = Cable Mode 1 = Trace Mode RSVD For TI use only 0x00 00000000 1 0 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 17 SN65LVCP1412 SLLSED2 – SEPTEMBER 2012 www.ti.com Table 5. SN65LVCP1412 Register Description (continued) REGISTER BIT SYMBOL FUNCTION DEFAULT 7 6 5 4 3 2 LN_EN_CH1 Channel 1 Enable: 0 = Enable 1 = Disable 1 LN_EN_CH0 Channel 0 Enable: 0 = Enable 1 = Disable 0x01 00000000 0 7 RSVD 6 EQ2 5 EQ1 4 EQ0 3 VOD_CTRL Channel [x] VOD control: 0 = low VOD range 1 = high VOD range 2 DC_GAIN_CTRL Channel [x] EQ DC Gain: 0 = set EQ DC Gain to 0.5x 1 = set EQ DC Gain to 1x 1 AC_GAIN_CTRL1 0 AC_GAIN_CTRL0 0x05 0x08 Equalizer Adjustment Setting 000 = Minimum equalization setting 111 = Maximum equalization setting 00000000 AC Gain Control: 00 = Low 01 = HiZ 11 = High 7 6 5 4 3 0x06 0x09 0x0F 18 2 DRV_PEAK Channel [x] Driver Peaking: 0 = disables driver Peaking 1 = enables driver 6db AC Peaking 1 EQ_EN Channel [x] EQ stage enable: 0 = Enable 1 = Disable 0 DRV_EN Channel [x] Driver stage enable: 0 = Enable 1 = Disable 7 RSVD For TI use only 6 RSVD For TI use only 5 RSVD For TI use only 4 RSVD For TI use only 3 RSVD For TI use only 2 RSVD For TI use only 1 RSVD For TI use only 0 RSVD For TI use only Submit Documentation Feedback 00000000 00110000 Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 SN65LVCP1412 www.ti.com SLLSED2 – SEPTEMBER 2012 Table 5. SN65LVCP1412 Register Description (continued) REGISTER BIT SYMBOL FUNCTION DEFAULT 7 6 RSVD For TI use only 5 0x11 4 00000000 3 2 1 0 7 RSVD For TI use only 6 5 0x12 4 00000000 3 2 1 0 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :SN65LVCP1412 19 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVCP1412RLHR ACTIVE WQFN RLH 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVCP 1412 SN65LVCP1412RLHT ACTIVE WQFN RLH 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVCP 1412 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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