SN65LVCP404
www.ti.com ................................................................................................................................................... SLLS700B – MARCH 2007 – REVISED JANUARY 2009
Gigabit 4x4 CROSSPOINT SWITCH
P22
1Z
VCC
2DE
3DE
40
38
37
1Y
41
39
P11
GND
43
42
1DE
P12
44
VCC
46
45
S11
S10
47
3Z
29
VCC
3A
9
28
4Y
3B
10
27
4Z
EQ
11
26
GND
VBB
12
25
4DE
P32
30
23
7
8
24
2B
VCC
P31
3Y
P42
31
21
GND
6
22
5
2A
P41
GND
20
2Z
32
S40
33
S41
4
19
1B
VCC 18
2Y
16
1A
17
P21
4A
35
34
4B
2
3
15
Clock Buffering/Clock MUXing
Wireless Base Stations
High-Speed Network Routing
Telecom/Datacom
XAUI 802.3ae Protocol Backplane Redundancy
36
S21
GND
•
•
•
•
•
1
14
APPLICATIONS
S20
S31
•
•
•
•
The SN65LVCP404 is characterized for operation
from -40°C to 85°C.
48
•
•
•
•
•
•
Up to 4.25 Gbps Operation
Non-blocking Architecture Allows Each
Output to be Connected to Any Input
30 ps of Deterministic Jitter
Selectable Transmit Pre-Emphasis Per Lane
Selectable Receive Equalization
Available Packaging 48 Pin QFN
Propagation Delay Times: 500 ps Typical
Inputs Electrically Compatible With
CML Signal Levels
Operates From a Single 3.3-V Supply
Ability to 3-STATE ouputs
Low Power: 560 mW
Integrated Termination Resistors
13
•
•
S30
FEATURES
1
DESCRIPTION
The SN65LVCP404 is a 4x4 non-blocking crosspoint
switch in a flow-through pin-out allowing for ease in
PCB layout. VML signaling is used to achieve a
high-speed data throughput while using low power.
Each of the output drivers includes a 4:1 multiplexer
to allow any input to be routed to any output. Internal
signal paths are fully differential to achieve the high
signaling speeds while maintaining low signal skews.
The SN65LVCP404 incorporates 100-Ω termination
resistors for those applications where board space is
a premium. Built-in transmit pre-emphasis and
receive equalization for superior signal integrity
performance.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
SN65LVCP404
SLLS700B – MARCH 2007 – REVISED JANUARY 2009 ................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC DIAGRAM
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
Differential Inputs (with 50-Ω
termination to Vbb)
xA=P; xB=N
Line Side Differential Inputs CML compatible
High Speed I/O
xA
xB
3, 6, 9, 16
4, 7, 10, 17
xY
xZ
41, 34, 31, 28
40, 33, 30, 27
Differential Output xY=P; xZ=N
Switch Side Differential Outputs. VML
45, 38, 37, 25
Input
Data Enable; Active Low; LVTTL; When not enabled the ouput
is in 3-STATE mode for power savings
Control Signals
xDE
S10 - S41
1, 2, 13, 14, 19,
20, 47, 48
Input; S1x = Channel 1 bit one
Switching Selection; LVTTL
P11-P42
43, 44, 35, 36, 23,
24, 21, 22
Input; P1x- Channel 1 bit one
Output Preemphasis Control; LVTTL
Input; Selection for receive
equalization setting
EQ = 1 (default) is for the 5 dB setting, EQ = 0 is for the 12 dB
setting
Power
Power Supply 3.3v ±5%
EQ
11
Power Supply
VCC
8, 18, 29, 39, 46
GND
5, 15, 26, 32, 42
The ground center pad of the package must be connected to
GND plane.
Thermal Pad
VBB
2
12
Input
Receiver input biasing voltage. For ac coupling, VBB should be
left floating for optimal bias value. For dc coupling, VBB can
driven to change the common mode. VBB should not be tied to
ground.
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
IN+
RT(SE)
= 50 W
Gain
Stage
+ EQ
VCC
RBBDC
RT(SE)
= 50 W
IN−
VBB
ESD
LineEndTermination
Self−Biasing Network
Figure 1. Equivalent Input Circuit Design
OUT+
49.9 W
OUT−
49.9 W
VOCM
1 pF
Figure 2. Common-Mode Output Voltage Test Circuit
Table 1. CROSSPOINT LOGIC TABLES
OUTPUT CHANNEL 1
CONTROL
PINS
INPUT
SELECTED
OUTPUT CHANNEL 2
CONTROL
PINS
INPUT
SELECTED
OUTPUT CHANNEL 3
CONTROL
PINS
OUTPUT CHANNEL 4
INPUT
SELECTED
CONTROL
PINS
INPUT
SELECTED
S10
S11
1Y/1Z
S20
S21
2Y/2Z
S30
S31
3Y/3Z
S40
S41
4Y/4Z
0
0
1A/1B
0
0
1A/1B
0
0
1A/1B
0
0
1A/1B
0
1
2A/2B
0
1
2A/2B
0
1
2A/2B
0
1
2A/2B
1
0
3A/3B
1
0
3A/3B
1
0
3A/3B
1
0
3A/3B
1
1
4A/4B
1
1
4A/4B
1
1
4A/4B
1
1
4A/4B
AVAILABLE OPTIONS
(1)
TA
DESCRIPTION
-40°C to 85°C
Serial multiplexer
PACKAGED DEVICE (1)
RGZ (48 pin)
SN65LVCP404
The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP404RGZR).
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PACKAGE THERMAL CHARACTERISTICS
PACKAGE THERMAL CHARACTERISTICS (1)
NOM
UNIT
θJA (junction-to-ambient)
33
°C/W
θJB (junction-to-board)
20
°C/W
23.6
°C/W
θJC (junction-to-case)
PSI-jt (junction-to-top pseudo)
4-layer JEDEC Board (JESD51-7) using eight GND-vias θ-0.2 on the
center pad as shown in the section: Recommended PCB footprint with
boundary and environment conditions of JEDEC Board (JESD51-2)
PSI-jb (junction-to-board pseudo)
0.6
°C/W
19.4
°C/W
5.4
°C/W
θJP (junction-to-pad)
(1)
See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
Supply voltage range
(2)
–0.5 V to 6 V
Control inputs, all outputs
Voltage range
ESD
TJ
Receiver inputs
Human Body Model
(3)
Charged-Device Model (4)
3 kV
All pins
500 V
See Package Thermal Characteristics
Table
Maximum junction temperature
2
Reflow temperature package soldering, 4 seconds
(2)
(3)
(4)
4
–0.5 V to 4 V
All pins
Moisture sensitivity level
(1)
–0.5 V to (VCC + 0.5 V)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
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RECOMMENDED OPERATING CONDITIONS
dR
Operating data rate
VCC
Supply voltage
VCC(N)
Supply voltage noise amplitude
TJ
Junction temperature
TA
Operating free-air temperature (1)
MIN
NOM
MAX
UNIT
4.25
Gbps
3.135
3.3
3.465
10 Hz to 2.125 GHz
V
20
mV
125
°C
-40
85
°C
dR(in) ≤ 4.25 Gbps
100
1750
mVPP
1.25 Gbps < dR(in) ≤ 4.25 Gbps
100
1560
mVPP
dR(in) > 4.25 Gbps
100
1000
mVPP
Note: for best jitter performance ac
coupling is recommended.
1.5
DIFFERENTIAL INPUTS
Receiver peak-to-peak differential input
voltage (2)
VID
VICM
Receiver common-mode
input voltage
|V
VCC *
1.6
|
ID
2
V
CONTROL INPUTS
VIH
High-level input voltage
2
VCC + 0.3
V
VIL
Low-level input voltage
–0.3
0.8
V
120
Ω
DIFFERENTIAL OUTPUTS
RL
(1)
(2)
Differential load resistance
80
100
Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
Differential input voltage VID is defined as | IN+ – IN– |.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
DIFFERENTIAL INPUTS
VIT+
Positive going differential
input high threshold
VIT–
Negative going differential
input low threshold
A(EQ)
Equalizer gain
RT(D)
Termination resistance,
differential
VBB
Open-circuit Input voltage
(input self-bias voltage)
R(BBDC)
Biasing network dc
impedance
R(BBAC)
Biasing network ac
impedance
50
–50
at 1.875 GHz (EQ=0)
mV
12
80
AC-coupled inputs
mV
100
dB
120
Ω
1.6
V
30
kΩ
375 MHz
42
2.125 GHz
8.4
Ω
DIFFERENTIAL OUTPUTS
VODH
High-level output voltage
VODL
Low-level output voltage
VODB(PP)
Output differential voltage
without preemphasis (2)
VOCM
Output common mode voltage
ΔVOC(SS)
Change in steady-state
common-mode output voltage
between logic states
(1)
(2)
RL = 100 Ω ±1%,
Px_2 = Px_1=0;
4 Gbps alternating 1010-pattern;
Figure 3
1000
650
mVPP
–650
mVPP
1300
1500
1.65
See Figure 2
1
mVPP
V
mV
All typical values are at TA = 25°C and VCC = 3.3 V supply unless otherwise noted. They are for reference purposes and are not
production tested.
Differential output voltage V(ODB) is defined as | OUT+ – OUT– |.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Output preemphasis voltage
ratio,
V(PE)
V
RL = 100 Ω±1%;
x = L or S;
See Figure 3
ODB(PP)
VODPE(PP)
MIN
TYP (1)
Px_2:Px_1 = 00
0
Px_2:Px_1 = 01
3
Px_2:Px_1 = 10
6
Px_2:Px_1 = 11
9
MAX
UNIT
dB
t(PRE)
Preemphasis duration
measurement
Output preemphasis is set to 9 dB during test
Px_x = 1;
Measured with a 100-MHz clock signal;
RL = 100 Ω ±1%, See Figure 4
175
ps
ro
Output resistance
Differential on-chip termination between OUT+ and
OUT–
100
Ω
CONTROL INPUTS
IIH
High-level Input current
VIN = VCC
IIL
Low-level Input current
VIN = GND
R(PU)
Pullup resistance
5
-125
µA
-90
µA
35
kΩ
POWER CONSUMPTION
PD
Device power dissipation
All outputs terminated 100 Ω
PZ
Device power dissipation in
3-State
All outputs in 3-state
ICC
Device current consumption
All outputs
terminated 100 Ω
560
750
mW
600
mW
220
mA
TYP (1)
MAX
UNIT
3
6
ns
0.5
0.7
ns
0.5
0.7
ns
PRBS 27-1 pattern at 4.25
Gbps
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MULTIPLEXER
t(SM)
Multiplexer switch time
Multiplexer to valid output
DIFFERENTIAL OUTPUTS
tPLH
Low-to-high propagation
delay
tPHL
High-to-low propagation
delay
tr
Rise time
tf
Fall time
tsk(p)
Pulse skew, | tPHL – tPLH | (2)
tsk(o)
Output skew
(3)
tsk(pp)
Part-to-part skew (4)
tzd
3-State switch time to
Disable
tze
3-State switch time to
Enable
RJ
Device random jitter, rms
(1)
(2)
(3)
(4)
6
Propagation delay input to output
See Figure 6
20% to 80% of VO(DB); Test Pattern: 100-MHz clock signal;
See Figure 5 and Figure 8
80
ps
80
ps
20
ps
100
ps
300
ps
Assumes 50 Ω to Vcm and 150 pF load on each output
20
ns
Assumes 50 Ω to Vcm and 150 pF load on each output
10
ns
2
ps-rms
All outputs terminated with 100 Ω
See Figure 8 for test circuit.
BERT setting 10–15
Alternating 10-pattern.
25
0.8
All typical values are at 25°C and with 3.3 V supply unless otherwise noted.
tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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SWITCHING CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
0 dB preemphasis
Intrinsic deterministic device (PREx_x = 0);
jitter (5) (6), peak-to-peak
See Figure 8 for the test
circuit.
DJ
(5)
(6)
(7)
0 dB preemphasis
Absolute deterministic
(PREx_x = 0);
output jitter (7), peak-to-peak See Figure 8 for the test
circuit.
PRBS 27-1
pattern
MIN
4.25 Gbps
MAX
UNIT
30
1.25Gbps;
EQ=1
Over 25-inch
FR4 trace
PRBS 27-1
pattern
TYP (1)
4.25 Gbps;
EQ=0
Over FR4
trace 2-inch
to 43 inches
long
ps
7
ps
20
Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation
(DJ(OUT) – DJ(IN) ), where DJ(OUT) is the total peak-to-peak deterministic jitter measured at the output of the device in PSPP. DJ(IN) is the
peak-to-peak deterministic jitter of the pattern generator driving the device.
The SN65LVCP404 built-in passive input equalizer compensates for ISI. For a 25-inch FR4 transmission line with 8-mil trace width, the
LVCP404 typically reduces jitter by 60 ps from the device input to the device output.
Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP404 output. The value is a real measured
value with a Bit error tester as described in Figure 8. The absolute DJ reflects the sum of all deterministic jitter components accumulated
over the link: DJ(absolute) = DJ(Signal generator) + DJ(transmission line) + DJ(intrinsic(LVCP404)).
Table 2. Preemphasis Controls PL_2, PL_1, PS_2, and PS_1
(1)
Px_2 (1)
Px_1 (1)
OUTPUT
PREEMPHASIS
LEVEL IN dB
OUTPUT LEVEL IN mVpp
DE-EMPHASIZED
PRE-EMPHASIZED
TYPICAL FR4
TRACE LENGTH
0
0
0 dB
1200
1200
10 inches of FR4 trace
0
1
3 dB
850
1200
20 inches of FR4 trace
1
0
6 dB
600
1200
30 inches of FR4 trace
1
1
9 dB
425
1200
40 inches of FR4 trace
x = L or S
Table 3. Receive Equalization Settings
EQ
EQUALIZATION
TYPICAL TRACE
1
5 dB
25 inches of FR4
0
12 dB
43 inches of FR4
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PARAMETER MEASUREMENT INFORMATION
1−bit
1 to N bit
3−dB Preemphasis
VODPE3(pp)
9−dB Preemphasis
VOCM
VODB(PP)
VODPE2(pp)
6−dB Preemphasis
VODPE1(pp)
0−dB Preemphasis
VOH
VOL
Figure 3. Preemphasis and Output Voltage Waveforms and Definitions
1−bit
VODPE3(pp)
9−dB Preemphasis
1 to N bit
VODB(PP)
80%
20%
tPRE
Figure 4. t(PRE) Preemphasis Duration Measurement
80%
80%
VODB
20%
20%
tr
tf
Figure 5. Driver Output Transition Time
8
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PARAMETER MEASUREMENT INFORMATION (continued)
VID = 0 V
IN
t PHLD
t PLHD
VOD = 0 V
OUT
Figure 6. Propagation Delay Input to Output
VA
0V
VB
Clock Input
0V
Ideal Output
VY − VZ
1/fo
1/fo
Period Jitter
Cycle-to-Cycle Jitter
Actual Output
Actual Output
0V
0V
VY − VZ
VY − VZ
tc(n)
tc(n)
tc(n +1)
tjit(cc) = | tc(n) − tc(n + 1) |
tjit(pp) = | tc(n) − 1/fo |
Peak-to-Peak Jitter
VA
PRBS Input
VY
0V
VB
0V
VZ
PRBS Output
tjit(pp)
A.
All input pulses are supplied by an Agilent 81250 Stimulus System.
B.
The measurement is made with the AgilentParBert measurement software.
Figure 7. Driver Jitter Measurement Waveforms
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