SN65LVDS051DRG4Q1

SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 www.ti.com SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS Check for Samples: SN65LVDS180-Q1, SN65LVDS050-Q1, SN65LVDS051-Q1 FEATURES 1 • • • • • • • • • • • • Qualified for Automotive Applications ESD Protection Exceeds 2000 V Per MIL-STD883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard Signaling Rates up to 400 Mbps Bus-Terminal ESD Exceeds 12 kV Operates From a Single 3.3-V Supply Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 100-Ω Load Propagation Delay Times – Driver: 1.7 ns Typ – Receiver: 3.7 ns Typ Power Dissipation at 200 MHz – Driver: 25 mW Typical – Receiver: 60 mW Typical LVTTL Input Levels Are 5-V Tolerant Receiver Maintains High Input Impedance With VCC < 1.5 V Receiver Has Open-Circuit Fail Safe DESCRIPTION The SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-Ω load and receipt of 50-mV signals with up to 1 V of ground potential difference between a transmitter and receiver. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state but rather disconnects the input and reduces the quiescent power used by the device. (For these functions with a high-impedance driver output, see the SN65LVDM series of devices.) All devices are characterized for operation from −40°C to 85°C. ORDERING INFORMATION (1) TA -40°C to 85°C (1) (2) (3) PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC (D) Tape and reel SN65LVDS180DRQ1 VDS180Q TSSOP (PW) Tape and reel SN65LVDS180PWRQ1 VDS180Q SOIC (D) Tape and reel SN65LVDS050DRQ1 (3) VDS050Q TSSOP (PW) Tape and reel SN65LVDS050IPWRQ1 VDS050Q SOIC (D) Tape and reel SN65LVDS051DRQ1 VDS051Q TSSOP (PW) Tape and reel SN65LVDS051PWRQ1 VDS051Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Product Preview FUNCTION TABLES SN65LVDS180, SN65LVDS050, and SN65LVDS051 RECEIVER (1) INPUTS (1) OUTPUT VID = VA - VB RE R VID≥ 50 mV L H -50 mV < VID < 50 mV L ? VID≤ -50 mV L L Open L H X H Z H = high level, L = low level, Z = high impedance, X = don't care, ? = indeterminate SN65LVDS180, SN65LVDS050, and SN65LVDS051 DRIVER (1) INPUTS (1) 2 OUTPUTS D DE Y Z H L H L H H H L Open H L H X L OFF OFF H = high level, L = low level, Z = high impedance, X = don't care, OFF = no output Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 www.ti.com SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 3 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT VCC Supply voltage range (2) –0.5 V to 4 V Voltage range |VOD| D, R, DE, RE –0.5 V to 6 V Y, Z, A, and B –0.5 V to 4 V Differential output voltage 1V Electrostatic discharge Y, Z, A, B , and GND (see (3) ) Class 3, A:12 kV, B:600 V All Class 3, A:7 kV, B:500 V Continuous power dissipation See Dissipation Rating Table Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) 250°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages are with respect to network ground terminal. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE (1) PACKAGE TA≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C (1) TA = 85°C POWER RATING PW(14) 736 mW 5.9 mW/°C 383 mW PW(16) 839 mW 6.7 mW/°C 437 mW D(8) 635 mW 5.1 mW/°C 330 mW/°C D(14) 987 mW 7.9 mW/°C 513 mW/°C D(16) 1110 mW 8.9 mW/°C 577 mW/°C This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no airflow. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VCC Supply voltage 3 3.3 3.6 VIH High-level input voltage 2 VIL Low-level input voltage |VID| Magnitude of differential input voltage |VOD(dis)| Magnitude of differential output voltage with disabled driver VOY or VOZ Driver output voltage VIC Common-mode input voltage (see Figure 5) TA Operating free-air temperature V V 0.8 V 0.6 V 520 mV 2.4 V 0.1 0 ŤV Ť ŤV Ť ID 2 UNIT 2.4 * ID 2 V VCC- 0.8 4 Submit Documentation Feedback –40 85 °C Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 www.ti.com SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) MIN TYP (1) MAX Driver and receiver enabled, no receiver load, driver RL = 100 Ω 9 12 Driver enabled, receiver disabled, RL = 100 Ω 5 7 Driver disabled, receiver enabled, no load 1.5 2 Disabled 0.5 1 Drivers and receivers enabled, no receiver loads, driver RL = 100 Ω 12 20 Drivers enabled, receivers disabled, RL = 100 Ω 10 16 3 6 PARAMETER TEST CONDITIONS SN65LVDS180 Supply current ICC SN65LVDS050 SN65LVDS051 (1) Drivers disabled, receivers enabled, no loads Disabled 0.5 1 Drivers enabled, No receiver loads, driver RL = 100 Ω 12 20 3 6 MIN TYP MAX 247 340 454 Drivers disabled, no loads UNIT mA mA mA All typical values are at 25°C and with a 3.3-V supply. DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER |VOD| Differential output voltage magnitude Δ|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ΔVOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage IIH High-level input current IIL Low-level input current IOS Short-circuit output current DE D DE D TEST CONDITIONS RL = 100 Ω, See Figure 3 and Figure 2 -50 1.125 See Figure 3 50 1.2 –50 1.375 V mV mV 50 150 –20 2 20 –0.5 –10 2 10 VOY or VOZ = 0 V 3 10 VOD = 0 V 3 10 VIL = 0.8 V mV 50 –0.5 VIH = 5 V UNIT μA μA mA DE = OV VOY = VOZ = OV IO(OFF) Off-state output current CIN Input capacitance Copyright © 2003–2013, Texas Instruments Incorporated –1 DE = VCC VOY = VOZ = OV, VCC < 1.5 V 1 3 Submit Documentation Feedback Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 μA pF 5 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIT+ Positive-going differential input voltage threshold VIT- Negative-going differential input voltage threshold VOH High-level output voltage VOL Low-level output voltage TEST CONDITIONS See Figure 5 and MIN TYP (1) MAX 50 –50 IOH = -8 mA 2.4 IOH = -4 mA 2.8 mV V IOL = 8 mA 0.4 VI = 0 UNIT –2 –11 –1.2 –3 –20 V μA II Input current (A or B inputs) II(OFF) Power-off input current (A or B inputs) VCC = 0 ±20 μA IIH High-level input current (enables) VIH = 5 V ±10 μA IIL Low-level input current (enables) VIL = 0.8 V ±10 μA IOZ High-impedance output current ±10 μA CI Input capacitance (1) VI = 2.4 V VO = 0 or 5 V 5 pF All typical values are at 25°C and with a 3.3-V supply. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 1.7 2.7 ns tPHL Propagation delay time, high-to-low-level output 1.7 2.7 ns 0.8 1 ns 0.8 1 ns RL = 100 Ω, CL = 10 pF, See Figure 2 tr Differential output signal rise time tf Differential output signal fall time tsk(p) Pulse skew (|tpHL - tpLH|) (2) 300 ps tsk(o) Channel-to-channel output skew (3) 150 ps ten Enable time tdis Disable time (1) (2) (3) See Figure 4 4.3 10 ns 3.1 10 ns All typical values are at 25°C and with a 3.3-V supply. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 3.7 4.5 ns 3.7 4.5 ns UNIT tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) Pulse skew (|tpHL - tpLH|) (2) tr Output signal rise time 0.7 1.5 ns tf Output signal fall time 0.9 1.5 ns tPZH Propagation delay time, high-impedance-to-high-level output 2.5 ns tPZL Propagation delay time, high-impedance-to-low-level output 2.5 ns tPHZ Propagation delay time, high-level-to-high-impedance output 7 ns tPLZ Propagation delay time, low-level-to-high-impedance output 4 ns (1) (2) 6 CL = 10 pF, See Figure 6 0.3 See Figure 7 ns All typical values are at 25°C and with a 3.3-V supply. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 www.ti.com SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 PARAMETER MEASUREMENT INFORMATION DRIVER IOY Driver Enable Y II A IOZ VOD V VOY Z VI OY )V OZ 2 VOC VOZ Figure 1. Driver Voltage and Current Definitions Driver Enable Y 100 Ω ±1% VOD Input Z CL = 10 pF (2 Places) 2V 1.4 V 0.8 V Input tPHL tPLH 100% 80% VOD(H) Output 0V VOD(L) 20% 0% tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 7 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 4. Enable and Disable Time Circuit and Definitions 8 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 www.ti.com SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 PARAMETER MEASUREMENT INFORMATION (continued) RECEIVER A V IA )V IB VID 2 R VIA B VIC VO VIB Figure 5. Receiver Voltage Definitions Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES (V) RESULTING DIFFERENTIAL INPUT VOLTAGE (mV) RESULTING COMMONMODE INPUT VOLTAGE (V) VIA VIB VID VIC 1.25 1.15 100 1.2 1.15 1.25 –100 1.2 2.4 2.3 100 2.35 2.3 2.4 –100 2.35 0.1 0 100 0.05 0 0.1 –100 0.05 1.5 0.9 600 1.2 0.9 1.5 –600 1.2 2.4 1.8 600 2.1 1.8 2.4 –600 2.1 0.6 0 600 0.3 0 0.6 –600 0.3 Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 9 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 A. www.ti.com All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 6. Timing Test Circuit and Waveforms 10 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 www.ti.com SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 Figure 7. Enable/Disable Time Test Circuit and Waveforms Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 11 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS DISABLED DRIVER OUTPUT CURRENT vs OUTPUT VOLTAGE Disabled Driver Output Current − mA 40 VCC = 3.3 V TA = 25°C DE = 0 V 30 Other output at 0 V 20 Other output at 1.2 V 10 VOZ = VOY 0 −10 Other output at 2.4 V −20 −30 0 0.5 1 1.5 2 VO − Output Voltage − V Figure 8. DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3.5 VCC = 3.3 V TA = 25°C VOH − High-Level Output Voltage − V VOL − Low-Level Output Voltage − V 3 DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 3 2 1 VCC = 3.3 V TA = 25°C 3 2.5 2 1.5 1 0.5 0 0 0 2 4 IOL − Low-Level Output Current − mA Figure 9. 12 2.5 Submit Documentation Feedback 6 −4 −3 −2 −1 0 IOH − High-Level Output Current − mA Figure 10. Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 www.ti.com SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS (continued) RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 5 4 VCC = 3.3 V TA = 25°C VOH − High-Level Output Voltage − V VOL − Low-Level Output Votlage − V VCC = 3.3 V TA = 25°C 4 3 2 1 0 0 10 20 30 40 50 IOL − Low-Level Output Current − mA Figure 11. VCC = 3 V VCC = 3.6 V 1.5 −50 −30 −10 10 50 30 70 TA − Free-Air Temperature − °C Figure 13. Copyright © 2003–2013, Texas Instruments Incorporated 90 1 −60 −40 −20 IOH − High-Level Output Current − mA Figure 12. 0 DRIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.5 t PLH − Low-To-High Propagation Delay Time − ns t PHL − High-To-Low Propagation Delay Time − ns VCC = 3.3 V 2 0 −80 60 DRIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.5 2 3 2 VCC = 3.3 V VCC = 3 V VCC = 3.6 V 1.5 −50 −30 10 −10 50 30 70 TA − Free-Air Temperature − °C Figure 14. Submit Documentation Feedback Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 90 13 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) t PLH − High-To-Low Level Propagation Delay Time − ms RECEIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 4.5 VCC = 3.3 V 4 VCC = 3 V 3.5 VCC = 3.6 V 3 2.5 −50 −30 10 −10 50 30 70 TA − Free−Air Temperature − °C Figure 15. 90 t PLH − Low-To-High Level Propagation Delay Time − ns RECEIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 14 Submit Documentation Feedback 4.5 VCC = 3 V 4 VCC = 3.3 V 3.5 VCC = 3.6 V 3 2.5 −50 −30 10 −10 50 30 70 TA − Free-Air Temperature − °C Figure 16. 90 Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 www.ti.com SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 APPLICATION INFORMATION The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground differences are less than 1 V with a low common-mode output and balanced interface for low noise emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL speeds without the power and dual supply requirements. Transmission Distance – m 1000 30% Jitter 100 5% Jitter 10 1 24 AWG UTP 96 Ω (PVC Dielectric) 0.1 100k 1M 10M 100M Data Rate – Hz Figure 17. Data Transmission Distance Versus Rate FAIL SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between -100 mV and 100 mV and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 11. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to VCC - 0.4 V to detect this condition and force the output to a high-level regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt 100 Ω Typ Y B VIT ≈ 2.3 V Figure 18. Open-Circuit Fail Safe of the LVDS Receiver Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 15 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 www.ti.com It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. spacer 16 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 www.ti.com SGLS204C – SEPTEMBER 2003 – REVISED MARCH 2013 REVISION HISTORY Changes from Original (September 2003) to Revision A Page • Deleted Feature: "Qualification in Accordance With AEC-Q100†" ....................................................................................... 1 • Deleted Feature: "Customer-Specific Configuration Control..." ............................................................................................ 1 Changes from Revision A (April 2008) to Revision B • Page Changed device number From: SN65LVDS050PWRQ1 To: SN65LVDS050IPWRQ1. Changed the device status to Production ............................................................................................................................................................................. 2 Changes from Revision B (November 2011) to Revision C • Page Deleted device SN65LVDS179-Q1 ....................................................................................................................................... 1 Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN65LVDS180-Q1 SN65LVDS050-Q1 SN65LVDS051-Q1 17 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVDS050IPWRQ1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VDS050Q SN65LVDS051DRG4Q1 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VDS051Q SN65LVDS051PWRG4Q1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VDS051Q SN65LVDS051PWRQ1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VDS051Q SN65LVDS180PWRG4Q1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VDS180Q SN65LVDS180PWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VDS180Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of