SN65LVDS19DRFRG4

SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 www.ti.com SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS • FEATURES • • • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs Clock Rates to 1 GHz – 250-ps Output Transition Times – 0.12 ps Typical Intrinsic Phase Jitter – Less than 630 ps Propagation Delay Times 2.5-V or 3.3-V Supply Operation 2-mm x 2-mm Small-Outline No-Lead Package APPLICATIONS • • PECL-to-LVDS Translation Clock Signal Amplification DESCRIPTION These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19. The SN65LVx18 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx19 defaults to 575 mV as well. Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open. All devices are characterized for operation from –40°C to 85°C. SN65LVDS19, SN65LVP19 SN65LVDS18, SN65LVP18 Q Q 4 mA 4 mA A Y A Y Z B Z VBB VREF VCC VBB EN VREF VCC EN GC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 www.ti.com SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS (1) INPUT OUTPUT GAIN CONTROL BASE PART NUMBER PART MARKING Single-ended LVDS Yes SN65LVDS18 ER Single-ended LVPECL Yes SN65LVP18 EP Differential LVDS No SN65LVDS19 ET Differential LVPECL No SN65LVP19 ES (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT (2) VCC Supply voltage VI Input voltage –0.5 V to VCC + 0.5 V VO Output voltage –0.5 V to VCC + 0.5 V IO VBB output current (1) (2) (3) (4) –0.5 V to 4 V ±0.5 mA HBM electrostatic discharge (3) ±3 kV CDM electrostatic discharge (4) ±1500 V Continuous power dissipation See Power Dissipation Ratings Table Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground (see Figure 1). Tested in accordance with JEDEC Standard 22, Test Method A114-A-7 Tested in accordance with JEDEC Standard 22, Test Method C101 DISSIPATION RATINGS PACKAGE TA < 25°C POWER RATING OPERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING DRF 403 mW 4.0 mW/°C 161 mW RECOMMENDED OPERATING CONDITIONS MIN NOM 2.375 2.5 or 3.3 MAX UNIT VCC Supply Voltage 3.6 V VIC Common-mode input voltage (VIA + VIB)/2 SN65LVDS19 or SN65LVP19 1.2 VCC – (VID/2) V |VID| Differential input voltage magnitude |VIA - VIB| SN65LVDS19 or SN65LVP19 0.8 1 V VIH High-level input voltage VIL Low-level input voltage IO Output current to VBB RL Differential load resistance TA Operating free-air temperature (1) 2 EN SN65LVDS18 or SN65LVP18 EN SN65LVDS18 or SN65LVP18 2 VCC VCC– 1.17 VCC– 0.44 V 0 0.8 VCC– 2.25 VCC– 1.52 –400 (1) 400 90 132 Ω -40 85 °C The algebraic convention, where the least positive (more negative) value is designated minimum, is used in this data sheet. V µA SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 www.ti.com SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) TYP (1) MAX RL = 100 Ω, EN at 0 V, Other inputs open 30 36 Outputs unloaded, EN at 0 V, Other inputs open 17 22 VCC– 1.35 VCC– 1.25 PARAMETER ICC Supply current TEST CONDITIONS MIN UNIT mA VBB Reference voltage (2) IBB = –400 µA IIH High-level input current, EN VI = 2 V –20 20 IIAH or IIBH High-level input current, A or B VI = VCC –20 20 IIL Low-level input current, EN VI = 0.8 V –20 20 IIAL or IIBL Low-level input current, A or B VI = GND –20 20 VCC– 1.44 V µA SN65LVDS18/19 Y AND Z OUTPUT CHARACTERISTICS |VOD| Differential output voltage magnitude, |VOY– VOZ| ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common- mode output voltage (see Figure 3) ∆VOC(SS) Change in steady-state common-mode output voltage between logic states 247 340 454 mV See Figure 1 and Figure 2 50 1.125 1.375 –50 50 See Figure 3 V mV VOC(PP) Peak-to-peak common-mode output voltage IOYZ or IOZZ High-impedance output current EN at VCC, VO = 0 V or VCC –1 1 IOYS or IOZS Short-circuit output current EN at 0 V, VOY or VOZ = 0 V –50 50 IOS(D) Differential short-circuit output current, |IOY– IOZ| EN at 0 V, VOY = VOZ –12 12 VCC– 1.13 VCC– 0.85 VCC– 1.87 VCC– 1.61 VCC– 1.92 VCC– 1.61 50 100 µA mA SN65LVP18/19 Y AND Z OUTPUT CHARACTERISTICS VOYH or VOZH High-level output voltage VOYL or VOZL Low-level output voltage VOYL or VOZL Low-level output voltage |VOD| Differential output voltage magnitude, |VOH– VOL| IOYZ or IOZZ High-impedance output current 3.3 V; 50 Ω from Y and Z to VCC - 2 V 2.5 V; 50 Ω from Y and Z to VCC– 2 V V 0.6 EN at VCC, VO = 0 V or VCC 0.8 –1 1 1 µA Q OUTPUT CHARACTERISTICS (see Figure 1) VOH High-level output voltage VOL Low-level output voltage VO(pp) (1) (2) Peak-to-peak output voltage No load VCC– 0.94 GC Tied to GND, No load VCC– 1.22 GC Open, No load VCC– 1.52 GC Tied to VCC, No load VCC– 1.82 GC Tied to GND 300 GC Open 575 CGT Tied to VCC 860 V V mV Typical values are at room temperature and with a VCC of 3.3 V. Single-ended input operation is limited to VCC≥ 3.0 V. 3 SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 www.ti.com SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPD Propagation delay time, tPLH or tPHL tSK(P) Pulse skew, |tPLH - tPHL| tSK(PP) Part-to-part skew A to Q D to Y or Z (2) 20%-to-80% differential signal rise time tf 20%-to-80% differential signal fall time tjit(per) RMS period jitter (3) tjit(cc) Peak cycle-to-cycle jitter tjit(ph) Intrinsic phase jitter tPHZ Propagation delay time, high-level-to-high-impedance output tPLZ Propagation delay time, low-level-to-high-impedance output 340 460 460 630 VCC = 3.3 V 80 VCC = 2.5 V 130 LVDS, See Figure 4 140 250 LVPECL, See Figure 4 190 300 LVDS, See Figure 4 140 250 LVPECL, See Figure 4 210 300 2-GHz 50%-duty-cycle square-wave input, See Figure 5 (4) 1 GHz tPZH Propagation delay time, high-impedance-to-high-level output tPZL Propagation delay time, high-impedance-to-low-level output (3) (4) See Figure 4 TYP (1) MAX UNIT 2 4 17 24 0.12 ps ps ps ps ps 30 30 See Figure 6 ns 30 30 Typical values are at room temperature and with a VCC of 3.3 V. Part-to-part skew is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles. Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle pairs. PARAMETER MEASUREMENT INFORMATION VCC ICC 8 VCC 2 IIA IIGC II VIA VIB + _ Q A VBB 4 GC D.U.T. Z 5 Y EN GND 9 1 3 IBB 6 50
S1 IOZ 7 50
IOY VCC − 2 V CL VI + _ + _ + _ + + + + VOY VOZ VBB VO − − − − (1) CL is the instrumentation and test fixture capacitance. (2) S1 is open for the SN65LVDS18 and closed for the SN65LVP18. + VOC − Figure 1. Output Voltage Test Circuit and Voltage and Current Definitions for LVDS/LVP18 4 ps 20 tr (1) (2) MIN SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 www.ti.com SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) VCC ICC 8 VCC 2 IIA IIB II VIA VIB + _ Q A 3 B D.U.T. 5 EN GND 9 VBB Z Y 1 4 50
IBB 6 S1 IOZ 7 50
IOY VCC − 2 V CL VI + _ + _ + + + + VOY VOZ VBB VO − − − − + _ (1) CL is the instrumentation and test fixture capacitance. (2) S1 is open for the SN65LVDS19 and closed for the SN65LVP19. + VOC − Figure 2. Output Voltage Test Circuit and Voltage and Current Definitions for LVDS/LVP19 INPUT dVOC(SS) VOC(PP) VOC Figure 3. VOC Definitions VCC 1.2 V 1.125 V VIA 1.5 V VIB t PHL t PLH VOY − VOZ 80% 100% 50% tf tr 20% Figure 4. Propagation Delay and Transition Time Test Waveforms 5 SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 www.ti.com SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) 50
Cable, X  Y cm, SMA Coax Connectors, 4 Places TDS Oscilloscope with TJIT3 Analysis Pack Device Under Test HP3104 Pattern Generator 50
50
DC Figure 5. Jitter Measurement Setup VCC 1.2 V VIA 1.5 V VIB VI to EN 2V 1.4 V t PZH t PZL t PHZ 0.8 V t PLZ 0V VOY − VOZ 80% 50% 20% Figure 6. Enable and Disable Time Test Waveforms 6 100% SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 www.ti.com SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 DEVICE INFORMATION FUNCTION TABLE SN65LVDS18, SN65LVP18 (1) SN65LVDS19, SN65LVP19 A EN Q Y Z A B EN Q Y H L L H L H H L ? ? Z ? L L H L H L H L H L H L X H ? Z Z H L L L H Open L ? ? ? L L L ? ? ? X Open ? ? ? X X H ? Z Z Open Open L ? ? ? X X Open ? ? ? (1) H = high, L = low, Z = high impedance, ? = indeterminate DRF PACKAGE TOP VIEW 1 4 9 8 5 BOTTOM VIEW Package Pin Assignments – Numerical Listing SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 PIN SIGNAL PIN SIGNAL 1 Q 1 Q 2 A 2 A 3 VBB 3 B 4 GC 4 VBB 5 EN 5 EN 6 Z 6 Z 7 Y 7 Y 8 VCC 8 VCC 9 GND 9 GND 7 SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 www.ti.com SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 55 35 LVDS18/19 25 15 200 400 600 800 LVP18/19 = Loaded 45 35 LVDS18/19 25 1000 tr −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 TA − Free−Air Temperature − C Figure 7. Figure 8. Figure 9. LVP18/19 RISE/FALL TIME vs FREE-AIR TEMPERATURE LVDS18/19 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE PERIOD JITTER vs FREQUENCY tf 210 200 tr 190 180 170 524 5 500 4 476 tPHL 452 tPLH Period Jitter − ps Propagation Delay Time − ps 220 tr/tf − Rise/Fall Time − ps 136 TA − Free−Air Temperature − C 230 428 404 −20 0 20 40 60 80 −40 100 −20 0 20 40 60 80 100 TA − Free−Air Temperature − C Figure 10. Figure 11. 3 2 25 20 15 10 5 0 0 200 400 600 800 f − Frequency − MHz Figure 13. 0 0 200 400 600 800 f − Frequency − MHz Figure 12. CYCLE-TO-CYCLE JITTER vs FREQUENCY Cycle−To−Cycle Jitter − ps 100 1 TA − Free−Air Temperature − C 8 tf 144 120 −40 f − Frequency − MHz −40 152 128 15 5 0 160 tr/tf − Rise/Fall Time − ps LVP18/19 = Loaded 45 I CC − Supply Current − mA I CC − Supply Current − mA 55 5 LVDS18/19 RISE/FALL TIME vs FREE-AIR TEMPERATURE 1000 1000 SN65LVDS18, SN65LVP18 SN65LVDS19, SN65LVP19 www.ti.com SLLS624B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS OUTPUT LVP18/19 OUTPUT LVDS18/19 VCC R VCC VCC VCC VCC R Y VCC Y 7V Z Z 7V 7V 7V ENABLE VCC 400 Ω 300 kΩ 7V INPUT VCC OUTPUT VBB VCC A VCC VCC B VBB VBB 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVDS18DRFT ACTIVE WSON DRF 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ER SN65LVDS19DRFT ACTIVE WSON DRF 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ET SN65LVP18DRFT ACTIVE WSON DRF 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 EP SN65LVP19DRFT ACTIVE WSON DRF 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ES (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of