SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
SLLS261N – JULY 1997 – REVISED APRIL 2021
SNx5LVDSxx High-Speed Differential Line Drivers
1 Features
3 Description
•
The SN55LVDS31, SN65LVDS31, SN65LVDS3487,
and SN65LVDS9638 devices are differential line
drivers that implement the electrical characteristics
of low-voltage differential signaling (LVDS). This
signaling technique lowers the output voltage levels
of 5-V differential standard levels (such as TIA/
EIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3.3-V
supply rail. Any of the four current-mode drivers
will deliver a minimum differential output voltage
magnitude of 247 mV into a 100-Ω load when
enabled.
•
•
•
•
•
•
•
•
•
•
Meet or Exceed the Requirements of ANSI TIA/
EIA-644 Standard
Low-Voltage Differential Signaling With Typical
Output Voltage of 350 mV and 100-Ω Load
Typical Output Voltage Rise and Fall Times of 500
ps (400 Mbps)
Typical Propagation Delay Times of 1.7 ns
Operate From a Single 3.3-V Supply
Power Dissipation 25 mW Typical Per Driver at
200 MHz
Driver at High-Impedance When Disabled or With
VCC = 0
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Input Levels
Pin Compatible With AM26LS31, MC3487, and
μA9638
Cold Sparing for Space and High-Reliability
Applications Requiring Redundancy
Device Information(1)
PART NUMBER
SN55LVDS31
2 Applications
SN65LVDS31
•
•
•
SN65LVDS3487
Wireless Infrastructure
Telecom Infrastructure
Printers
SN65LVDS9638
(1)
EQUIVALENT OF EACH A INPUT
PACKAGE
BODY SIZE (NOM)
LCCC (20)
8.89 mm × 8.89 mm
CDIP (16)
19.56 mm × 6.92 mm
CFP (16)
10.30 mm × 6.73 mm
SOIC (16)
9.90 mm × 3.91 mm
SOP (16)
10.30 mm × 5.30 mm
TSSOP (16)
5.00 mm × 4.40 mm
SOIC (16)
9.90 mm × 3.91 mm
TSSOP (16)
5.00 mm × 4.40 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
HVSSOP (8)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS
TYPICAL OF ALL OUTPUTS
VCC
VCC
VCC
50 Ω
50 Ω
Input
Input
10 kΩ
7V
7V
300 kΩ
5Ω
Y or Z
Output
7V
Equivalent Input and Output Schematic Diagrams
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
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SLLS261N – JULY 1997 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (Continued)..................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings(1) .................................... 7
7.2 ESD Ratings............................................................... 7
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics: SN55LVDS31.................... 9
7.6 Electrical Characteristics: SN65LVDSxxxx............... 10
7.7 Switching Characteristics: SN55LVDS31..................10
7.8 Switching Characteristics: SN65LVDSxxxx...............11
7.9 Typical Characteristics.............................................. 12
8 Parameter Measurement Information.......................... 13
8.1 .................................................................................. 13
9 Detailed Description......................................................15
9.1 Overview................................................................... 15
9.2 Functional Block Diagram......................................... 15
9.3 Feature Description...................................................15
9.4 Device Functional Modes..........................................17
10 Application and Implementation................................ 18
10.1 Application Information........................................... 18
10.2 Typical Application.................................................. 18
11 Power Supply Recommendations..............................24
11.1 ................................................................................ 24
12 Layout...........................................................................25
12.1 Layout Guidelines................................................... 25
12.2 Layout Example...................................................... 27
13 Device and Documentation Support..........................29
13.1 Device Support....................................................... 29
13.2 Documentation Support.......................................... 29
13.3 Support Resources................................................. 29
13.5 Electrostatic Discharge Caution..............................30
13.6 Glossary..................................................................30
14 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
Changes from Revision M (August 2014) to Revision N (April 2021)
Page
• Added thermal data for SN65LVDS9638 in DGK package.................................................................................7
Changes from Revision L (July 2007) to Revision M (August 2014)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
Changes from Revision K (March 2004) to Revision L (July 2007)
Page
• Added Cold Sparing Feature.............................................................................................................................. 1
• Added Cold Sparing information.......................................................................................................................15
2
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SLLS261N – JULY 1997 – REVISED APRIL 2021
5 Description (Continued)
The intended application of these devices and signaling technique is both point-to-point and multidrop (one
driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The
transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance
of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.
The SN65LVDS31, SN65LVDS3487, and SN65LVDS9638 devices are characterized for operation from –40°C to
85°C. The SN55LVDS31 device is characterized for operation from –55°C to 125°C.
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SLLS261N – JULY 1997 – REVISED APRIL 2021
6 Pin Configuration and Functions
SN55LVDS31 . . . J OR W
SN65LVDS31 . . . D OR PW
(Marked as LVDS31 or 65LVDS31)
(TOP VIEW)
1A
1Y
1Z
G
2Z
2Y
2A
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4A
4Y
4Z
G
3Z
3Y
3A
1A
NC
VCC
3
2
1
20 19
4A
1Y
SN55LVDS31FK
(TOP VIEW)
18 4Y
G
5
17 4Z
NC
6
16 NC
2Z
7
15 G
2Y
8
14 3Z
3Y
3A
10 11 12 13
NC
9
GND
4
2A
1Z
SN65LVDS3487D
(Marked as LVDS3487 or 65LVDS3487)
(TOP VIEW)
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4A
4Y
4Z
3,4EN
3Z
3Y
3A
SN65LVDS9638D (Marked as DK638 or LVDS38)
SN65LVDS9638DGN (Marked as L38)
SN65LVDS9638DGK (Marked as AXG)
(TOP VIEW)
VCC
1A
2A
GND
1
8
2
7
3
6
4
5
1Y
1Z
2Y
2Z
Table 6-1. Pin Functions: SN55LVDS31 J or W, SN65LVDS31 D or PW
PIN
NAME
4
NUMBER
I/O
DESCRIPTION
VCC
16
–
Supply voltage
GND
8
–
Ground
1A
1
I
LVTTL input signal
1Y
2
O
Differential (LVDS) non-inverting output
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SLLS261N – JULY 1997 – REVISED APRIL 2021
Table 6-1. Pin Functions: SN55LVDS31 J or W, SN65LVDS31 D or PW (continued)
PIN
NAME
NUMBER
I/O
DESCRIPTION
1Z
3
O
Differential (LVDS) inverting output
2A
7
I
LVTTL input signal
2Y
6
O
Differential (LVDS) non-inverting output
2Z
5
O
Differential (LVDS) inverting output
3A
9
I
LVTTL input signal
3Y
10
O
Differential (LVDS) non-inverting output
3Z
11
O
Differential (LVDS) inverting output
4A
15
I
LVTTL input signal
4Y
14
O
Differential (LVDS) non-inverting output
4Z
13
O
Differential (LVDS) inverting output
G
4
I
Enable (HI = ENABLE)
G/
12
I
Enable (LO = ENABLE)
Table 6-2. Pin Functions: SN65LVDS31FK
PIN
NAME
NUMBER
I/O
DESCRIPTION
VCC
20
–
Supply voltage
GND
10
–
Ground
1A
2
I
LVTTL input signal
1Y
3
O
Differential (LVDS) non-inverting output
1Z
4
O
Differential (LVDS) inverting output
2A
9
I
LVTTL input signal
2Y
8
O
Differential (LVDS) non-inverting output
2Z
7
O
Differential (LVDS) inverting output
3A
12
I
LVTTL input signal
3Y
13
O
Differential (LVDS) non-inverting output
3Z
14
O
Differential (LVDS) inverting output
4A
19
I
LVTTL input signal
4Y
18
O
Differential (LVDS) non-inverting output
4Z
17
O
Differential (LVDS) inverting output
G
5
I
Enable (HI = ENABLE)
G/
15
I
Enable (LO = ENABLE)
NC
1, 6, 11, 16
–
No connection
Table 6-3. Pin Functions: SN65LVDS3487D
PIN
NAME
NUMBER
I/O
DESCRIPTION
VCC
16
–
Supply voltage
GND
8
–
Ground
1A
1
I
LVTTL input signal
1Y
2
O
Differential (LVDS) non-inverting output
1Z
3
O
Differential (LVDS) inverting output
2A
7
I
LVTTL input signal
2Y
6
O
Differential (LVDS) non-inverting output
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Table 6-3. Pin Functions: SN65LVDS3487D (continued)
PIN
NAME
NUMBER
I/O
DESCRIPTION
2Z
5
O
Differential (LVDS) inverting output
3A
9
I
LVTTL input signal
3Y
10
O
Differential (LVDS) non-inverting output
3Z
11
O
Differential (LVDS) inverting output
4A
15
I
LVTTL input signal
4Y
14
O
Differential (LVDS) non-inverting output
4Z
13
O
Differential (LVDS) inverting output
1,2EN
4
I
Enable for channels 1 and 2
3,4EN
12
I
Enable for channels 3 and 4
Table 6-4. Pin Functions: SN65LVDS9638D, SN65LVDS9638DGN, SN65LVDS9638DGK
PIN
NAME
6
NUMBER
I/O
DESCRIPTION
VCC
1
–
Supply voltage
GND
4
–
Ground
1A
2
I
LVTTL input signal
1Y
8
O
Differential (LVDS) non-inverting output
1Z
7
O
Differential (LVDS) inverting output
2A
3
I
LVTTL input signal
2Y
6
O
Differential (LVDS) non-inverting output
2Z
5
O
Differential (LVDS) inverting output
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SLLS261N – JULY 1997 – REVISED APRIL 2021
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range(2)
–0.5
4
V
VI
Input voltage range
–0.5
VCC + 0.5
V
Continuous total power dissipation
See Section 7.4
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
Tstg
Storage temperature
–65
260
°C
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
7.2 ESD Ratings
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
(1)
VALUE
UNIT
±8000
V
260
°C
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
3.3
3.6
VCC
Supply voltage
3
VIH
High-level input voltage
2
VIL
Low-level input voltage
TA
Operating free-air
temperature
UNIT
V
V
0.8
SN65 prefix
–40
85
SN55 prefix
–55
125
V
°C
7.4 Thermal Information
SN55LVDS31
THERMAL METRIC(1)
RθJA
SN65LVDS31
SN65LVDS3487
SN65LVDS9638
FK
J
W
D
NS
PW
D
PW
20
PINS
16
PINS
16
PINS
16
PINS
16
PINS
16
PINS
16
PINS
16
PINS
84.8
86.0
179.5
46.0
44.2
72.3
26.4
101.5
Junction-to-ambient
thermal resistance
RθJC(top) Junction-to-case (top)
thermal resistance
D
DGK
UNIT
8 PINS 8 PINS 8 PINS
RθJB
Junction-to-board
thermal resistance
41.8
ψJT
Junction-to-top
characterization
parameter
11.1
10.9
11
ψJB
Junction-to-board
characterization
parameter
41.5
46.1
99.7
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DGN(2)
°C/W
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SN55LVDS31
SN65LVDS3487
SN65LVDS9638
D
DGK
DGN(2)
J
W
D
NS
PW
D
PW
20
PINS
16
PINS
16
PINS
16
PINS
16
PINS
16
PINS
16
PINS
16
PINS
TA ≤ 25°C
1375
1375
1000
950
—
774
950
774
725
425
2140
TA ≤ 70°C
880
880
640
608
—
496
608
496
464
272
1370
TA ≤ 85°C
715
715
520
494
—
402
494
402
377
221
1110
TA ≤ 125°C
275
275
200
—
—-
—
—
—
—
—
—
THERMAL METRIC(1)
Power
Rating
SN65LVDS31
FK
UNIT
8 PINS 8 PINS 8 PINS
mW
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The PowerPAD™ must be soldered to a thermal land on the printed-circuit board. See the application note PowerPAD Thermally
Enhanced Package (SLMA002).
8
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7.5 Electrical Characteristics: SN55LVDS31
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
340
454
mV
50
mV
VOD
Differential output voltage
magnitude
RL = 100 Ω, See Figure 8-2
247
ΔVOD
Change in differential output
voltage magnitude between logic
states
RL = 100 Ω, See Figure 8-2
–50
VOC(SS)
Steady-state common-mode
output voltage
See Figure 8-3
1.125
ΔVOC(SS)
Change in steady-state commonmode output voltage between
See Figure 8-3
logic states
–50
VOC(PP)
Peak-to-peak common-mode
output voltage
See Figure 8-3
ICC
Supply current
VI = 0.8 or 2 V, RL = 100 Ω, Enabled
IIH
High-level input current
VIH = 2
IIL
Low-level input current
1.2
VI = 0.8 or 2 V, Enabled, No load
VI = 0 or VCC, Disabled
mV
50
150
mV
9
20
25
35
1
4
20
μA
μA
0.1
10
–4
–24
IOZ
High-impedance output current
VO = 0 or 2.4 V
IO(OFF)
Power-off output current
VCC = 0, VO = 2.4 V
Ci
Input capacitance
mA
0.25
VIL = 0.8 V
Short-circuit output current
V
50
VO(Y) or VO(Z) = 0
IOS
(1)
1.375
VOD = 0
±12
3
mA
±1
μA
±4
μA
pF
All typical values are at TA = 25°C and with VCC = 3.3 V.
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7.6 Electrical Characteristics: SN65LVDSxxxx
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS31
SN65LVDS3487
SN65LVDS9638
MIN
TYP(1)
MAX
340
454
mV
50
mV
VOD
Differential output voltage magnitude
RL = 100 Ω, See Figure 8-2
247
ΔVOD
Change in differential output voltage
magnitude between logic states
RL = 100 Ω, See Figure 8-2
–50
VOC(SS)
Steady-state common-mode output
voltage
See Figure 8-3
1.125
ΔVOC(SS)
Change in steady-state common-mode
output voltage between logic states
See Figure 8-3
–50
VOC(PP)
Peak-to-peak common-mode output
voltage
See Figure 8-3
SN65LVDS31
SN65LVDS3487
ICC
Supply current
1.2
50
VI = 0.8 V or 2 V, Enabled, No load
VI = 0.8 or 2 V, RL = 100 Ω, Enabled
VI = 0 or VCC, Disabled
SN65LVDS9638
VI = 0.8 V or 2 V
UNIT
No load
RL = 100 Ω
1.375
50
mV
150
mV
9
20
25
35
1
4.7
8
9
13
4
20
μA
μA
High-level input current
VIH = 2
IIL
Low-level input current
VIL = 0.8 V
0.1
10
VO(Y) or VO(Z) = 0
–4
–24
Short-circuit output current
IOZ
High-impedance output current
VO = 0 or 2.4 V
IO(OFF)
Power-off output current
VCC = 0, VO = 2.4 V
Ci
Input capacitance
(1)
mA
0.25
IIH
IOS
V
VOD = 0
±12
mA
mA
±1
μA
±1
μA
3
pF
All typical values are at TA = 25°C and with VCC = 3.3 V.
7.7 Switching Characteristics: SN55LVDS31
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
0.5
1.4
4
ns
tPHL
Propagation delay time, high-to-low-level output
1
1.7
4.5
ns
tr
Differential output signal rise time (20% to 80%)
tf
Differential output signal fall time (80% to 20%)
tsk(p)
Pulse skew (|tPHL – tPLH|)
0.3
0.6
ns
tsk(o)
Channel-to-channel output skew(2)
0.3
0.6
ns
tPZH
Propagation delay time, high-impedance-to-highlevel output
5.4
15
ns
tPZL
Propagation delay time, high-impedance-to-low-level
output
2.5
15
ns
8.1
17
ns
7.3
15
ns
tPHZ
Propagation delay time, high-level-to-highimpedance output
tPLZ
Propagation delay time, low-level-to-high-impedance
output
RL = 100 Ω, CL = 10 pF
See Figure 8-2
(1)
All typical values are at TA = 25°C and with VCC = 3.3 V.
tsk(o) is the maximum delay time difference between drivers on the same device.
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0.5
1
ns
0.5
1
ns
See Figure 8-4
(2)
10
0.4
0.4
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7.8 Switching Characteristics: SN65LVDSxxxx
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS31
SN65LVDS3487
SN65LVDS9638
MIN
TYP(1)
UNIT
MAX
tPLH
Propagation delay time, low-to-high-level output
0.5
1.4
2
ns
tPHL
Propagation delay time, high-to-low-level output
1
1.7
2.5
ns
tr
Differential output signal rise time (20% to 80%)
tf
Differential output signal fall time (80% to 20%)
tsk(p)
Pulse skew (|tPHL – tPLH|)
tsk(o)
Channel-to-channel output skew(2)
tsk(pp)
Part-to-part skew(3)
tPZH
Propagation delay time, high-impedance-to-highlevel output
tPZL
Propagation delay time, high-impedance-to-low-level
output
tPHZ
Propagation delay time, high-level-to-highimpedance output
tPLZ
Propagation delay time, low-level-to-high-impedance
output
RL = 100 Ω, CL = 10 pF,
See Figure 8-2
0.4
0.5
0.6
ns
0.4
0.5
0.6
ns
0.3
0.6
ns
0
0.3
ns
800
ps
5.4
15
ns
2.5
15
ns
8.1
15
ns
7.3
15
ns
See Figure 8-4
(1)
All typical values are at TA = 25°C and with VCC = 3.3 V.
(2)
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
(3)
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
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7.9 Typical Characteristics
7.9.1
t PLH − Low-to-High Propagation Delay Time − ns
1.9
Four Drivers Loaded Per Figure 8-3 and Switching
Simultaneously
1.8
1.7
1.6
VCC = 3.3 V
1.5
VCC = 3 V
1.4
VCC = 3.6 V
1.3
1.2
1.1
1
−40
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
100
Figure 7-2. Low-to-High Propagation Delay Time vs
Free-Air Temperature
Figure 7-1. SN55LVDS31, SN65LVDS31 Supply
Current vs Frequency
t PHL − High-to-Low Propagation Delay Time − ns
1.9
1.8
VCC = 3 V
1.7
1.6
VCC = 3.3 V
1.5
VCC = 3.6 V
1.4
1.3
1.2
1.1
1
−40
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
100
Figure 7-3. High-to-Low Propagation Delay Time vs Free-Air Temperature
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8 Parameter Measurement Information
8.1
IOY
Y
II
A
Z
VOD
IOZ
VOY
VI
VOC
VOZ
(VOY + VOZ)/2
Figure 8-1. Voltage and Current Definitions
2V
1.4 V
0.8 V
Input
tPLH
Y
Input
(see Note A)
VOD
Z
tPHL
100 Ω
± 1%
100%
80%
VOD
CL = 10 pF
(2 Places)
(see Note B)
0
20%
0%
tf
tr
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 8-2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
Y
Input
(see Note A)
49.9 Ω ± 1% (2 Places)
3V
A
A
0
VOC(PP)
Z
(see Note C)
VOC(SS)
VOC
CL = 10 pF
(2 Places)
(see Note B)
VOC
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
C. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
Figure 8-3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
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49.9 Ω ± 1% (2 Places)
Y
0.8 V or 2 V
Inputs
(see Note A)
Z
G
G
1,2EN or 3,4EN
1.2 V
CL = 10 pF
(2 Places)
(see Note B)
G, 1,2EN,
OR 3,4EN
2V
1.4 V
0.8 V
G
2V
1.4 V
0.8 V
tPZH
VOY
VOZ
tPHZ
VOY
or
VOZ
tPZL
100%, ≅1.4 V
50%
0%, 1.2 V
A at 2 V, G at VCC and Input to G
or
G at GND and Input to G for ’LVDS31 Only
100%, 1.2 V
50%
0%, ≅1 V
A at 0.8 V, G at VCC and Input to G
or
G at GND and Input to G for ’LVDS31 Only
tPLZ
VOZ
or
VOY
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 8-4. Enable or Disable Time Circuit and Definitions
14
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9 Detailed Description
9.1 Overview
The SNx5LVDSxx devices are dual- and quad-channel LVDS line drivers. They operate from a single supply that
is nominally 3.3 V, but can be as low as 3 V and as high as 3.6 V. The input signal to the SN65LVDS1 device
is an LVTTL signal. The output of the device is a differential signal complying with the LVDS standard (TIA/
EIA-644A). The differential output signal operates with a signal level of 340 mV, nominally, at a common-mode
voltage of 1.2 V. This low differential output voltage results in a low emitted radiated energy, which is dependent
on the signal slew rate. The differential nature of the output provides immunity to common-mode coupled
signals.
The SNx5LVDSxx devices are intended to drive a 100-Ω transmission line. This transmission line may be a
printed-circuit board (PCB) or cabled interconnect. With transmission lines, the optimum signal quality and power
delivery is reached when the transmission line is terminated with a load equal to the characteristic impedance of
the interconnect. Likewise, the driven 100-Ω transmission line should be terminated with a matched resistance.
9.2 Functional Block Diagram
’LVDS31 logic diagram (positive logic)
G
G
1A
2A
3A
4A
SN65LVDS3487 logic diagram
(positive logic)
4
12
1
7
2
3
6
5
9
10
11
15
14
13
1A
1Y
1Z
1,2EN
2Y
2A
1
3
3A
3Z
3,4EN
4Y
4A
1Y
1Z
4
7
6
5
2Z
3Y
2
9
10
11
2Y
2Z
3Y
3Z
12
15
14
13
4Z
4Y
4Z
SN65LVDS9638 logic diagram
(positive logic)
1A
2A
2
8
7
3
6
5
1Y
1Z
2Y
2Z
9.3 Feature Description
9.3.1 Driver Disabled Output
When the SNx5LVDSxx driver is disabled, or when power is removed from the device, the driver outputs are
high-impedance.
9.3.2 NC Pins
NC (not connected) pins are pins where the die is not physically connected to the lead frame or package. For
optimum thermal performance, a good rule of thumb is to ground the NC pins at the board level.
9.3.3 Unused Enable Pins
Unused enable pins should be tied to VCC or GND as appropriate.
9.3.4 Driver Equivalent Schematics
The driver input is represented by a CMOS inverter stage with a 7-V Zener diode. The input stage is highimpedance, and includes an internal pulldown to ground. If the driver input is left open, the driver input provides
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a low-level signal to the rest of the driver circuitry, resulting in a low-level signal at the driver output pins. The
Zener diode provides ESD protection. The driver output stage is a differential pair, one half of which is shown
in Figure 9-1. Like the input stage, the driver output includes Zener diodes for ESD protection. The schematic
shows an output stage that includes a set of current sources (nominally 3.5 mA) that are connected to the
output load circuit based upon the input stage signal. To the first order, the SNx5LVDSxx output stage acts a
constant-current source.
EQUIVALENT OF EACH A INPUT
EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS
VCC
VCC
TYPICAL OF ALL OUTPUTS
VCC
50 Ω
50 Ω
Input
Input
10 kΩ
7V
7V
300 kΩ
5Ω
Y or Z
Output
7V
Figure 9-1. Equivalent Input and Output Schematic Diagrams
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9.4 Device Functional Modes
Table 9-1. SN55LVDS31, SN65LVDS31(1)
(1)
ENABLES
OUTPUTS
INPUT
A
G
G
Y
Z
H
H
X
H
L
L
H
X
L
H
H
X
L
H
L
H
L
X
L
L
X
L
H
Z
Z
Open
H
X
L
H
Open
X
L
L
H
H = high level, L = low level, X = irrelevant, Z = high-impedance
(off)
Table 9-2. SN65LVDS3487(1)
(1)
INPUT A
ENABLE EN
H
H
OUTPUTS
Y
Z
H
L
L
H
L
H
X
L
Z
Z
Open
H
L
H
H = high level, L = low level, X = irrelevant, Z = high-impedance
(off)
Table 9-3. SN65LVDS9638(1)
INPUT A
(1)
OUTPUTS
Y
Z
H
H
L
L
L
H
Open
L
H
H = high level, L = low level
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The SNx5LVDSxx devices are dual- and quad-channel LVDS drivers. These devices are generally used as
building blocks for high-speed, point-to-point, data transmission where ground differences are less than 1 V.
LVDS drivers and receivers provide high-speed signaling rates that are often implemented with ECL class
devices without the ECL power and dual-supply requirements. A common question with any class of driver
is how far and how fast can the devices operate. While individual drivers and receivers have specifications
that define their inherent switching rate, a communication link will quite often be limited by the impairments
introduced by the interconnecting media. Figure 10-1 shows the typical relationship between signaling rate and
distance achievable depends on the quality of the eye pattern at the receiver that is either desired or needed.
Figure 10-1 shows the curves representing 5% and 30% eye closure due to inter-symbol interference (ISI).
Transmission Distance (m)
100
30% Jitter
(see Note A)
10
5% Jitter
(see Note A)
1
0.1
10
100
1000
Signaling Rate (Mbps)
24 A WG UTP 96 Ω (PVC Dielectric)
A.
This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 10-1. Typical Transmission Distance vs Signaling Rate
10.2 Typical Application
10.2.1 Point-to-Point Communications
The most basic application for LVDS buffers, as found in this data sheet, is for point-to-point communications of
digital data, as shown in Figure 10-2.
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100 Ω Differential T-Line
OUT+
IN+
100 Ω
Driver
Receiver
IN-
OUT-
Figure 10-2. Point-to-Point Topology
A point-to-point communications channel has a single transmitter (driver) and a single receiver. This
communications topology is often referred to as simplex. In Figure 10-2 the driver receives a single-ended input
signal and the receiver outputs a single-ended recovered signal. The LVDS driver converts the single-ended
input to a differential signal for transmission over a balanced interconnecting media of 100-Ω characteristic
impedance. The conversion from a single-ended signal to an LVDS signal retains the digital data payload while
translating to a signal whose features are more appropriate for communication over extended distances or in a
noisy environment.
10.2.1.1 Design Requirements
DESIGN PARAMETERS
EXAMPLE VALUE
Driver Supply Voltage (VCCD)
3.0 to 3.6 V
Driver Input Voltage
0.8 to 3.3 V
Driver Signaling Rate
DC to 400 Mbps
Interconnect Characteristic Impedance
100 Ω
Termination Resistance
100 Ω
Number of Receiver Nodes
1
Receiver Supply Voltage (VCCR)
3.0 to 3.6 V
Receiver Input Voltage
0 to 2.4 V
Receiver Signaling Rate
DC to 400 Mbps
Ground shift between driver and receiver
±1 V
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Driver Supply Voltage
The SNx5LVDSxx driver is operated from a single supply. The device can support operation with a supply as low
as 3 V and as high as 3.6 V. The differential output voltage is nominally 340 mV over the complete output range.
The minimum output voltage stays within the specified LVDS limits (247 mV to 454 mV) for a 3.3-V supply.
10.2.1.2.2 Driver Bypass Capacitance
Bypass capacitors play a key role in power distribution circuitry. Specifically, they create low-impedance paths
between power and ground. At low frequencies, a good digital power supply offers very-low-impedance paths
between its terminals. However, as higher frequency currents propagate through power traces, the source is
quite often incapable of maintaining a low-impedance path to ground. Bypass capacitors are used to address
this shortcoming. Usually, large bypass capacitors (10 to 1000 μF) at the board-level do a good job up into the
kHz range. Due to their size and length of their leads, they tend to have large inductance values at the switching
frequencies of modern digital circuitry. To solve this problem, one should resort to the use of smaller capacitors
(nF to μF range) installed locally next to the integrated circuit.
Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass
capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes,
a typical capacitor with leads has a lead inductance around 5 nH.
The value of the bypass capacitors used locally with LVDS chips can be determined by the following formula
according to Johnson1, equations 8.18 to 8.21. A conservative rise time of 200 ps and a worst-case change in
supply current of 1 A covers the whole range of LVDS devices offered by Texas Instruments. In this example,
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the maximum power supply noise tolerated is 200 mV; however, this figure varies depending on the noise budget
available in your design. 1
æ DIMaximum Step Change Supply Current ö
Cchip = ç
÷ ´ TRise Time
è DVMaximum Power Supply Noise ø
(1)
æ 1A ö
CLVDS = ç
÷ ´ 200 ps = 0.001 mF
è 0.2V ø
(2)
The following example lowers lead inductance and covers intermediate frequencies between the board-level
capacitor (>10 µF) and the value of capacitance found above (0.001 µF). You should place the smallest value of
capacitance as close as possible to the chip.
3.3 V
0.1 F
0.001 F
Figure 10-3. Recommended LVDS Bypass Capacitor Layout
10.2.1.2.3 Driver Output Voltage
The SNx5LVDSxx driver output is a 1.2-V common-mode voltage, with a nominal differential output signal of 340
mV. This 340 mV is the absolute value of the differential swing (VOD = |V+ – V–|). The peak-to-peak differential
voltage is twice this value, or 680 mV.
10.2.1.2.4 Interconnecting Media
The physical communication channel between the driver and the receiver may be any balanced paired metal
conductors meeting the requirements of the LVDS standard, the key points which will be included here. This
media may be a twisted pair, twinax, flat ribbon cable, or PCB traces. The nominal characteristic impedance of
the interconnect should be between 100 Ω and 120 Ω with a variation of no more than 10% (90 Ω to 132 Ω).
10.2.1.2.5 PCB Transmission Lines
As per SNLA187, Figure 10-4 depicts several transmission line structures commonly used in printed-circuit
boards (PCBs). Each structure consists of a signal line and a return path with uniform cross-section along its
length. A microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return
path in a ground or power plane. A stripline is a signal trace in the inner layer, with a dielectric layer in between a
ground plane above and below the signal trace. The dimensions of the structure along with the dielectric material
properties determine the characteristic impedance of the transmission line (also called controlled-impedance
transmission line).
When two signal lines are placed close by, they form a pair of coupled transmission lines. Figure 10-4
shows examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines. When excited
by differential signals, the coupled transmission line is referred to as a differential pair. The characteristic
impedance of each line is called odd-mode impedance. The sum of the odd-mode impedances of each line
is the differential impedance of the differential pair. In addition to the trace dimensions and dielectric material
properties, the spacing between the two traces determines the mutual coupling and impacts the differential
impedance. When the two lines are immediately adjacent; for example, S is less than 2W, the differential pair
is called a tightly-coupled differential pair. To maintain constant differential impedance along the length, it is
important to keep the trace width and spacing uniform along the length, as well as maintain good symmetry
between the two lines.
1
20
Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
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Single-Ended Stripline
Single-Ended Microstrip
W
W
T
H
T
H
H
5.98H
87
ln
0
.
8W + T
+
1
.
41
r
[
Z0 =
Z0 =
]
60
r
Edge-Coupled
ln
[ 1(.09.(82WH ++TT)) ]
Edge-Coupled
S
S
H
H
Differential Stripline
Differential Microstrip
[
−0.96×
Z diff = 2 ×Z0 × 1− 0.48× e
S
H
[
]
Co-Planar Coupled Microstrips
W
G
W
S
−2.9×
Z diff = 2×Z0 × 1− 0.347e
S
H
]
Broad-Side Coupled Striplines
W
G
S
H
H
Figure 10-4. Controlled-Impedance Transmission Lines
10.2.1.2.6 Termination Resistor
As shown earlier, an LVDS communication channel employs a current source driving a transmission line which is
terminated with a resistive load. This load serves to convert the transmitted current into a voltage at the receiver
input. To ensure incident wave switching (which is necessary to operate the channel at the highest signaling
rate), the termination resistance should be matched to the characteristic impedance of the transmission line.
The designer should ensure that the termination resistance is within 10% of the nominal media characteristic
impedance. If the transmission line is targeted for 100-Ω impedance, the termination resistance should be
between 90 and 110 Ω.
The line termination resistance should be located as close as possible to the receiver, thereby minimizing the
stub length from the resistor to the receiver. The limiting case would be to incorporate the termination resistor
into the receiver, which is exactly what is offered with a device like the SN65LVDT386. The SN65LVDT386
provides all the functionality and performance of the SN65LVDT386 receiver, with the added feature of an
integrated termination load.
While we talk in this section about point-to-point communications, a word of caution is useful when a multidrop
topology is used. In such topologies, line termination resistors are to be located only at the end(s) of the
transmission line. In such an environment, SN65LVDT386 receivers could be used for loads branching off the
main bus with an SN65LVDT386 used only at the bus end.
10.2.1.2.7 Driver NC Pins
NC (not connected) pins are pins where the die is not physically connected to the lead frame and package. For
optimum thermal performance, a good rule of thumb is to ground the NC pins at the board level.
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10.2.1.3 Application Curve
Figure 10-5. Typical Driver Output Eye Pattern in Point-to-Point System
10.2.2 Multidrop Communications
A second common application of LVDS buffers is a multidrop topology. In a multidrop configuration, a single
driver and a shared bus are present along with two or more receivers (with a maximum permissible number of 32
receivers). Figure 10-6 shows an example of a multidrop system.
Minimize
Stub
Lengths
Minimize
Stub
Lengths
+
±
+
Receiver
±
+
Receiver
|100
Driver
Receiver
±
Figure 10-6. Multidrop Topology
10.2.2.1 Design Requirements
DESIGN PARAMETERS
EXAMPLE VALUE
Driver Supply Voltage (VCCD)
3.0 to 3.6 V
Driver Input Voltage
0.8 to 3.3 V
Driver Signaling Rate
DC to 400 Mbps
Interconnect Characteristic Impedance
100 Ω
Termination Resistance
100 Ω
Number of Receiver Nodes
2 to 32
Receiver Supply Voltage (VCCR)
3.0 to 3.6 V
Receiver Input Voltage
0 to 2.4 V
Receiver Signaling Rate
DC to 400 Mbps
Ground shift between driver and receiver
±1 V
10.2.2.2 Detailed Design Procedure
10.2.2.2.1 Interconnecting Media
The interconnect in a multidrop system differs considerably from a point-to-point system. While point-to-point
interconnects are straightforward and well understood, the bus type architecture encountered with multidrop
systems requires more careful attention. We will use Figure 10-6 above to explore these details.
22
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The most basic multidrop system would include a single driver, located at a bus origin, with multiple receiver
nodes branching off the main line, and a final receiver at the end of the transmission line, co-located with a bus
termination resistor. While this would be the most basic multidrop system, it has several considerations not yet
explored.
The location of the transmitter at one bus end allows the design concerns to be simplified, but this comes at the
cost of flexibility. With a transmitter located at the origin, a single bus termination at the far-end is required. The
far-end termination absorbs the incident traveling wave. The flexibility lost with this arrangement is thus: if the
single transmitter needed to be relocated on the bus, at any location other than the origin, we would be faced
with a bus with one open-circuited end, and one properly terminated end. Locating the transmitter say in the
middle of the bus may be desired to reduce (by ½) the maximum flight time from the transmitter to receiver.
Another new feature in Figure 10-6 is clear in that every node branching off the main line results in stubs. The
stubs should be minimized in any case, but have the unintended effect of locally changing the loaded impedance
of the bus.
To a good approximation, the characteristic transmission line impedance seen into any cut point in the unloaded
multipoint or multidrop bus is defined by √ L/C, where L is the inductance per unit length and C is the
capacitance per unit length. As capacitance is added to the bus in the form of devices and interconnections,
the bus characteristic impedance is lowered. This may result in signal reflections from the impedance mismatch
between the unloaded and loaded segments of the bus.
If the number of loads is constant and can be distributed evenly along the line, reflections can be reduced
by changing the bus termination resistors to match the loaded characteristic impedance. Normally, the number
of loads are not constant or distributed evenly and the reflections resulting from any mismatching should be
accounted for in the noise budget.
10.2.2.3 Application Curve
Figure 10-7. Typical Driver Output Eye Pattern in Multi-Drop System
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11 Power Supply Recommendations
11.1
The LVDS drivers in this data sheet are designed to operate from a single power supply, with supply voltages in
the range of 3.0 V to 3.6 V. In a typical application, a driver and a receiver may be on separate boards or even
separate equipment. In these cases, separate supplies would be used at each location. The expected ground
potential difference between the driver power supply and the receiver power supply would be less than |±1 V|.
Board-level and local device-level bypass capacitance should be used and are covered in Section 10.2.1.2.2.
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12 Layout
12.1 Layout Guidelines
12.1.1 Microstrip vs. Stripline Topologies
As per SLLD009, printed-circuit boards usually offer designers two transmission line options: Microstrip and
stripline. Microstrips are traces on the outer layer of a PCB, as shown in Figure 12-1.
Figure 12-1. Microstrip Topology
On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and
susceptibility problems because the reference planes effectively shield the embedded traces. However, from the
standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends
routing LVDS signals on microstrip transmission lines, if possible. The PCB traces allow designers to specify the
necessary tolerances for ZO based on the overall noise budget and reflection allowances. Footnotes 12, 23, and
34 provide formulas for ZO and tPD for differential and single-ended traces. 2 3 4
Figure 12-2. Stripline Topology
2
3
4
Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
Mark I. Montrose. 1996. Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press. ISBN number 0780311310.
Clyde F. Coombs, Jr. Ed, Printed Circuits Handbook, McGraw Hill, ISBN number 0070127549.
Copyright © 2021 Texas Instruments Incorporated
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SLLS261N – JULY 1997 – REVISED APRIL 2021
12.1.2 Dielectric Type and Board Construction
The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually
provides adequate performance for use with LVDS signals. If rise or fall times of TTL/CMOS signals are less
than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350
or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters
pertaining to the board construction that can affect performance. The following set of guidelines were developed
experimentally through several designs involving LVDS devices:
• Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz
• All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
• Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
• Solder mask over bare copper with solder hot-air leveling
12.1.3 Recommended Stack Layout
Following the choice of dielectrics and design specifications, you should decide how many levels to use in the
stack. To reduce the TTL/CMOS to LVDS crosstalk, it is a good practice to have at least two separate signal
planes as shown in Figure 12-3.
Layer 1: Routed Plane (LVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Routed Plane (TTL/CMOS Signals)
Figure 12-3. Four-Layer PCB Board
Note
The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the power and
ground planes tightly coupled, the increased capacitance acts as a bypass for transients.
One of the most common stack configurations is the six-layer board, as shown in Figure 12-4.
Layer 1: Routed Plane (LVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Ground Plane
Layer 5: Ground Plane
Layer 6: Routed Plane (TTL Signals)
Figure 12-4. Six-Layer PCB Board
In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one
ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer
board is preferable, because it offers the layout designer more flexibility in varying the distance between signal
layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.
12.1.4 Separation Between Traces
The separation between traces depends on several factors; however, the amount of coupling that can be
tolerated usually dictates the actual separation. Low-noise coupling requires close coupling between the
differential pair of an LVDS link to benefit from the electromagnetic field cancellation. The traces should be
100-Ω differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs
should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew
and signal reflection.
In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance
between two traces should be greater than two times the width of a single trace, or three times its width
26
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SLLS261N – JULY 1997 – REVISED APRIL 2021
measured from trace center to trace center. This increased separation effectively reduces the potential for
crosstalk. The same rule should be applied to the separation between adjacent LVDS differential pairs, whether
the traces are edge-coupled or broad-side-coupled.
W
Differential Traces
LVDS
Pair
S = Minimum Spacing as Defined by PCB Vender
W
≥2 W
Single-Ended Traces TTL/CMOS
Trace
W
Figure 12-5. 3-W Rule for Single-Ended and Differential Traces (Top View)
You should exercise caution when using autorouters, because they do not always account for all factors affecting
crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the
signal path. Using successive 45° turns tends to minimize reflections.
12.1.5 Crosstalk and Ground Bounce Minimization
To reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible
to its originating trace. A ground plane usually achieves this. Because the returning currents always choose
the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing
crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as
possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic
field strength. Discontinuities in the ground plane increase the return path inductance and should be avoided.
12.2 Layout Example
At least two or three times the width of an individual trace should separate single-ended traces and differential
pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength
of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long
parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as
shown in Figure 12-6.
Layer 1
Layer 6
Figure 12-6. Staggered Trace Layout
This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between
traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal
path, TI recommends having an adjacent ground via for every signal via, as shown in Figure 12-7. Note that vias
create additional capacitance. For example, a typical via has a lumped capacitance effect of 0.5 pF to 1 pF in
FR4.
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SLLS261N – JULY 1997 – REVISED APRIL 2021
Signal via
Signal Trace
Uninterrupted Ground Plane
Signal Trace
Uninterrupted Ground Plane
Ground via
Figure 12-7. Ground Via Location (Side View)
Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground
bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create
discontinuities that increase returning current loop areas.
To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and
so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the
same area, as opposed to mixing them together, helps reduce susceptibility issues.
28
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www.ti.com
SLLS261N – JULY 1997 – REVISED APRIL 2021
13 Device and Documentation Support
13.1 Device Support
13.1.1 Other LVDS Products
For other products and application notes in the LVDS and LVDM product families visit our Web site at http://
www.ti.com/sc/datatran.
13.2 Documentation Support
13.2.1 Related Information
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
•
•
•
•
•
•
Low-Voltage Differential Signaling Design Notes (SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
13.2.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.2.3 Related Links
Table 13-1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 13-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN55LVDS31
Click here
Click here
Click here
Click here
Click here
SN65LVDS31
Click here
Click here
Click here
Click here
Click here
SN65LVDS3487
Click here
Click here
Click here
Click here
Click here
SN65LVDS9638
Click here
Click here
Click here
Click here
Click here
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
Rogers™ is a trademark of Rogers Corporation.
All trademarks are the property of their respective owners.
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SLLS261N – JULY 1997 – REVISED APRIL 2021
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9762101Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629762101Q2A
SNJ55
LVDS31FK
5962-9762101QEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9762101QE
A
SNJ55LVDS31J
5962-9762101QFA
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9762101QF
A
SNJ55LVDS31W
SN55LVDS31W
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN55LVDS31W
Samples
SN65LVDS31D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS31
Samples
SN65LVDS31DG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS31
Samples
SN65LVDS31DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS31
Samples
SN65LVDS31DRG4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS31
Samples
SN65LVDS31NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS31
Samples
SN65LVDS31PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS31
Samples
SN65LVDS31PWG4
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS31
Samples
SN65LVDS31PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS31
Samples
SN65LVDS31PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS31
Samples
SN65LVDS3487D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS3487
Samples
SN65LVDS3487DG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS3487
Samples
SN65LVDS3487DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS3487
Samples
SN65LVDS9638D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
DK638
Samples
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN65LVDS9638DGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AXG
Samples
SN65LVDS9638DGKG4
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AXG
Samples
SN65LVDS9638DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AXG
Samples
SN65LVDS9638DGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
L38
Samples
SN65LVDS9638DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
L38
Samples
SN65LVDS9638DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
DK638
Samples
SNJ55LVDS31FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629762101Q2A
SNJ55
LVDS31FK
SNJ55LVDS31J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9762101QE
A
SNJ55LVDS31J
SNJ55LVDS31W
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9762101QF
A
SNJ55LVDS31W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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