SN65LVDT122DR

SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 1.5-Gbps 2 × 2 LVDS CROSSPOINT SWITCH FEATURES • DESCRIPTION Designed for Signaling Rates Up To 1.5 Gbps Total Jitter < 65 ps Pin-Compatible With SN65LVDS22 and SN65LVDM22 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range Inputs Electrically Compatible With CML, LVPECL and LVDS Signal Levels Propagation Delay Times, 900 ps Maximum LVDT Integrates 110-Ω Terminating Resistor Offered in SOIC and TSSOP (1) • • • • • • • APPLICATIONS • • • • • 10-G (OC-192) Optical Modules 622-MHz Central Office Clock Distribution Wireless Basestations Low Jitter Clock Repeater/Multiplexer Protection Switching for Serial Backplanes (1) The signlaing rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). The SN65LVDS122 and SN65LVDT122 are crosspoint switches that use low voltage differential signaling (LVDS) to achieve signaling rates as high as 1.5 Gbps. They are pin-compatible speed upgrades to the SN65LVDS22 and SN65LVDM22. The internal signal paths maintain differential signaling for high speeds and low signal skews. These devices have a 0-V to 4-V common-mode input range that accepts LVDS, LVPECL, or CML inputs. Two logic pins (S0 and S1) set the internal configuration between the differential inputs and outputs. This allows the flexibility to perform the following configurations: 2 x 2 crosspoint switch, 2:1 input multiplexer, 1:2 splitter or dual repeater/translator within a single device. Additionally, SN65LVDT122 incorporates a 110-Ω termination resistor for those applications where board space is a premium. Although these devices are designed for 1.5 Gbps, some applications at a 2-Gbps data rate can be supported depending on loading and signal quality. The intended application of this device is ideal for loopback switching for diagnostic routines, fanout buffering of clock/data distribution provide protection in fault-tolerant systems, clock multiplexing in optical modules, and for overall signal boosting over extended distances. The SN65LVDS122 and SN65LVDT122 characterized for operation from –40°C to 85°C. EYE PATTERNS OF OUTPUTS OPERATING SIMULTANEOUSLY FUNCTIONAL DIAGRAM 1DE 1A 1Y 1Z 110 Ω are 1.5 Gbps 223 − 1 PRBS OUTPUT 1 1B VCC = 3.3 V S0 MUX S1 2A 110 Ω 2B VID = 200 mV, VIC = 1.2 V Vertical Scale=200 mV/div 2Y 2Z OUTPUT 2 2DE Integrated Termination on SN65LVDT122 Only Horizontal Scale= 200 ps/div Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2004, Texas Instruments Incorporated SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TERMINATION RESISTOR PART NUMBER (1) SYMBOLIZATION SOIC No SN65LVDS122D LVDS122 SOIC Yes SN65LVDT122D LVDT122 TSSOP No SN65LVDS122PW LVDS122 TSSOP Yes SN65LVDT122PW LVDT122 PACKAGE (1) Add the suffix R for taped and reeled carrier ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) SN65LVDS122, SN65LVDT122 VCC Supply voltage range (2) –0.5 V to 4 V (A, B) Voltage range –0.7 V to 4.3 V |VA-VB| (LVDT only) 1V (DE, S0, S1) –0.5 V to 4 V (Y, Z) –0.5 V to 4 V Human Body Model (3) ESD Charged-Device Model (4) A, B, Y, Z, and GND ±4 kV All pins ±2 kV ±1500 V All pins Continuous power dissipation Tstg See Dissipation Rating Table Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) (4) 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A.7. Tested in accordance with JEDEC Standard 22, Test Method C101. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3 3.3 UNIT VCC Supply voltage 3.6 V VIH High-level input voltage S0, S1, 1DE, 2DE 2 4 V VIL Low-level input voltage S0, S1, 1DE, 2DE 0 0.8 V LVDS 0.1 1 LVDT 0.1 0.8 |VID| Magnitude of differential input voltage Input voltage (any combination of common-mode or input signals) TA Operating free-air temperature 0 4 V –40 85 °C PACKAGE DISSIPATION RATINGS TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING PW 712 mW 6.2 mW/°C 340 mW D 1002 mW 8.7 mW/°C 480 mW PACKAGE (1) 2 V This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 INPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIT+ Positive-going differential input voltage threshold VIT- Negative-going differential input voltage threshold TEST CONDITIONS MIN TYP (1) MAX See Figure 1 and Table 1 See Figure 1 and Table 1 100 –100 (2) VID(HYS) Differential input voltage hysteresis (VIT+– VIT-) IIH High-level input current IIL Low-level input current ICC Supply current DE S0, S1 DE S0, S1 Input current (A or B inputs 'LVDS) II Input current (A or B inputs 'LVDT) Input current (A or B inputs 'LVDS) II(OFF) Input current (A or B inputs 'LVDT) IIO (1) (2) 0 0 20 0 20 RL = 100 Ω 80 100 Disabled 35 45 VI = 0 V or 2.4 V, Other input at 1.2 V –20 20 0 33 –40 40 0 66 VCC = 1.5 V, VI = 0 V or 2.4 V, Other input at 1.2 V –20 20 VCC = 1.5 V, VI = 2.4 V or 4 V, Other input at 1.2 V 0 33 VCC = 1.5 V, VI = 0 V or 2.4 V, Other input open –40 40 VCC = 1.5 V, VI = 2.4 V or 4 V, Other input open 0 66 6 VI = 4 V, Other input at 1.2 V VI = 0 V or 2.4 V, Other input open VI = 4 V, Other input open µA mA µA µA µA VIA = VIB, 0 ≤ VIA ≤ 4 V –6 Termination resistance ('LVDT) VID = 300 mV and 500 mV, VIC = 0 V to 2.4 V 90 110 132 Termination resistance ('LVDT with power-off) VID = 300 mV and 500 mV, VCC = 1.5 V, VIC = 0 V to 2.4 V 90 110 132 Differential input capacitance ('LVDT with power-off) µA µA Input offset current (| IIA– IIB |) 'LVDS RT CI mV –10 –10 VIL = 0.8 V mV mV 25 VIH = 2 UNIT µA Ω VI = 0.4 sin (4E6πt) + 0.5 V 3 Powered down (VCC = 1.5 V) 3 pF All typical values are at 25°C and with a 3.3-V supply. The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet. OUTPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER |VOD| Differential output voltage magnitude ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage IOS TEST CONDITIONS MIN TYP (1) 247 See Figure 2 310 MAX UNIT 454 mV –50 50 1.125 1.375 See Figure 3 –50 50 mV 150 mV Short-circuit output current VO(Y) or VO(Z) = 0 V –24 24 mA IOS(D) Differential short-circuit output current VOD = 0 V –12 12 mA IOZ High-impedance output current VOD = 600 mV –1 1 VO = 0 V or VCC –1 1 Co Differential output capacitance (1) 50 VI = 0.4 sin (4E6πt) + 0.5 V 3 V µA pF All typical values are at 25°C and with a 3.3-V supply. 3 SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 TIMING CHARACTERISTICS PARAMETER tSET Input to select setup time tHOLD Input to select hold time tSWITCH Select to switch output TEST CONDITIONS MIN NOM MAX UNIT 0 ns 0.5 ns 1 2 2.6 ns SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tr Differential output signal rise time (20% - 80%) tf Differential output signal fall time (20% - 80%) tsk(p) Pulse skew (|tPHL - tPLH|) (2) skew (3) TEST CONDITIONS See Figure 4 MIN NOM (1) MAX UNIT 400 650 900 ps 400 650 900 ps 280 ps 280 ps 50 ps 10 tsk(pp) Part-to-part 100 ps tjit(per) Period jitter, rms (1 standard deviation) (4) 750 MHz clock input (5) 1 2.2 ps tjit(cc) Cycle-to-cycle jitter (peak) (4) 750 MHz clock input (6) 10 17 ps 33 65 ps 17 50 ps jitter (4) VID = 0.2 V Peak-to-peak tjit(det) Deterministic jitter, peak-to-peak (4) 1.5 Gbps 27–1 PRBS input (8) tPHZ Propagation delay time, high-level-to-high-impedance output See Figure 5 6 8 ns tPLZ Propagation delay time, low-level-to-high-impedance output See Figure 5 6 8 ns tPZH Propagation delay time, high-impedance-to-high-level output See Figure 5 4 6 ns tPZL Propagation delay time, high-impedance-to-low-level output See Figure 5 4 6 ns tsk(o) Output skew (9) 15 40 ps (4) (5) (6) (7) (8) (9) 4 PRBS input (7) tjit(pp) (1) (2) (3) 1.5 Gbps 223–1 All typical values are at 25°C and with a 3.3-V supply. tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Jitter is specified by design and characterization. Stimulus jitter has been subtracted. Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%), measured over 1000 samples. Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%). Input voltage = VID = 200 mV, 223–1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%), measured over 200 k samples. Input voltage = VID = 200 mV, 27–1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%). Output skew is the magnitude of the time delay difference between the outputs of a single device with all inputs tied together. SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 PIN ASSIGNMENT D OR PW PACKAGE (TOP VIEW) 1B 1A S0 1DE S1 2A 2B GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC VCC 1Y 1Z 2DE 2Z 2Y GND Circuit Function Table INPUTS (1) OUTPUTS (1) 1VID 2VID S1 S0 1DE 2DE 1VOD 2VOD X X X X L L Z Z > 100 mV X L L H L H Z < -100 mV X L L H L L Z < -100 mV X L L H H L L > 100 mV X L L H H H H > 100 mV X L L L H Z H < -100 mV X L L L H Z L > 100 mV X H L H L H Z < -100 mV X H L H L L Z < -100 mV < -100 mV H L H H L L < -100 mV > 100 mV H L H H L H > 100 mV < -100 mV H L H H H L > 100 mV > 100 mV H L H H H H X > 100 mV H L L H Z H X < -100 mV H L L H Z L X > 100 mV L H H L H Z X < -100 mV L H H L L Z X < -100 mV L H H H L L X > 100 mV L H H H H H X > 100 mV L H L H Z H X < -100 mV L H L H Z L X > 100 mV H H H L H Z X < -100 mV H H H L L Z < -100 mV < -100 mV H H H H L L < -100 mV > 100 mV H H H H H L > 100 mV < -100 mV H H H > 100 mV > 100 mV H H H H L H H H H > 100 mV X H H L H Z H < -100 mV X H H L H Z L LOGIC DIAGRAM 1DE 1A / 1B 1Y / 1Z 2A / 2B 2Y / 2Z 2DE 1DE 1A / 1B 1Y / 1Z 2A / 2B 2Y / 2Z 2DE 1DE 1A / 1B 1Y / 1Z 2A / 2B 2Y / 2Z 2DE 1DE 1A / 1B 1Y / 1Z 2A / 2B 2Y / 2Z 2DE (1) H = high level, L = low level, Z = high impedance, X = don't care 5 SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION IIA VID VIA (VIA+VIB)/2 A Y B Z VOD VOY VIC VIB IIB (VOY+VOZ)/2 VOZ Figure 1. Voltage and Current Definitions 3.74 kΩ Y VOD 100 Ω Z 3.74 kΩ + _ 0 V ≤ Vtest ≤ 2.4 V Figure 2. Differential Output Voltage (VOD) Test Circuit A Y B Z A ≈ 1.4 V B ≈1V 49.9 Ω ±1% VID VOC(PP) 49.9 Ω ±1% 1 pF VOC VOC(SS) VOC NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; RL = 100 Ω; CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.; the measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage A VIA VID Y 1 pF B VOD 100 Ω VIA 1.4 V VIB 1V VID 0.4 V 0V -0.4 V Z VIB tPHL tPLH 80% VOD 0V 20% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 4. Timing Test Circuit and Waveforms 6 SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION (continued) 49.9 Ω ±1% Y 1 V or 1.4 V 1.2 V DE A 1 pF B 49.9 Ω ±1% Z 3V 1.5 V 0V DE ≅ 1.4 V 1.25 V 1.2 V VOY or VOZ 1.2 V tPZH tPHZ 1.2 V 1.15 V ≅1V VOZ or VOY tPZL tPLZ NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 5. Enable and Disable Time Circuit and Definitions INPUT 1 A B INPUT 2 C D SEL 0/1 t(SET) OUTPUT1 A t(HOLD) B C D t(SWITCH) Figure 6. Example Switch, Setup, and Hold Times 7 SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION (continued) t(SET) and t(HOLD) times specify that data must be in a stable state before and after multiplex control switches. Table 1. Receiver Input Voltage Threshold Test APPLIED VOLTAGES (1) 8 RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE OUTPUT (1) VIA VIB VID VIC 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.2 V L 4.0 V 3.9 V 100 mV 3.95 V H 3.9 V 4. 0 V –100 mV 3.95 V L 0.1 V 0.0 V 100 mV 0.05 V H 0.0 V 0.1 V –100 mV 0.05 V L 1.7 V 0.7 V 1000 mV 1.2 V H 0.7 V 1.7 V –1000 mV 1.2 V L 4.0 V 3.0 V 1000 mV 3.5 V H 3.0 V 4.0 V –1000 mV 3.5 V L 1.0 V 0.0 V 1000 mV 0.5 V H 0.0 V 1.0 V –1000 mV 0.5 V L H = high level, L = low level H SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS INPUT LVDS122 VCC A VCC B 7V 7V VCC VCC 300 kΩ 400 Ω S0, S1 DE1, DE2 400 Ω 300 kΩ 7V 7V OUTPUT LVDS122 VCC VCC VCC Y 7V Z 7V 9 SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY DIFFERENTIAL PROPAGATION DELAY vs COMMON-MODE INPUT VOLTAGE 1000 300 250 200 150 VCC = 3.3 V TA = 25°C VIC = 1.2 V VID = 200 mV Input = Clock 100 50 800 VCC = 3.3 V TA = 25°C VID = 200 mV f = 150 MHz 900 800 tPHL 700 tPLH 600 700 tPHL 600 0 500 1000 1500 0 2000 f − Frequency − MHz 400 300 200 100 0 1 2 3 4 5 VIC − Common-Mode Input Voltage − V −40 −20 0 20 40 60 80 Figure 9. PEAK-TO-PEAK JITTER vs FREQUENCY PEAK-TO-PEAK JITTER vs DATA RATE PEAK-TO-PEAK JITTER vs FREQUENCY 60 30 VCC = 3.3 V TA = 25°C VIC = 400 mV Input = PRBS 223 −1 VID = 0.5 V VID = 0.8 V 10 5 40 VID = 0.8 V VID = 0.5 V 30 20 VID = 0.3 V 10 VCC = 3.3 V TA = 25°C VIC = 1.2 V Input = Clock 25 Peak-To-Peak Jitter − ps Peak-To-Peak Jitter − ps 50 20 100 TA − Free Air Temperature − °C Figure 8. VCC = 3.3 V TA = 25°C VIC = 400 mV Input = Clock 15 VCC = 3.3 V VID = 200 mV f = 150 MHz Figure 7. 30 25 tPLH 500 500 0 Peak-To-Peak Jitter − ps Differential Propagation Delay − ps Differential Propagation Delay − ps V O− Differential Output Voltage − mV 350 DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE 20 15 VID = 0.3 V VID = 0.5 V 10 VID = 0.8 V 5 VID = 0.3 V 0 0 0 200 400 600 800 0 0 f − Frequency − MHz 1200 1600 0 Figure 12. PEAK-TO-PEAK JITTER vs DATA RATE PEAK-TO-PEAK JITTER vs FREQUENCY PEAK-TO-PEAK JITTER vs DATA RATE 20 VID = 0.3 V 50 20 Peak-To-Peak Jitter − ps Peak-To-Peak Jitter − ps VID = 0.5 V VID = 0.3 V VID = 0.8 V 15 10 5 VID = 0.3 V 800 30 VID = 0.5 V 20 VCC = 3.3 V TA = 25°C VIC = 2.8 V Input = PRBS 223 −1 10 0 400 VID = 0.8 V 40 VID = 0.5 V 0 1200 Data Rate − Mbps Figure 13. 1600 800 60 VCC = 3.3 V TA = 25°C VIC = 2.8 V Input = Clock 25 VID = 0.8 V 0 600 Figure 11. 40 10 400 f − Frequency − MHz 30 30 200 Figure 10. VCC = 3.3 V TA = 25°C VIC = 1.2 V Input = PRBS 223 −1 50 Peak-To-Peak Jitter − ps 800 Data Rate − Mbps 60 10 400 0 0 200 400 600 f − Frequency − MHz Figure 14. 800 0 400 800 1200 Data Rate − Mbps Figure 15. 1600 SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) PEAK-TO-PEAK JITTER vs TEMPERATURE PEAK-TO-PEAK JITTER vs DATA RATE 50 VCC = 3.3 V TA = 25°C VIC = 1.2 V |V ID |= 200 m V Input = PRBS 223 −1 90 Peak-To-Peak Jitter − ps Peak-To-Peak Jitter - ps 40 100 VCC = 3.3 V TA = 25°C VIC = 1.2 V VID = 200 mV Input = 1.5 Gpbs, PRBS 223 −1 30 20 10 80 70 60 50 40 30 20 10 0 0 −40 −20 0 20 40 60 80 TA − Free Air Temperature − °C Figure 16. LVDS122 622 Mbps, 223– 1 PRBS 100 0 500 1000 1500 2000 2500 3000 3500 Data Rate − Mbps Figure 17. LVDS122 1.5 Gbps, 223– 1 PRBS VCC = 3.3 V TA = 25°C VID = 200 mV Horizontal Scale= 200 ps/div LVPECL-to-LVDS Figure 18. VCC = 3.3 V TA = 25°C VID = 200 mV Horizontal Scale= 100 ps/div LVPECL-to-LVDS Figure 19. 11 SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) LVDS122 622 Mbps, 223– 1 PRBS LVDS122 1.5 Gbps, 223– 1 PRBS VCC = 3.3 V TA = 25°C VID = 200 mV VCC = 3.3 V TA = 25°C VID = 200 mV Horizontal Scale= 200 ps/div LVDS-to-LVDS Horizontal Scale= 100 ps/div LVDS-to-LVDS Figure 20. Power Supply 1 Figure 21. + 3.3 V − Power Supply 2 + 1.22 V − J3 DUT GND J2 EVM GND J1 VCC J4 J5 J6 100 Ω J7 50 Ω DUT Pattern Generator Matched Cables SMA to SMA 50 Ω Matched Cables SMA to SMA EVM Oscilloscope Figure 22. Jitter Setup Connections for SN65LVDS122 12 SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 APPLICATION INFORMATION TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.) 50 Ω 3.3 V or 5 V 3.3 V SN65LVDS122 A ECL B 50 Ω 50 Ω 50 Ω VTT = VCC −2 V VTT Figure 23. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) 3.3 V 50 Ω 50 Ω 3.3 V 3.3 V SN65LVDS122 A CML B 50 Ω 50 Ω 3.3 V Figure 24. Current-Mode Logic (CML) 3.3 V SN65LVDS122 3.3 V 50 Ω A ECL B 50 Ω 1.1 kΩ VTT 1.5 kΩ VTT = VCC −2 V VCC Figure 25. Single-Ended (LVPECL) 3.3 V or 5 V 50 Ω 3.3 V SN65LVDS122 A 100 Ω LVDS B 50 Ω Figure 26. Low-Voltage Differential Signaling (LVDS) 13 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN65LVDS122D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS122 Samples SN65LVDS122DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS122 Samples SN65LVDS122PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS122 Samples SN65LVDS122PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS122 Samples SN65LVDT122D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT122 Samples SN65LVDT122PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT122 Samples SN65LVDT122PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT122 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of