SN65LVELT22DGK

SN65LVELT22 www.ti.com............................................................................................................................................................................................ SLLS928 – DECEMBER 2008 3.3 V Dual LVTTL to DIfferential LVPECL Translator FEATURES APPLICATIONS • • • • 1 • • • 450 ps (typ) Propagation Delay Operating Range: VCC 3.0 V to 3.8 with GND = 0 V 25°C (mW/°C) POWER RATING TA = 85°C (mW) SOIC Low-K 719 139 7 288 High-K 840 119 8 336 Low-K 469 213 5 188 High-K 527 189 5 211 SOIC-TSSOP THERMAL CHARACTERISTICS PARAMETER θJB Junction-to Board Thermal Resistance θJC Junction-to Case Thermal Resistance PACKAGE VALUE UNIT SOIC 79 °C/W SOIC-TSSOP 120 SOIC 98 SOIC-TSSOP 74 °C/W KEY ATTRIBUTES CHARACTERISTICS Moisture sensitivity level VALUE Level 1 Flammability rating (Oxygen Index: 28 to 34) UL 94 V-0 at 0.125 in ESD-HBM 4 kV ESD-machine model 200 V ESD-charge device model 2 kV Meets or exceeds JEDEC Spec EIA/JESD78 latchup test 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVELT22 SN65LVELT22 www.ti.com............................................................................................................................................................................................ SLLS928 – DECEMBER 2008 PECL DC CHARACTERISTICS (1) (VCC = 3.3 V, GND = 0.0 V (2) –40°C CHARACTERISTICS ICC Power Supply Current VOH Output HIGH Voltage VOL (1) (2) (3) Output LOW Voltage MIN 25°C TYP MAX 23 (3) (3) MIN 85°C TYP MAX 33 25 MIN 33 TYP MAX 26 UNIT 33 mA 2275 2317 2420 2275 2331 2420 2275 2343 2420 mV 1490 1558 1680 1490 1556 1680 1490 1555 1680 mV Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Input parameters vary 1:1 with VCC. VCC can vary ±0.15 V Outputs are terminated through a 50-Ω resistor to VCC – 2.0 V. TTL DC CHARACTERISTICS (1) (VCC = 3.3 V; TA = –40°C to 85°C) CHARACTERISTIC CONDITION µA µA Input LOW current VIN = 0.5 V –0.2 mA Input clamp diode voltage IIN = –18 mA –1.2 V IIHH Input HIGH current max IIL VIK VIH Input HIGH voltage VIL Input LOW voltage 2.0 V 0.8 V Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. AC CHARACTERISTICS (1) (VCC = 3.3 V; GND = 0.0 V) –40°C CHARACTERISTIC MIN fMAX Max switching frequency (2), see Figure 5 tPLH/tPHL Propagation delay to output at 1.5V, see Figure 4 tSKEW 25°C TYP MAX MIN 1750 200 425 TYP 85°C MAX MIN 550 200 1750 550 200 445 TYP MAX 1700 460 20 50 20 50 20 50 Device-to-device skew (4) 30 100 30 100 30 100 Random clock jitter (RMS) tr/tf Output rise/fall times Q (20%–80%) 0.5 300 1.0 500 0.5 300 1.0 500 0.5 300 UNIT MHz 550 Within – device skew (3) tJITTER (2) (3) (4) UNIT 100 VIN = 2.7 V (1) TYP MAX VIN = VCC Input HIGH current (1) MIN 20 IIH ps ps 1.0 ps 500 ps Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Maximum switching frequency measured at output amplitude of 300 mVpp. This is measured between outputs under the identical transitions and conditions on any one device. Device-Device Skew is defined as identical transitions at identical VCC levels. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVELT22 3 SN65LVELT22 SLLS928 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com Typical Termination for Output Driver ZO = 50 W P P Driver Receiver N N ZO = 50 W 50 W 50 W VTT VTT = VCC - 2 V Figure 1. Termination for Output Driver 1.5 V 1.5 V IN OUT OUT tPLH tPHL Figure 2. Output Propagation Delay 80% 20% tr tf Figure 3. Output Rise and Fall Times 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVELT22 SN65LVELT22 www.ti.com............................................................................................................................................................................................ SLLS928 – DECEMBER 2008 1.5 V 1.5 V IN QO QO tPLH0 tPHL0 Q1 Q1 tPLH1 tPHL1 Device Skew = Higher [(tPLH1 - tPLH0), (tPHL1 - tPHL0)] Figure 4. Device Skew 1000 VCC = 3.3 V, GND = 0 V, Vswing = 0.8 V - 2 V 900 Output Amplitude - mV 800 700 TA = 85°C 600 500 TA = -40°C 400 TA = 25°C 300 200 100 0 0 500 1000 1500 f - Frequency - MHz 2000 2500 Figure 5. Output Amplitude vs. Frequency Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVELT22 5 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVELT22DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65LVELT22DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVELT22DGKR VSSOP DGK 8 2500 356.0 356.0 35.0 SN65LVELT22DR SOIC D 8 2500 356.0 356.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TUBE T - Tube height L - Tube length W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) SN65LVELT22D D SOIC 8 75 506.6 8 3940 4.32 SN65LVELT22DGK DGK VSSOP 8 80 330.2 6.6 3005 1.88 Pack Materials-Page 3 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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