SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
FEATURES
APPLICATIONS
•
•
1
•
•
•
•
•
•
•
•
Low-Voltage Differential 30-Ω to 55-Ω Line
Drivers and Receivers for Signaling Rates(1)
Up to 200 Mbps
Type-1 Receivers Incorporate 25 mV of
Hysteresis
Type-2 Receivers Provide an Offset (100 mV)
Threshold to Detect Open-Circuit and Idle-Bus
Conditions
Meets or Exceeds the M-LVDS Standard
TIA/EIA-899 for Multipoint Data Interchange
Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
-1 V to 3.4 V Common-Mode Voltage Range
Allows Data Transfer With 2 V of Ground Noise
Bus Pins High Impedance When Disabled or
VCC ≤ 1.5 V
100-Mbps Devices Available (SN65MLVD200A,
202A, 204A, 205A)
M-LVDS Bus Power Up/Down Glitch Free
•
•
•
•
Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485
Backplane or Cabled Multipoint Data and
Clock Transmission
Cellular Base Stations
Central-Office Switches
Network Switches and Routers
DESCRIPTION
The SN65MLVD201, 203, 206, and 207 are
multipoint-low-voltage differential (M-LVDS) line
drivers and receivers, which are optimized to operate
at signaling rates up to 200 Mbps. All parts comply
with the multipoint low-voltage differential signaling
(M-LVDS) standard TIA/EIA-899. These circuits are
similar to their TIA/EIA-644 standard compliant LVDS
counterparts, with added features to address
multipoint applications. The driver output has been
designed to support multipoint buses presenting
loads as low as 30 Ω, and incorporates controlled
transition times to allow for stubs off of the backbone
transmission line.
The signaling rate of a line, is the number of voltage transitions
that are made per second expressed in the units bps (bits per
second).
These devices have Type-1 and Type-2 receivers
that detect the bus state with as little as 50 mV of
differential input voltage over a common-mode
voltage range of -1 V to 3.4 V. The Type-1 receivers
exhibit 25 mV of differential input voltage hysteresis
to prevent output oscillations with slowly changing
signals or loss of input. Type-2 receivers include an
offset threshold to provide a known output state
under open-circuit, idle-bus, and other faults
conditions. The devices are characterized for
operation from –40°C to 85°C.
LOGIC DIAGRAM (POSITIVE LOGIC)
SN65MLVD201, SN65MLVD206
DE
D
RE
SN65MLVD203, SN65MLVD207
3
D
4
DE
2
1
R
RE
6
7
A
B
5
10
4
Y
Z
3
2
R
9
12
11
A
B
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2007, Texas Instruments Incorporated
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER (1)
(1)
FOOTPRINT
RECEIVER TYPE
PACKAGE MARKING
SN65MLVD201D
SN75176
Type 1
MF201
SM65MLVD203D
SN75ALS180
Type 1
MLVD203
SN65MLVD206D
SN75176
Type 2
MF206
SM65MLVD207D
SN75ALS180
Type 2
MLVD207
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
PACKAGE DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
D(8)
725 mW
5.8 mW/°C
377 mW
D(14)
950 mW
7.6 mW/°C
494 mw
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE / UNIT
Supply voltage range
(2)
Input voltage range
, VCC
–0.5 V to 4 V
D, DE, RE
–0.5 V to 4 V
A, B (201, 206)
–1.8 V to 4 V
A, B (203, 207)
Output voltage range
Electrostatic discharge
–4 V to 6 V
R
–0.3 V to 4 V
Y, Z, A, or B
–1.8 V to 4 V
Human Body Model (3)
Charged-Device Model (4)
A, B, Y, and Z
±8 kV
All pins
±2 kV
All pins
±1500 V
Continuous power dissipation
See Dissipation Rating Table
Storage temperature range
(1)
(2)
(3)
(4)
–65°C to 150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
VCC
Supply voltage
3
3.3
3.6
V
VIH
High-level input voltage
2
VCC
V
VIL
Low-level input voltage
GND
0.8
V
Voltage at any bus terminal VA, VB, VY or VZ
–1.4
3.8
V
|VID|
Magnitude of differential input voltage
0.05
VCC
V
TA
Operating free-air temperature
–40
85
°C
2
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MAX UNIT
Copyright © 2002–2007, Texas Instruments Incorporated
Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207
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SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
(1)
Supply current
TEST CONDITIONS
MIN TYP (1)
MAX
13
22
1
4
Driver only
RE and DE at VCC, RL = 50 Ω, All others open
Both disabled
RE at VCC, DE at 0 V, RL = No Load, All others open
Both enabled
RE at 0 V, DE at VCC, RL = 50 Ω, All others open
16
24
Receiver only
RE at 0 V, DE at 0 V, RL = 50 Ω, All others open
4
13
UNIT
mA
All typical values are at 25°C and with a 3.3-V supply voltage.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN (1) TYP (2)
TEST CONDITIONS
|VAB| or
|VYZ|
Differential output voltage magnitude
Δ|VAB| or
Δ|VYZ|
Change in differential output voltage magnitude
between logic states
VOS(SS)
Steady-state common-mode output voltage
ΔVOS(SS)
Change in steady-state common-mode output
voltage between logic states
VOS(PP)
Peak-to-peak common-mode output voltage
VY(OC) or
VA(OC)
Maximum steady-state open-circuit output
voltage
VZ(OC) or
VB(OC)
Maximum steady-state open-circuit output
voltage
VP(H)
Voltage overshoot, low-to-high level output
VP(L)
Voltage overshoot, high-to-low level output
IIH
High-level input current (D, DE)
VIH = 2 V
IIL
Low-level input current (D, DE)
VIL = 0.8 V
JIOSJ
Differential short-circuit output current magnitude See Figure 4
IOZ
High-impedance state output current (driver only)
–1.4 V ≤ VY or VZ ≤ 3.8 V,
Other output = 1.2 V
IO(OFF)
Power-off output current
–1.4 V ≤ VY or VZ ≤ 3.8 V,
Other output = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
CY or CZ
Output capacitance
VI = 0.4 sin(30E6πt) + 0.5 V, (3)
Other input at 1.2 V, Driver disabled
CYZ
Differential output capacitance
CY/Z
Output capacitance balance, (CY/CZ)
(1)
(2)
(3)
MAX
UNIT
480
650
mV
–50
50
mV
0.8
1.2
V
–50
50
mV
150
mV
0
2.4
V
0
2.4
V
1.2 VSS
V
0
10
µA
0
10
µA
24
mA
–15
10
µA
–10
10
µA
See Figure 2
See Figure 3
See Figure 7
See Figure 5
VAB = 0.4 sin(30E6πt) V,
Driver disabled
–0.2 VSS
V
3
pF
(3)
2.5
0.99
pF
1.01
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
Copyright © 2002–2007, Texas Instruments Incorporated
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3
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SN65MLVD206, SN65MLVD207
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted (1)
PARAMETER
TEST CONDITIONS
50
Type 2
150
Positive-going differential input voltage threshold
VIT-
Negative-going differential input voltage threshold
VHYS
Differential input voltage hysteresis, (VIT+ – VIT)
VOH
High-level output voltage
IOH = –8 mA
VOL
Low-level output voltage
IOL = 8 mA
IIH
High-level input current (RE)
VIH = 2 V
IIL
Low-level input current (RE)
VIL = 0.8 V
IOZ
High-impedance output current
VO = 0 V or 3.6 V
Input capacitance
VI = 0.4 sin(30E6πt) + 0.5 V, (2)
Other input at 1.2 V
CAB
Differential input capacitance
CA/B
Input capacitance balance, (CA/CB)
(1)
(2)
4
MAX
Type 1
VIT+
CA or CB
MIN TYP (1)
Type 1
Type 2
See Figure 9 and Table 1 and
Table 2
–50
mV
mV
50
Type 1
25
Type 2
0
mV
2.4
VAB = 0.4 sin(30E6πt) V
UNIT
V
0.4
V
–10
0
µA
–10
0
µA
–10
15
µA
3
(2)
pF
2.5
0.99
pF
1.01
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
Submit Documentation Feedback
Copyright © 2002–2007, Texas Instruments Incorporated
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SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Receiver or transceiver with driver
disabled input current
IA
IB
Receiver or transceiver with driver
disabled input current
IAB
Receiver or transceiver with driver
disabled differential input current
(IA – IB)
IA(OFF)
Receiver or transceiver power-off
input current
IB(OFF)
Receiver or transceiver power-off
input current
MIN TYP (1) MAX
TEST CONDITIONS
VA = 3.8 V,
VB = 1.2 V,
0
32
VA = 0 V or 2.4 V,
VB = 1.2 V
–20
20
VA = –1.4 V,
VB = 1.2 V
–32
0
VB = 3.8 V,
VA = 1.2 V
0
32
VB = 0 V or 2.4 V,
VA = 1.2 V
–20
20
VB = –1.4 V,
VA = 1.2 V
–32
0
VA = VB,
1.4 ≤ VA ≤ 3.8 V
-4
4
VA = 3.8 V,
VB = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
0
32
VA = 0 V or 2.4 V,
VB = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
–20
20
VA = –1.4 V,
VB= 1.2 V,
0 V ≤ VCC ≤ 1.5 V
–32
0
VB = 3.8 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
0
32
VB = 0 V or 2.4 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
–20
20
VB = –1.4 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
–32
0
–4
4
UNIT
µA
µA
µA
µA
µA
IAB(OFF)
Receiver input or transceiver
power-off differential input current
(IA – IB)
VA = VB, 0 V ≤ VCC ≤ 1.5 V, –1.4 ≤ VA ≤ 3.8 V
CA
Transceiver with driver disabled input
capacitance
VA = 0.4 sin (30E6πt) + 0.5V (2),
VB = 1.2 V
5
pF
CB
Transceiver with driver disabled input
capacitance
VB = 0.4 sin (30E6πt) + 0.5 V (2),
VA = 1.2 V
5
pF
CAB
Transceiver with driver disabled
differential input capacitance
VAB = 0.4 sin (30E6πt)V (2)
CA/B
Transceiver with driver disabled input
capacitance balance, (CA/CB)
(1)
(2)
3
0.99
µA
pF
1.01
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX UNIT
tPLH
Propagation delay time, low-to-high-level output
1
1.5
2.4
ns
tPHL
Propagation delay time, high-to-low-level output
1
1.5
2.4
ns
tr
Differential output signal rise time
1
1.6
ns
tf
Differential output signal fall time
1
1.6
ns
tsk(p)
Pulse skew (|tPHL – tPLH|)
100
ps
tsk(pp)
Part-to-part skew (2)
1
ns
2
3
ps
30
130
ps
7
ns
7
ns
7
ns
7
ns
See Figure 5
0
(3)
tjit(per)
Period jitter, rms (1 standard deviation)
tjit(pp)
Peak-to-peak jitter (3)
tPHZ
Disable time, high-level-to-high-impedance output
tPLZ
Disable time, low-level-to-high-impedance output
tPZH
Enable time, high-impedance-to-high-level output
tPZL
Enable time, high-impedance-to-low-level output
(1)
(2)
(3)
(4)
(5)
(6)
(5)
100 MHz clock input
(4)
200 Mbps 215–1 PRBS input (6)
See Figure 6
All typical values are at 25°C and with a 3.3-V supply voltage.
tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
Copyright © 2002–2007, Texas Instruments Incorporated
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
tpLH
Propagation delay time, low-to-high-level output
2
4
6
ns
tpHL
Propagation delay time, high-to-low-level output
2
4
6
ns
tr
Output signal rise time
1
2.3
ns
tf
Output signal fall time
1
2.3
ns
CL = 15 pF, See Figure 10
Type 1
100
300
ps
Type 2
300
500
ps
1
ns
4
7
ps
300
700
ps
450
800
ps
tsk(p)
Pulse skew (|tpHL – tpLH|)
tsk(pp)
Part-to-part skew (2)
tjit(per)
Period jitter, rms (1 standard deviation)
tjit(pp)
Peak-to-peak jitter (3) (5)
tpHZ
Disable time, high-level-to-high-impedance output
10
ns
tpLZ
Disable time, low-level-to-high-impedance output
10
ns
tpZH
Enable time, high-impedance-to-high-level output
15
ns
tpZL
Enable time, high-impedance-to-low-level output
15
ns
(1)
(2)
(3)
(4)
(5)
(6)
6
100 MHz clock input (4)
(3)
Type 1
Type 2
200 Mbps 215–1 PRBS input (6)
See Figure 11
All typical values are at 25°C and with a 3.3-V supply voltage.
tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
VID = 200 mVpp (LVD201, 203), VID = 400 mVpp (LVD206, 207), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
VID = 200 mVpp (LVD201, 203), VID = 400 mVpp (LVD206, 207), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
IA or IY
A/Y
II
D
IB or IZ
VAB or VYZ
VA or VY
B/Z
VI
VOS
VB or VZ
VA + VB
2
or
VY + VZ
2
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
A/Y
VAB or VYZ
D
B/Z
A.
+
_
49.9 Ω
-1 V ≤ Vtest ≤ 3.4 V
3.32 kΩ
All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
R1
24.9 Ω
A/Y
C1
1 pF
D
≈ 1.3 V
B/Z
≈ 0.7 V
VOS(PP)
B/Z
C2
1 pF
A/Y
R2
24.9 Ω
VOS
C3
2.5 pF
VOS(SS)
VOS
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse frequency = 500
kHz, duty cycle = 50 ± 5%.
B.
C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C.
R1 and R2 are metal film, surface mount, 1%, and located within 2 cm of the D.U.T.
D.
The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A/Y
IOS
0 V or VCC
+
B/Z
VTest
-1 V or 3.4 V
-
Figure 4. Driver Short-Circuit Test Circuit
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
A/Y
D
C1
1 pF
C3
0.5 pF
R1
Output
50 Ω
B/Z
C2
1 pF
VCC
VCC/2
Input
0V
tpLH
tpHL
VSS
0.9VSS
VP(H)
Output
0V
VP(L)
0.1V
SS
0 V SS
tf
tr
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 5%.
B.
C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C.
R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D.
The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
A/Y
0 V or VCC
C1
1 pF
D
B/Z
DE
C4
Output
0.5 pF
C2
1 pF
R2
24.9 Ω
VCC
VCC/2
0V
DE
tpZH
tpHZ
∼ 0.6 V
0.1 V
0V
Output With
D at VCC
Output With
D at 0 V
C3
2.5 pF
tpZL
tpLZ
0V
-0.1 V
∼ -0.6 V
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 5%.
B.
C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C.
R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D.
The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
8
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
A/Y
0 V or VCC
B/Z
VA, VB, VY or VZ
1.62 kΩ , ±1%
Figure 7. Maximum Steady State Output Voltage
VCC
CLOCK
INPUT
VCC/2
0V
1/f0
Period Jitter
IDEAL
OUTPUT 0 V
VCC
PRBS INPUT
VA -VB or VY -VZ
0V
ACTUAL
OUTPUT 0 V
VA -VB or VY -VZ
VCC/2
1/f0
Peak to Peak Jitter
VA -VB or VY -VZ
OUTPUT 0 V Diff
tc(n)
tjit(per) = tc(n) -1/f0
VA -VB or VY -VZ
tjit(pp)
A.
All input pulses are supplied by an Agilent 8304A Stimulus System.
B.
The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C.
Period jitter is measured using a 100 MHz 50 1% duty cycle clock input.
D.
Peak-to-peak jitter is measured using a 200Mbps 215-1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
IA
A
VID
VCM
(VA + VB)/2
VA
IB
R
IO
B
VO
VB
Figure 9. Receiver Voltage and Current Definitions
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
Table 1. Type-1 Receiver Input Threshold Test Voltages
APPLIED
VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
VID
VIC
RECEIVER
OUTPUT (1)
VIA
VIB
2.400
0.000
2.400
1.200
0.000
2.400
–2.400
1.200
L
3.800
3.750
0.050
3.775
H
3.750
3.800
–0.050
3.775
L
–1.350
–1.400
0.050
–1.375
H
–1.400
–1.350
–0.050
–1.375
L
(1)
H
H = high level, L = low level, output state assumes receiver is enabled (RE = L)
Table 2. Type-2 Receiver Input Threshold Test Voltages
APPLIED
VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
RECEIVER
OUTPUT (1)
VIA
VIB
VID
VIC
2.400
0.000
2.400
1.200
H
0.000
2.400
–2.400
1.200
L
3.800
3.650
0.150
3.725
H
3.800
3.750
0.050
3.775
L
–1.250
–1.400
0.150
–1.325
H
–1.350
–1.400
0.050
–1.375
L
(1)
H = high level, L = low level, output state assumes receiver is enabled (RE = L)
VID
VA
CL
VO
15 pF
VB
VA
1.2 V
VB
1.0 V
VID
0.2 V
0V
-0.2 V
tpHL
VO
tpLH
VOH
90%
VCC/2
VOL
10%
tf
tr
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 50 MHz,
duty cycle = 50 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture
capacitance within 2 cm of the D.U.T.
B.
The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 10. Receiver Timing Test Circuit and Waveforms
10
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
1.2 V
B
RL
499 Ω
R
A
Inputs
CL
RE
VO
+
_
VTEST
15 pF
VCC
VTEST
1V
A
VCC
RE
VCC/2
0V
tpZL
Output
tpLZ
VCC
VCC/2
VOL +0.5 V
VOL
R
VTEST
0V
1.4 V
A
VCC
RE
VCC/2
0V
tpZH
tpHZ
VO
VOH
VOH -0.5 V
VCC/2
0V
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 5%.
B.
RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C.
RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
D.
CL is the instrumentation and fixture capacitance within 2 cm of the DUT and 20%.
Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
INPUTS
VA -VB
0.2 V - Type 1
0.4 V - Type 2
CLOCK INPUT
VA -VB
1/f0
VIC
1V
Period Jitter
IDEAL
OUTPUT
VOH
VA
VCC/2
PRBS INPUT
VOL
1/f0
VB
VOH
ACTUAL
OUTPUT VCC/2
Peak to Peak Jitter
VOH
VOL
tc(n)
tjit(per) = tc(n) -1/f0
OUTPUT V
CC/2
VOL
tjit(pp)
A.
All input pulses are supplied by an Agilent 8304A Stimulus System.
B.
The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C.
Period jitter is measured using a 100 MHz 50 1% duty cycle clock input.
D.
Peak-to-peak jitter is measured using a 200 Mbps 215-1 PRBS input.
Figure 12. Receiver Jitter Measurement Waveforms
PIN ASSIGNMENTS
SN65MLVD201D (Marked as MF201)
SN65MLVD206D (Marked as MF206)
(TOP VIEW)
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
SN65MLVD203D (Marked as MLVD203)
SN65MLVD207D (Marked as MLVD207)
(TOP VIEW)
NC
R
RE
DE
D
GND
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
NC - No internal connection
12
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
DEVICE FUNCTION TABLES
TYPE-1 RECEIVER (201, 203)
INPUTS
TYPE-2 RECEIVER (206, 207)
OUTPUT
INPUTS
OUTPUT
VID = VA - VB
RE
R
VID = VA - VB
RE
R
VID ≥ 50 mV
- 50 mV < VID < 50 mV
VID ≤ - 50 mV
X
X
L
L
L
H
Open
H
?
L
Z
Z
VID ≥ 150 mV
50 mV < VID < 150 mV
VID ≤ 50 mV
X
X
L
L
L
H
Open
H
?
L
Z
Z
Open Circuit
L
?
Open Circuit
L
L
DRIVER
INPUT
ENABLE
D
L
H
OPEN
X
X
DE
H
H
H
OPEN
L
OUTPUTS
A OR Y
B OR Z
L
H
L
Z
Z
H
L
H
Z
Z
H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
DRIVER OUTPUT
DRIVER INPUT AND DRIVER ENABLE
RECEIVER ENABLE
VCC
VCC
VCC
360 kΩ
400 Ω
400 Ω
D or DE
A/Y or B/Z
7V
RE
7V
360 kΩ
RECEIVER INPUT
RECEIVER OUTPUT
VCC
VCC
100 kΩ
100 kΩ
250 kΩ
10 Ω
250 kΩ
A
R
B
10 Ω
200 kΩ
Copyright © 2002–2007, Texas Instruments Incorporated
200 kΩ
7V
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
20
20
16
ICC − Supply Current − mA
ICC − Supply Current − mA
VCC = 3.3 V
TA = 25°C
Driver
12
8
Receiver
4
16
Driver
12
Receiver
8
4
Receiver
VID = 250 mV
VIC = 1 V
0
10
50
30
90
70
VCC = 3.3 V
TA = 25°C
f = 100 MHz
0
110
−50
f − Frequency − MHz
70
Figure 14.
RECEIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
RECEIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
90
0
TA = 25°C
60
VCC = 3.6 V
50
VCC = 3.3 V
40
VCC = 3.0 V
IOH − Receiver High Level Output Current − mA
IOL − Receiver Low Level Output Current − mA
14
10
−10
30
50
TA − Free-Air Temperature − °C
Figure 13.
70
30
20
10
0
−30
Receiver
VID = 250 mV
VIC = 1 V
0
1
2
3
4
TA = 25°C
−10
−20
−30
VCC = 3.0 V
−40
−50
VCC = 3.3 V
−60
−70
VCC = 3.6 V
−80
−90
0
1
2
3
VOL − Low Level Output Voltage − V
VOH − High Level Output Voltage − V
Figure 15.
Figure 16.
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
DRIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
2
2
1.6
Driver Propagation Delay − ns
Differential Output Voltage − V
VCC = 3.3 V
f = 1 MHz
1.2
0.8
0.4
1.8
tpLH
1.6
tpHL
1.4
1.2
VCC = 3.3 V
TA = 25°C
0
0
1
−50
IO − Output Current − mA
10
50
−10
30
TA − Free-Air Temperature − °C
Figure 17.
Figure 18.
RECEIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
ADDED DRIVER CYCLE-TO-CYCLE
JITTER (PEAK)
vs
FREQUENCY
4
2
6
8
10
12
tpHL
4
tpLH
2
1
−50
70
90
45
VCC = 3.3 V
VID = 250 mV
VIC = 1 V
f = 1 MHz
Added Driver Cycle-To-Cycle Jitter − pa
Receiver Propagation Delay − ns
6
−30
VCC = 3.3 V
TA = 25°C
Input = Clock
36
27
18
9
0
−30
10
50
−10
30
TA − Free-Air Temperature − °C
Figure 19.
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70
90
10
30
50
70
90
110
f − Frequency − MHz
Figure 20.
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
ADDED DRIVER PEAK-TO-PEAK JITTER
vs
DATA RATE
60
VCC = 3.3 V
TA = 25°C
Input = PRBS 215−1
Added Driver Peak-To-Peak Jitter − ps
Added Driver Peak-To-Peak Jitter − ps
60
ADDED DRIVER PEAK-TO-PEAK JITTER
vs
FREE-AIR TEMPERATURE
50
40
30
20
10
0
25
105
65
145
185
50
40
30
20
VCC = 3.3 V
TA = 25°C
Input = PRBS 215−1
f = 200 Mbps
10
0
−50
225
−30
Figure 21.
ADDED RECEIVER CYCLE-TO-CYCLE JITTER
vs
FREQUENCY
VIC = 3.0 V
21
VIC = −0.5 V
VIC = 1 V
14
7
0
10
30
50
70
f − Frequency − MHz
Figure 23.
16
Added Receiver Peak-To-Peak Jitter − ps
Added Receiver Cycle-To-Cycle Jitter − ps
400
28
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10
30
50
70
90
ADDED RERCEIVER PEAK-TO-PEAK JITTER
vs
FREE-AIR TEMPERATURE
35
VCC = 3.3 V
VID = 250 mV
TA = 25°C
−10
TA − Free-Air Temperature − °C
Figure 22.
Data Rate − Mbps
90
110
VCC = 3.3 V
VID = 250 mV
TA = 25°C
Pattern = 215−1
320
240
160
80
0
0
30
60
120
150
90
Data Rate − Mbps
180
210
Figure 24.
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SN65MLVD206, SN65MLVD207
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
SN65MLVD201 DRIVER OUTPUT
EYE PATTERN
200 Mbps, 215–1 PRBS, RL = 50 Ω
ADDED RECEIVER PEAK-TO-PEAK JITTER
vs
FREE-AIR TEMPERATURE
Vertical Scale = 175 mV/div
Added Receiver Peak-To-Peak Jitter − ps
400
320
240
160
80
0
−50
VCC = 3.3 V
VID = 250 mV
VIC =1 V
f =200 Mbps
Pattern = 215−1
−30
Horizontal Scale = 1 ns/div
10
50
−10
30
TA − Free-Air Temperature − °C
70
90
Figure 25.
Figure 26.
Vertical Scale = 400 mV/div
SN65MLVD201 RECEIVER OUTPUT
EYE PATTERN
200 Mbps, 215–1 PRBS, RL = 15 Ω
Horizontal Scale = 1 ns/div
Figure 27.
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
APPLICATION INFORMATION
Receiver Input Threshold (Failsafe)
The MLVD standard defines a type 1 and type 2 receiver. Type 1 receivers include no provisions for failsafe and
have their differential input voltage thresholds near zero volts. Type 2 receivers have their differential input
voltage thresholds offset from zero volts to detect the absence of a voltage difference. The impact to receiver
output by the offset input can be seen in Table 3 and Figure 28.
Table 3. Receiver Input Voltage Threshold Requirements
RECEIVER TYPE
OUTPUT LOW
OUTPUT HIGH
Type 1
–2.4 V ≤ VID ≤ –0.05 V
0.05 V ≤ VID ≤ 2.4 V
Type 2
–2.4 V ≤ VID ≤ 0.05 V
0.15 V ≤ VID ≤ 2.4 V
200
Type 1
Type 2
VID - Differential Input Voltage - mV
High
150
100
High
50
0
Low
-50
-100
Low
Transition Regions
Figure 28. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region
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SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
LIVE INSERTION/GLITCH-FREE POWER UP/DOWN
The SN65MLVD201/203/206/207 family of products offered by Texas Instruments provides a glitch-free
powerup/down feature that prevents the M-LVDS outputs of the device from turning on during a powerup or
powerdown event. This is especially important in live insertion applications, when a device is physically
connected to an M-LVDS multipoint bus and VCC is ramping.
While the M-LVDS interface for these devices is glitch free on powerup/down, the receiver output structure is
not.Figure 29 shows the performance of the receiver output pin, R (CHANNEL 2), as Vcc (CHANNEL 1) is
ramped.
Figure 29. M-LVDS Receiver Output: VCC (CHANNEL 1), R Pin (CHANNEL 2)
The glitch on the R pin is independent of the RE voltage. Any complications or issues from this glitch are easily
resolved in power sequencing or system requirements that suspend operation until VCC has reached a steady
state value.
Copyright © 2002–2007, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65MLVD201D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF201
SN65MLVD201DG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF201
SN65MLVD201DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF201
SN65MLVD203D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MLVD203
SN65MLVD203DG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MLVD203
SN65MLVD203DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MLVD203
SN65MLVD206D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF206
SN65MLVD206DG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF206
SN65MLVD206DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF206
SN65MLVD207D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MLVD207
SN65MLVD207DG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MLVD207
SN65MLVD207DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MLVD207
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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