SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
D Low-Voltage Differential 30-Ω Line Drivers
D
D
D
D
D
and Receivers for Signaling Rates† up to
100 Mbps
Power Dissipation at 100 Mbps
– Driver: 50 mW Typical
– Receiver: 30 mW Typical
Meets or Exceeds Current Revision of
M-LVDS Standard TIA/EIA–899 for
Multipoint Data Interchange
Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
–1-V to 3.4-V Common-Mode Voltage Range
Allows Data Transfer With up to 2 V of
Ground Noise
Type-1 Receivers Incorporate 25 mV of
Hysteresis
SN65MLVD200D (Marked as MF200)
SN65MLVD204D (Marked as MF204)
(TOP VIEW)
R
RE
DE
D
1
8
2
7
3
6
4
5
D Type-2 Receivers Provide an Offset
D
D
D
D
D
D
(100 mV) Threshold to Detect Open-Circuit
and Idle-Bus Conditions
Operates From a Single 3.3-V Supply
Propagation Delay Times Typically 2.3 ns
for Drivers and 5 ns for Receivers
Power-Up/Down Glitch-Free Driver
Driver Handles Operation Into a
Continuous Short Circuit Without Damage
Bus Pins High Impedance When Disabled
or VCC ≤ 1.5 V
200-Mbps Devices Available
(SN65MLVD201, 203, 206, and 207)
SN65MLVD202D (Marked as MLVD202)
SN65MLVD205D (Marked as MLVD205)
(TOP VIEW)
VCC
B
A
GND
NC
R
RE
DE
D
GND
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
NC – No internal connection
logic diagram (positive logic)
SN65MLVD200, SN65MLVD204
DE
D
RE
D
4
DE
2
1
R
SN65MLVD202, SN65MLVD205
3
RE
6
7
5
10
4
R
B
Y
Z
3
2
A
9
12
11
A
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The signaling rate of a line is the number of voltage transitions that are made per second expressed in bps (bits per second) units.
Copyright 2001–2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
description
This series of SN65MLVD20x devices are low-voltage differential line drivers and receivers complying with the
proposed multipoint low-voltage differential signaling (M-LVDS) standard (TIA/EIA–899). These circuits are
similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint
applications. Driver output current has been increased to support doubly-terminated, 50-Ω load multipoint
applications. Driver output slew rates are optimized for signaling rates up to 100 Mbps.
Types 1 and 2 receivers are available. Both types of receivers operate over a common-mode voltage range of
–1 V to 3.4 V to provide increased noise immunity in harsh electrical environments. Type-1 receivers have their
differential input voltage thresholds near zero volts (±50 mV), and include 25 mV of hysteresis to prevent output
oscillations in the presence of noise. Type-2 receivers include an offset threshold to detect open-circuit, idle-bus,
and other fault conditions, and provide a known output state under these conditions.
The intended application of these devices is in half-duplex or multipoint baseband data transmission over
controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media may
be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
application-specific characteristics).
These devices are characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
NOMINAL
SIGNALING RATE,
Mbps
FOOTPRINT
RECEIVER TYPE
PART NUMBER†
100
SN75176
Type 1
SN65MLVD200D
100
SN75ALS180
Type 1
SN65MLVD202D
100
SN75176
Type 2
SN65MLVD204D
100
SN75ALS180
Type 2
SN65MLVD205D
† The D package is available taped and reeled. Add the R suffix to the device type (e.g., SN65MLVD200DR)
Function Tables
TYPE-1 RECEIVER (200, 202)
INPUTS
TYPE-2 RECEIVER (204, 205)
OUTPUT
VID = VA – VB
RE
R
VID ≥ 50 mV
– 50 mV < VID < 50 mV
VID ≤ – 50 mV
X
X
L
L
L
H
Open
H
?
L
Z
Z
Open Circuit
L
?
INPUTS
VID = VA – VB
R
VID ≥ 150 mV
50 mV < VID < 150 mV
VID ≤ 50 mV
X
X
L
L
L
H
Open
H
?
L
Z
Z
Open Circuit
L
L
DRIVER
INPUT
ENABLE
D
L
H
OPEN
X
X
DE
H
H
H
OPEN
L
OUTPUTS
A OR Y
B OR Z
L
H
L
Z
Z
H
L
H
Z
Z
H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate
2
POST OFFICE BOX 655303
OUTPUT
RE
• DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
equivalent input and output schematic diagrams
DRIVER INPUT AND DRIVER ENABLE
RECEIVER OUTPUT
RECEIVER ENABLE
VCC
VCC
VCC
360 kΩ
400 Ω
7V
10 Ω
400 Ω
D or DE
RE
R
7V
360 kΩ
10 Ω
7V
RECEIVER INPUT
DRIVER OUTPUT
VCC
VCC
100 kΩ
100 kΩ
250 kΩ
A/Y or B/Z
250 kΩ
A
B
200 kΩ
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
200 kΩ
3
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Input voltage range: D, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
A, B (200, 204) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.8 V to 4 V
A, B (202, 205) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to 6 V
Output voltage range: R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Y, Z, A, or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.8 V to 4 V
Electrostatic discharge: Human body model (see Note 2)
A, B, Y, or Z . . . . . . . . . . . . . . . . . . . . . . ±3 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 kV
Charged-device model (see Note 3) All pins . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating table)
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
D(8)
725 mW
5.8 mW/°C
377 mW
D(14)
950 mW
7.6 mW/°C
494 mW
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC
3
3.3
3.6
V
High-level input voltage, VIH
2
VCC
0.8
V
V
Low-level input voltage, VIL
0
UNIT
V
Magnitude of differential input voltage, VID
0.05
Voltage at any bus terminal, VA, VY, VZ, or VB
–1.4
VCC
3.8
–1
3.4
V
5
15
pF
–40
85
°C
Common-mode input voltage VCM, (VA + VB)/2
Receiver load capacitance, CL
Operating free-air temperature, TA
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
device electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
ICC
TEST CONDITIONS
Receiver disabled and driver enabled
RE and DE at VCC,
RL = 50 Ω, All others open
Driver and receiver disabled
RE at VCC, DE at 0 V,
RL = No load, All others open
Receiver enabled and driver enabled
RE at 0 V, DE at VCC,
RL = 50 Ω, All others open,
No receiver load
Receiver enabled and driver disabled
RE at 0 V, DE at 0 V,
All others open, No receiver load
Supply current
MIN†
TYP‡
MAX
13
22
1
7
16
26
4
11
UNIT
mA
† The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
‡ All typical values are at 25°C and with a 3.3-V supply voltage.
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VAB or
VYZ
Differential output voltage magnitude
See Figure 2
∆VABor
∆VYZ
Change in differential output voltage magnitude
between logic states
See Figure 2
VOS(SS)
Steady-state common-mode output voltage
∆VOS(SS)
Change in steady-state common-mode output
voltage between logic states
VOS(PP)
VA(OC) or
VY(OC)
Peak-to-peak common-mode output voltage
VB(OC) or
VZ(OC)
See Figure 3
Maximum steady-state open-circuit output voltage
MIN†
TYP‡
MAX
UNIT
480
650
mV
–50
50
mV
0.8
1.2
V
–50
50
mV
150
mV
0
2.4
V
0
2.4
V
1.2VSS
V
–0.2VSS
0
10
µA
0
10
µA
24
mA
See Figure 7
Maximum steady-state open-circuit output voltage
VP(H)
VP(L)
Voltage overshoot, low-to-high level output
IIH
IIL
High-level input current
Low-level input current
VIH = 2 V
VIL = 0.8 V
IOS
Differential short-circuit output current
See Figure 4
IOZ
High-impedance state output current (driver only)
–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
Other output at 1.2 V
– 15
10
µA
IO(OFF)
Power-off output current (driver only)
–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
VCC ≤ 1.5 V,
Other output at 1.2 V
– 10
10
µA
Voltage overshoot, high-to-low level output
See Figure 5
V
† The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
‡ All typical values are at 25°C and with a 3.3-V supply voltage.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive going differential input voltage threshold
Positive-going
VIT–
Negative going differential input voltage threshold
Negative-going
VID(HYS)
hysteresis VIT+ – VIT–
Differential input voltage hysteresis,
VOH
VOL
High-level output voltage
IIH
IIL
High-level input current
MIN
TYP†
MAX
Type 1
50
Type 2
150
Type 1
Type 2
See Figure 8,
Table 1 and Table 2
mV
50
25
Type 2
0
Low-level input current
IOZ
High-impedance output current
† All typical values are at 25°C and with a 3.3-V supply voltage.
mV
–50
Type 1
Low-level output voltage
UNIT
mV
IOH = –8 mA
IOL = 8 mA
2.4
V
0.4
V
VIH = 2 V
VIL = 0.8 V
–10
0
µA
–10
0
µA
VO = 0 V or 3.6 V
–10
15
µA
bus input and output electrical characteritics over recommended operating conditions (unless
otherwise noted)
PARAMETER
IA
IB
TEST CONDITIONS
R
i
i
t or transceiver
t
i
iinput/output
t/ t t
Receiver
input
current
Receiver
R
i
input
i
t or transceiver
t
i
iinput/output
t/ t t
current
IAB
Receiver input or transceiver input/output
differential current (IA – IB)
IA(OFF)
Receiver
R
i
input
i
t or transceiver
t
i
iinput/output
t/ t t
power-off current
IB(OFF)
IAB(OFF)
CA
CB
Receiver
R
i
input
i
t or transceiver
t
i
iinput/output
t/ t t
power-off current
Receiver input or transceiver input/output
power-off differential current (IA – IB)
Receiver input, driver high-impedance
output or transceiver input/output
output,
capacitance
TYP†
MAX
VA = 3.8 V,
VA = 0 V or 2.4 V,
VB = 1.2 V
VB = 1.2 V
VA = –1.4 V,
VB = 3.8 V,
VB = 1.2 V
VA = 1.2 V
VB = 0 V or 2.4 V,
VB = –1.4 V,
VA = 1.2 V
VA = 1.2 V
VA = VB,
–1.4 ≤ VA ≤ 3.8 V
VA = 3.8 V,
VA = 0 V or 2.4 V,
VB = 1.2 V, VCC ≤ 1.5 V
VB = 1.2 V, VCC ≤ 1.5 V
VB = 1.2 V, VCC ≤ 1.5 V
VA = 1.2 V, VCC ≤ 1.5 V
VA = 1.2 V, VCC ≤ 1.5 V
VA = 1.2 V, VCC ≤ 1.5 V
–32
0
–1.4 ≤ VA ≤ 3.8 V, VCC ≤ 1.5 V
–4
4
VA = –1.4 V,
VB = 3.8 V,
VB = 0 V or 2.4 V,
VB = –1.4 V,
VA = VB,
0
32
–20
20
–32
0
0
32
–20
20
–32
0
–4
4
0
32
–20
20
–32
0
0
32
–20
20
UNIT
µA
µA
µA
µA
µA
µA
VA = 0.4 sin(2E8πt) +0.5, VB = 1.2 V
3
pF
VB = 0.4 sin(2E8πt) +0.5, VA = 1.2 V
3
pF
† All typical values are at 25°C and with a 3.3-V supply voltage.
6
MIN
POST OFFICE BOX 655303
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SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
1.6
2.3
4.1
ns
Propagation delay time, high-to-low-level output
1.6
2.3
4.1
ns
tr
tf
Differential output signal rise time
1.5
2
3
ns
2
3
ns
tsk(p)
tsk(pp)
Pulse skew (|tPHL –- tPLH|)
tPZH
tPZL
Propagation delay time, high-impedance-to-high-level output
1.5
Propagation delay time, high-impedance-to-low-level output
1.5
tPHZ
tPLZ
Propagation delay time, high-level-to-high-impedance output
See Figure 5
Differential output signal fall time
1.5
30
Part-to-part skew (see Note 4)
See Figure 6
Propagation delay time, low-level-to-high-impedance output
ps
900
ps
3.7
6.5
ns
3.7
6.5
ns
1.3
3.5
6.8
ns
1.8
3.5
6.1
ns
tjit(per)
Period jitter, rms (1 standard deviation) (see Notes 5 and 6)
50-MHz clock input
(see Figure 8)
tjit(cc)
Cycle-to-cycle jitter, peak (see Notes 5 and 6)
50-MHz clock input
(see Figure 8)
180
ps
tjit(pp)
Peak-to-peak jitter, (see Notes 5, 7, and 8)
100 Mbps 215–1 PRBS
input (see Figure 8)
210
ps
23
ps
† All typical values are at 25°C and with a 3.3-V supply voltage.
NOTES: 4. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5. Jitter parameters are based on design and characterization. Stimulus system jitter of 11 ps tjit(per), 43 ps tjit(cc), or 54 ps tjit(pp) have
been subtracted from the values.
6. Input voltage = 0 V to VCC, tr = tf ≤ 1 ns (20% to 80%), measured over 30k samples.
7. Input voltage = 0 V to VCC, tr = tf ≤ 1 ns (20% to 80%), measured over 100k samples.
8. Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
3
5
6.7
ns
Propagation delay time, high-to-low-level output
3
4.6
6.7
ns
tsk(p)
tsk(pp)
Pulse skew (|tPHL –- tPLH|)
1.5
ns
tr
tf
Output signal rise time
0.8
1.4
2
ns
Output signal fall time
0.8
1.5
2
ns
tPLH
tPHL
Propagation delay time, low-to-high-level output
3.4
5.8
9
ns
Propagation delay time, high-to-low-level output
3.4
5.4
9
ns
tsk(p)
tsk(pp)
Pulse skew (|tPHL –- tPLH|)
tr
tf
Output signal rise time
1
Output signal fall time
400
pF See Figure 10
CL = 5 pF,
Part-to-part skew (see Note 9)
ps
400
CL = 15 pF,
pF See Figure 10
Part-to-part skew (see Note 9)
tPHZ
Propagation delay time, high-level-to-high-impedance
output
tPLZ
Propagation delay time, low-level-to-high-impedance
output
ps
2.5
ns
2
2.6
ns
1
1.4
2.6
ns
4.5
6
15
ns
2
3.4
5
ns
3.5
9.8
15
ns
4
8.7
15
ns
See Figure 11
tPZH
Propagation delay time, high-impedance-to-high-level
output
tPZL
Propagation delay time, high-impedance-to-low-level
output
Period jitter, rms (1 standard deviation)
(see Notes 10 and 11)
50 MHz clock in
50-MHz
input
ut
(see Figure 12)
Type 1
10
tjit(per)
Type 2
10
93
Cycle to cycle jitter
Cycle-to-cycle
jitter, peak (see Notes 10 and 11)
50 MHz clock in
50-MHz
input
ut
(see Figure 12)
Type 1
tjit(cc)
Type 2
86
850
Peak to peak jitter,
Peak-to-peak
jitter (see Notes 10,
10 12,
12 and 13)
100 Mbps
Mb s 215–1
1 PRBS
input (see Figure 12)
Type 1
tjit(pp)
Type 2
790
ps
ps
ps
† All typical values are at 25°C and with a 3.3-V supply voltage.
NOTES: 9. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
10. Jitter parameters are based on design and characterization. Stimulus system jitter of 11 ps tjit(per), 43 ps tjit(cc), or 54 ps tjit(pp) have
been subtracted from the values.
11. Differential input voltage = 250 mVp–p (Type 1) or 500 mVp–p (Type 2), VCM = 1 V, tr = tf ≤ 1 ns (20% to 80%), measured over 30k
samples.
12. Differential input voltage = 250 mVp–p (Type 1) or 500 mVp–p (Type 2), VCM = 1 V, tr = tf ≤ 1 ns (20% to 80%), measured over 100k
samples.
13. Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
8
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SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
VCC
IA or IY
A/Y
II
D
IB or IZ
VAB or VYZ
VA or VY
B/Z
VI
VOS
VB or VZ
VA + VB
2
VY + VZ
2
or
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
A/Y
VAB or VYZ
D
+
_
49.9 Ω
B/Z
–1 V ≤ Vtest ≤ 3.4 V
3.32 kΩ
NOTE: All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
A/Y
A/Y
≈ 1.3 V
B/Z
≈ 0.7 V
24.9 Ω ±1%
D
VOS(PP)
CL
B/Z
24.9 Ω ±1%
2 pF
VOS
VOS(SS)
VOS
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1 ns, pulse repetition rate (PRR) = 0.25 Mpps,
pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOS(PP)
is made on test equipment with a –3-dB bandwidth of at least 1 GHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A/Y
IOS
0 V or VCC
+
B/Z
VTest
–1 V or 3.4 V
–
Figure 4. Driver Short-Circuit Test Circuit
POST OFFICE BOX 655303
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9
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
A/Y
CL
0.5 pF
Output
D
B/Z
49.9 Ω ±1%
(Metal Film Surface Mount)
VCC
VCC/2
Input
0V
tPLH
tPHL
VSS
0.9VSS
VP(H)
Output
0V
VP(L)
0.1V
SS
0 VSS
tf
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1 ns, pulse repetition rate (PRR) = 1 Mpps,
pulse width = 0.5 ±0.05 µs. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
24.9 Ω ±1%
(2 Places)
A/Y
CL
0 V or VCC
0.5 pF
Output
B/Z
+
1V
DE
VCC
VCC/2
0V
DE
tPZH
tPHZ
∼ 0.6 V
0.1 V
0V
Output With
D at VCC
Output With
D at 0 V
tPZL
tPLZ
0V
–0.1 V
∼ –0.6 V
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1 ns, pulse repetition rate (PRR) = 0.25 Mpps,
pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 6. Driver Enable and DIsable Time Circuit and Definitions
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
A/Y
0 V or VCC
B/Z
VA, VB, VY or VZ
1.62 kΩ
C
Figure 7. Maximum Steady-State Output Voltage Test Circuit
OUTPUT
0 V DIFF
VCC
CLOCK
INPUT
VCC/2
0V
1/f0
VA –VB or VY –VZ
tc(n)
tc(n+1)
tjit(cc) = | tc(n) – tc(n+1) |
Period Jitter
IDEAL
OUTPUT 0 V
VCC
PRBS INPUT
VA –VB or VY –VZ
0V
Peak to Peak Jitter
ACTUAL
OUTPUT 0 V
VA –VB or VY –VZ
NOTES: A.
B.
C.
D.
VCC/2
1/f0
VA – VB or VY – VZ
OUTPUT 0 V Diff
tc(n)
tjit(per) = tc(n) –1/f0
tjit(pp)
All input pulses are supplied by an Agilent 8304A Stimulus System.
The measurement is made on a TEK TDS6604 running TDSJIT3 application software
Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
Peak-to-peak jitter is measured using a 200Mbps 215–1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
IA
A
IB
VCM
(VA + VB)/2
VID
R
IO
B
VO
VA
VB
Figure 9. Receiver Voltage and Current Definitions
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
Table 1. Type-1 Receiver Input Threshold Test Voltages
APPLIED VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
RECEIVER OUTPUT
VA
3.425 V
VB
3.375 V
VID
50 mV
VCM
3.4 V
VO
H
3.375 V
3.425 V
–50 mV
3.4 V
L
–0.975 V
–1.025 V
50 mV
–1.0 V
H
–1.025 V
–0.975 V
–50 mV
–1.0 V
L
3.800 V
3.000 V
800 mV
3.4 V
H
3.000 V
3.800 V
–800 mV
3.4 V
L
–0.600 V
–1.400 V
800 mV
–1.0 V
H
–1.400 V
–0.600 V
–800 mV
–1.0 V
L
NOTE: H= high level, L = low level. Output state assumes receiver is enabled (RE is Low).
Table 2. Type-2 Receiver Input Threshold Test Voltages
APPLIED VOLTAGES
VA
3.475 V
VB
3.325 V
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON–
MODE INPUT VOLTAGE
RECEIVER OUTPUT
VID
150 mV
VCM
3.4 V
VO
H
3.425 V
3.375 V
50 mV
3.4 V
L
–0.925 V
–1.075 V
150 mV
–1.0 V
H
–0.975 V
–1.025 V
50 mV
–1.0 V
L
3.800 V
3.000 V
800 mV
3.4 V
H
3.000 V
3.800 V
–800 mV
3.4 V
L
–0.600 V
–1.400 V
800 mV
–1.0 V
H
–1.400 V
–0.600 V
–800 mV
–1.0 V
L
NOTE: H= high level, L = low level. Output state assumes receiver is enabled (RE is Low).
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
R1
453 Ω
VID
CL
VA
R2
49.9 Ω
VO
VB
VA
1.1 V
VA
1.2 V
VB
0.9 V
VB
0.8 V
0.2 V
VID
0V
0.4 V
VID
0.1 V
–0.2 V
tpHL
0.1 VOH
0.1 VCC/2
90%
VO
–0.4 V
tPHL
tpLH
10%
tf
0.1 VOL
tPLH
0.1 VOH
0.1 VCC/2
90%
VO
10%
tr
tf
0.1 VOL
tr
Type 1
Type 2
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1 ns, pulse repetition rate (PRR) = 1 Mpps,
pulse width = 0.5 ±0.05 µs.
B. Resistors are 1% tolerance, metal film, and surface mount.
C. CL is 20% tolerance, low-loss ceramic, and surface mount.
D. R1 and CL are located within 2 cm of the D.U.T.
E. R2 is located within 15 cm of the D.U.T.
Figure 10. Receiver Timing Test Circuit and Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
1.2 V
B
R
A
Inputs
RE
CL
5 pF
500 Ω ±1%
Output
+
_
Vtest
VCC
VTEST
1V
A
Inputs
VCC
VCC/2
0V
RE
tPZL
Output
tPLZ
VCC
VCC/2
VOL +0.5 V
VOL
R
VTEST
0V
1.4 V
A
Inputs
VCC
VCC/2
0V
RE
tPZH
Output
tPHZ
R
VOH
VOH –0.5 V
VCC/2
0V
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1 ns, pulse repetition rate (PRR) = 0.25 Mpps,
pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
CLOCK INPUT
VA – VB
1/f0
INPUTS
VA – VB
VIC
0.25 V – Type 1 1 V
0.5 V – Type 2
VOH
OUTPUT
VCC/2
VOL
tc(n)
Period Jitter
IDEAL VOH
OUTPUT V /2
CC
VOL
tjit(cc) = | tc(n) – tc(n+1) |
VA
PRBS INPUT
1/f0
VB
V
ACTUAL OH
OUTPUT VCC/2
VOL
NOTES: A.
B.
C.
D.
tc(n+1)
Peak to Peak Jitter
VOH
OUTPUT V /2
CC
VOL
tc(n)
tjit(per) = tc(n) –1/f0
tjit(pp)
All input pulses are supplied by an Agilent 8304A Stimulus System.
The measurement is made on a TEK TDS6604 running TDSJIT3 application software
Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
Peak-to-peak jitter is measured using a 200Mbps 215–1 PRBS input.
Figure 12. Receiver Jitter Measurement Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
t PLH – Driver Low-to-High Propagation Delay – ns
DRIVER LOW-TO-HIGH PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
2.5
See Figure 5
VCC = 3 V
2.4
VCC = 3.3 V
VCC = 3.6 V
2.3
2.2
2.1
–50
t PHL – Driver High-to-Low Propagation Delay – ns
TYPICAL CHARACTERISTICS
DRIVER HIGH-TO-LOW PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
2.5
See Figure 5
VCC = 3 V
2.4
VCC = 3.3 V
2.3
VCC = 3.6 V
2.2
2.1
0
50
TA – Free-Air Temperature – °C
100
–50
0
50
TA – Free-Air Temperature – °C
Figure 14
RECEIVER LOW-TO-HIGH PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
5.5
CL = 5 pF
See Figure 9
VCC = 3 V
VCC = 3.3 V
5
VCC = 3.6 V
4.5
4
–50
0
50
TA – Free-Air Temperature – °C
100
t PHL – Receiver High-to-Low Propagation Delay – ns
t PLH – Receiver Low-to-High Propagation Delay – ns
Figure 13
RECEIVER HIGH-TO-LOW PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
5.5
CL = 5 pF
See Figure 9
VCC = 3 V
5
VCC = 3.3 V
4.5
VCC = 3.6 V
4
–50
Figure 15
16
100
0
50
TA – Free-Air Temperature – °C
Figure 16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
5
15
TA = 25 °C
VCC = 3.3 V
I OH – Driver High-Level Output Current – mA
I OL– Driver Low-Level Output Current – mA
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
10
5
0
–5
–1
1
2
3
VOL – Low-Level Output Voltage – V
–5
–10
–15
–1
4
0
1
2
Figure 18
RECEIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
RECEIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
20
IOH – Receiver High-Level Output Current – mA
TA = 25 °C
VCC = 3.3 V
80
60
40
20
0
0.5
1
1.5
2
2.5
3
4
3
VOH – High-Level Output Voltage – V
100
0
0
Figure 17
120
I OL– Receiver Low-Level Output Current – mA
0
TA = 25 °C
VCC = 3.3 V
3.5
4
VOL – Low-Level Output Voltage – V
TA = 25 °C
VCC = 3.3 V
0
–20
–40
–60
–80
0
0.5
1
1.5
2
2.5
3
3.5
VOH – High-Level Output Voltage – V
Figure 19
4
Figure 20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
AVERAGE DRIVER SUPPLY CURRENT
vs
FREQUENCY
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
17
I CC – Average Driver Supply Current – mA
Differential Output Voltage – V
2
1.6
1.2
0.8
0.4
VCC = 3.3 V
TA = 25°C
0
0
50% Duty Cycle
RL = 50 Ω
TA = 25°C
See Figure 5
16
VCC = 3.3 V
15
VCC = 3 V
14
13
Note: 100 MHz = 200 Mbps
12
2
4
6
8
IO – Output Current – mA
10
0
12
25
t jit(per) – Driver Period Jitter (1 Sigma) – ps
I CC – Average Receiver Supply Current – mA
50
50% Duty Cycle
RL = 500 Ω
CL = 5 pF
TA = 25°C
See Figure 9
VCC = 3.6 V
VCC = 3.3 V
10
VCC = 3 V
5
Note: 100 MHz = 200 Mbps
25
50
75
100
VCC = 3.3 V,
TA = 25°C,
Input = Clock
40
30
20
10
0
10
f – Frequency – MHz
Figure 23
18
100
ADDED DRIVER PERIOD JITTER (1 SIGMA)
vs
CLOCK FREQUENCY
20
0
75
Figure 22
AVERAGE RECEIVER SUPPLY CURRENT
vs
FREQUENCY
0
50
f – Frequency – MHz
Figure 21
15
VCC = 3.6 V
20
30
40
f – Clock Frequency – MHz
Figure 24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
50
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
ADDED TYPE 1 RECEIVER PERIOD JITTER (1 SIGMA)
vs
CLOCK FREQUENCY
ADDED TYPE 2 RECEIVER PERIOD JITTER (1 SIGMA)
vs
CLOCK FREQUENCY
25
t jit(per) – Receiver Period Jitter (1 Sigma) – ps
t jit(per) – Receiver Period Jitter (1 Sigma) – ps
25
VCC = 3.3 V,
TA = 25°C,
Input = Clock,
VID = 250 mV
20
VIC = –0.5 V
VIC = 3 V
15
10
VIC = 1 V
5
0
10
20
30
40
f – Clock Frequency – MHz
20
VCC = 3.3 V,
TA = 25°C,
Input = Clock,
VID = 500 mV
15
VIC = 1 V
10
VIC = 3 V
5
0
10
50
20
ADDED TYPE 1 RECEIVER CYCLE-TO-CYCLE
JITTER (PEAK)
vs
CLOCK FREQUENCY
t jit(cc) – Receiver Cycle-to-Cycle Jitter (Peak) – ps
t jit(cc) – Driver Cycle-to-Cycle Jitter (Peak) – ps
50
Figure 26
ADDED DRIVER CYCLE-TO-CYCLE JITTER (PEAK)
vs
CLOCK FREQUENCY
250
VCC = 3.3 V,
TA = 25°C,
Input = Clock
150
100
50
0
10
40
f – Clock Frequency – MHz
Figure 25
200
30
VIC = –0.5 V
20
30
40
f – Clock Frequency – MHz
50
250
200
VCC = 3.3 V,
TA = 25°C,
Input = Clock,
VID = 250 mV
VIC = –0.5 V
150
VIC = 3 V
100
VIC = 1 V
50
0
10
20
30
40
f – Clock Frequency – MHz
50
Figure 28
Figure 27
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
ADDED DRIVER PEAK-TO-PEAK JITTER
vs
DATA RATE
250
250
t jit(pp) – Driver Peak-to-Peak Jitter – ps
t jit(cc) – Receiver Cycle-to-Cycle Jitter (Peak) – ps
ADDED TYPE 2 RECEIVER CYCLE-TO-CYCLE
JITTER (PEAK)
vs
CLOCK FREQUENCY
VCC = 3.3 V,
TA = 25°C,
Input = Clock,
VID = 500 mV
200
150
VIC = 1 V
VIC = –0.5 V
100
VIC = 3 V
50
0
10
20
30
40
f – Clock Frequency – MHz
VCC = 3.3 V,
TA = 25°C,
Input = PRBS(215 – 1)
200
150
100
50
0
20
50
40
Figure 29
100
ADDED TYPE 2 RECEIVER PEAK-TO-PEAK JITTER
vs
DATA RATE
2000
2000
VCC = 3.3 V,
TA = 25°C,
Input = PRBS(215 – 1),
VID = 250 mV
1600
t jit(pp) – Receiver Peak-to-Peak Jitter – ps
t jit(pp) – Receiver Peak-to-Peak Jitter – ps
80
Figure 30
ADDED TYPE 1 RECEIVER PEAK-TO-PEAK JITTER
vs
DATA RATE
1200
800
400
VCC = 3.3 V,
TA = 25°C,
Input = PRBS(215 – 1),
VID = 500 mV
1600
1200
800
400
0
0
20
40
60
80
100
20
Data Rate – Mbps
40
60
Data Rate – Mbps
Figure 32
Figure 31
20
60
Data Rate – Mbps
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
80
100
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
APPLICATION INFORMATION
Type-1 and Type-2 receivers
The M-LVDS standard defines Type-1 and Type-2 receivers. Type-1 receivers include no provisions for failsafe
and have their differential input voltage thresholds near zero volts. Type-2 receivers have their differential input
voltage thresholds offset from zero volts to detect the absence of a voltage difference. Type-1 receivers
maximize the differential noise margin and are intended for maximum signaling rates. Type-2 receivers are
intended for control signals and slower signaling rates. The impact on receiver output by the offset input can
be seen in Table 3 and Figure 33.
Table 3. M-LVDS Receiver Input Voltage Threshold Requirements
VID – Differential Input Voltage – mV
200
Receiver Type
Output Low
Output High
1
–2.4 V ≤ VID ≤ –0.05 V
0.05 V ≤ VID ≤ 2.4 V
2
–2.4 V ≤ VID ≤ 0.05 V
0.15 V ≤ VID ≤ 2.4 V
Type 1
Type 2
High
150
100
High
50
0
Low
–50
–100
Low
Transition Regions
Figure 33. Receiver Differential Input Voltage Showing Transition Region
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
APPLICATION INFORMATION
comparison of M-LVDS with RS-485
RS-485 applications are similar to M-LVDS. The two standards define balanced multipoint systems with some
basic architecture changes due to the different applications. Table 4 gives a high-level comparison of the two
different technologies.
Table 4. Comparison Between M-LVDS and RS-485 Standards
Number of Loads
Differential Voltage
Range
Common-Mode
Voltage Range
Maximum Signaling
Rate (Mbps)
Receiver Minimum
Threshold
RS-485
32
1.5 V to 5 V
–7 V to 12 V
50 Mbps
±200 mV
M-LVDS
32
480 mV to 650 mV
–1 V to 3.4 V
500 Mbps
±50 mV
It can be seen that with the greater differential output voltage and common-mode voltage range of the
RS-485-type device, it can handle longer signaling distances where M-LVDS offers ten times the signaling rate
of RS-485.
SN65MLVD200
SN65MLVD200
RT
RT
Up to 32
Transceivers
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.
Figure 34. Typical Application Circuit
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65MLVD200D
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF200
SN65MLVD200DR
NRND
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF200
SN65MLVD202D
NRND
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MLVD202
SN65MLVD204D
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF204
SN65MLVD204DR
NRND
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MF204
SN65MLVD205D
NRND
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MLVD205
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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