SN74ABT2827DWR

SN54ABT2827, SN74ABT2827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS648A – DECEMBER 1995 – REVISED JANUARY 1997 D D D D description These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all ten outputs are in the high-impedance state. The ’ABT2827 provide true data at their outputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. SN54ABT2827 . . . JT PACKAGE SN74ABT2827 . . . DW OR NT PACKAGE (TOP VIEW) OE1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 OE2 SN54ABT2827 . . . FK PACKAGE (TOP VIEW) A2 A1 OE1 NC VCC Y1 Y2 D Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Package Options Include Plastic Small-Outline (DW) Package, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs 4 A3 A4 A5 NC A6 A7 A8 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y3 Y4 Y5 NC Y6 Y7 Y8 A9 A10 GND NC OE2 Y10 Y9 D NC – No internal connection The SN54ABT2827 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT2827 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright  1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT2827, SN74ABT2827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS648A – DECEMBER 1995 – REVISED JANUARY 1997 FUNCTION TABLE INPUTS OE2 L L L L L L H H H X X Z X H X Z logic symbol† 1 OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 logic diagram (positive logic) & OE1 EN 13 2 A OUTPUT Y OE1 1 OE2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 Y1 A1 1 13 2 23 Y1 Y2 Y3 To Nine Other Channels Y4 Y5 Y6 Y7 Y8 Y9 Y10 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT2827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT2827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT2827, SN74ABT2827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS648A – DECEMBER 1995 – REVISED JANUARY 1997 recommended operating conditions (see Note 3) SN54ABT2827 SN74ABT2827 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –12 Low-level output current 12 12 mA ∆t/∆v Input transition rise or fall rate 5 5 ns/V 85 °C High-level input voltage 2 2 0.8 Input voltage 0 TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. –55 125 V 0.8 0 –40 V VCC –12 V V mA electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –1 mA VCC = 5 V, IOH = –1 mA IOH = –3 mA VCC = 4 4.5 5V VOL Vhys VCC = 4.5 V IOH = –12 mA IOL = 12 mA II IOZH VCC = 0 to 5.5 V, VCC = 5.5 V, VI = VCC or GND VO = 2.7 V VCC = 5.5 V, VCC = 0, VO = 0.5 V VI or VO ≤ 4.5 V ICEX IO§ VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, Outputs high ∆ICC¶ Ci Co TA = 25°C TYP† MAX SN54ABT2827 –1.2 –1.2 MIN MAX SN74ABT2827 MIN –1.2 2.5 2.5 3 3 3 2.4 2.4 2.4 2 MAX VCC = 5.5 V, IO = 0, VI = VCC or GND VCC = 5.5 V, O input One i at 3.4 V V, Other in inputs uts at VCC or GND VO = 2.5 V Outputs high 2 V 2 0.8 0.8 ±1 10‡ ±1 µA 10 ±1 10‡ –10 –10‡ µA ±100 µA 50 –225‡ µA 50 –225‡ –50 50 –225‡ –50 µA mA µA Outputs low 35 250 40‡ Outputs disabled 80 250 250 250 µA Outputs enabled 1.5 1.5 1.5 mA Outputs disabled 50 50 50 µA Control inputs 1.5 1.5 1.5 mA VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 80 V mV ±100 –140 V 0.8 –10‡ –50 UNIT 2.5 100 IOZL Ioff ICC MIN 250 40‡ 250 40‡ mA 4 pF 8.5 pF † All typical values are at VCC = 5 V, TA = 25°C. ‡ This data sheet limit may vary among suppliers. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT2827, SN74ABT2827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS648A – DECEMBER 1995 – REVISED JANUARY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y PARAMETER VCC = 5 V, TA = 25°C SN54ABT2827 MIN TYP MAX MIN MAX MIN MAX 1.1 3.3 5.1 1.1 5.6 1.1 5.5 1.1 2.7 4.5 1.1 5.2 1.1 5.1 1 4 5.9 1 6.8 1 6.7 1 4.2 6.8 1 8 1 7.8 2 5.3 6.7 2 7.4 2 7.2 1.3 4.8 7.2 1.3 8.5 1.3 7.5 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 SN74ABT2827 • DALLAS, TEXAS 75265 UNIT ns ns ns SN54ABT2827, SN74ABT2827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS648A – DECEMBER 1995 – REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input 1.5 V 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 3V Output Control 1.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 n D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74ABT2827DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT2827 SN74ABT2827DWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT2827 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of