SN74ABT843DWR

SN54ABT843, SN74ABT843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS197D – FEBRUARY 1991 – REVISED MAY 1997 D D D D State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs SN54ABT843 . . . JT OR W PACKAGE SN74ABT843 . . . DB, DW, OR NT PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND description The ’ABT843 9-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q PRE LE 2D 1D SN54ABT843 . . . FK PACKAGE (TOP VIEW) 4 3D 4D 5D NC 6D 7D 8D 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 3Q 4Q 5Q NC 6Q 7Q 8Q 9D CLR GND NC LE PRE 9Q The nine transparent D-type latches provide true data at the outputs. 1 OE NC VCC 1Q 2Q D NC – No internal connection OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT843 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT843 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT843, SN74ABT843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS197D – FEBRUARY 1991 – REVISED MAY 1997 FUNCTION TABLE INPUTS PRE CLR OE LE D OUTPUT Q L X L X X H H L L X X L H H L H L L H H L H H H H H L L X Q0 X X H X X Z logic symbol† OE 1 14 PRE 11 CLR LE 1D 2D 3D 4D 5D 6D 7D 8D 9D 13 2 EN S2 R C1 1D 2 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, and W packages. 2 23 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q SN54ABT843, SN74ABT843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS197D – FEBRUARY 1991 – REVISED MAY 1997 logic diagram (positive logic) OE PRE CLR LE 1 14 11 13 S2 C1 1D 2 23 1Q 1D R To Eight Other Channels Pin numbers shown are for the DB, DW, JT, NT, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range , VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT843 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT843 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT843, SN74ABT843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS197D – FEBRUARY 1991 – REVISED MAY 1997 recommended operating conditions (see Note 3) SN54ABT843 SN74ABT843 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –24 Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate 5 5 ns/V 85 °C High-level input voltage 2 2 V 0.8 Input voltage 0 TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. –55 125 0.8 0 V VCC –32 –40 V V mA electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL Vhys II IOZH‡ IOZL‡ Ioff ICEX IO§ VCC = 4 4.5 5V TA = 25°C TYP† MAX SN54ABT843 MIN –1.2 MAX SN74ABT843 MIN –1.2 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 IOH = –32 mA IOL = 48 mA 2* 0.55* 0.55 100 VI = VCC or GND VO = 2.7 V VCC = 5.5 V, VCC = 0, VO = 0.5 V VI or VO ≤ 4.5 V VCC = 5.5 V, VCC = 5.5 V, VO = 5.5 V VO = 2.5 V 5 5 V, V IO = Open, O VCC = 5.5 VI = VCC or GND ∆ICC¶ VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V V mV ±1 ±1 ±1 µA 10 10 10 µA –10 –10 –10 µA ±100 Outputs high 50 –50 V 2 0.55 IOL = 64 mA VCC = 5.5 V, VCC = 5.5 V, UNIT V 2 50 –50 –180 –50 ±100 µA 50 µA –140 –180 Outputs high 1 250 250 250 µA Outputs low 24 34 34 34 mA Outputs disabled 0.5 250 250 250 µA 1.5 1.5 1.5 mA POST OFFICE BOX 655303 –180 mA 4 pF 7 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ The parameters IOZH and IOZL include the input leakage current. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 MAX –1.2 2.5 ICC Co MIN • DALLAS, TEXAS 75265 SN54ABT843, SN74ABT843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS197D – FEBRUARY 1991 – REVISED MAY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figures 1 and 2) VCC = 5 V, TA = 25°C MIN tw Pulse duration th Hold time, time data after LE↓ MAX MIN 5.5 5.5 5.5 PRE low 4.5 4.5 4.5 3.3 3.3 3.4 2.5 2.5 2.5 Data before LE↓ Setup time MIN SN74ABT843 CLR low LE low tsu MAX SN54ABT843 Low 3 3 3 PRE inactive High 1.6 1.6 1.6 CLR inactive 2 2 2 1 1.5† 1 2.3† 1 1.5† High Low UNIT MAX ns ns ns † This data sheet limit may vary among suppliers. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figures 1 and 2) FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPLH tPHL PRE Q tPLH tPHL CLR Q tPZH tPZL OE Q tPHZ tPLZ OE Q PARAMETER VCC = 5 V, TA = 25°C SN54ABT843 MIN 1.2† TYP MAX MIN 1.2† MAX 3.8 5.2 1.5† 1.7† 3.4 6.3 7.3 5.6 1.5† 1.7† 4.4 SN74ABT843 MIN 1.2† MAX 6.7† 8.3 1.5† 1.7† 7.2 7.2† 7.2 1.9† 6.9 7.4 8 5.7† 7.8 1.9† 4.1 6.3 1.3† 2.2 2.1† 2† 5 6.2 6.5 4.4 6.3 2.2 2.1† 2† 8.3 4.1 7.6 2.2 2.1† 2† 1.9† 4.5 1.9† 8.1 1.9† 1 3.4 6.8 4.5† 1 6.4 1 2 2.4† 4.3 5.7† 6.6 4.9 6.2 2 2.4† 7.3 2 2.4† 6.3 1.5† 7 1.5† 1.5† 4.2 7.5 7.2 7.1 6.5 6.8 5.9† UNIT ns ns ns ns ns ns † This data sheet limit may vary among suppliers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT843, SN74ABT843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS197D – FEBRUARY 1991 – REVISED MAY 1997 recovery-time waveform 3V PRE, CLR 1.5 V 1.5 V 0V tw(L) tREC 3V LE 1.5 V 0V tPLH 3V Q 1.5 V 0V 3V Q 1.5 V 0V tPHL Figure 1. CLR and PRE Pulse Duration, CLR and PRE to Output Delay, and CLR and PRE to Latch-Enable Recovery Time 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT843, SN74ABT843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS197D – FEBRUARY 1991 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V Data Input 0V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 3V 1.5 V Input Output Control 1.5 V 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9571201QLA ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9571201QL A SNJ54ABT843JT SN74ABT843DBR ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AB843 Samples SN74ABT843DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT843 Samples SN74ABT843DWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT843 Samples SNJ54ABT843JT ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9571201QL A SNJ54ABT843JT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of