SN74AC564N


       
 
 
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003 D D SN54AC564 . . . J OR W PACKAGE SN74AC564 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9 ns at 5 V 3-State Inverting Outputs Drive Bus Lines Directly Full Parallel Access for Loading Flow-Through Architecture to Optimize PCB Layout OE 1D 2D 3D 4D 5D 6D 7D 8D GND description/ordering information The ’AC564 devices are octal D-type edge-triggered flip-flops that feature inverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK 2D 1D OE VCC SN54AC564 . . . FK PACKAGE (TOP VIEW) On the positive transition of the clock (CLK) input, the Q outputs are set to the inverse logic levels set up at the data (D) inputs. 3D 4D 5D 6D 7D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND CLK 8Q 7Q A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. 1Q D D D D OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION PDIP − N SN74AC564N Tube SN74AC564DW Tape and reel SN74AC564DWR SOP − NS Tape and reel SN74AC564NSR AC564 SSOP − DB Tape and reel SN74AC564DBR AC564 Tube SN74AC564PW Tape and reel SN74AC564PWR CDIP − J Tube SNJ54AC564J SNJ54AC564J CFP − W Tube SNJ54AC564W SNJ54AC564W LCCC − FK Tube SNJ54AC564FK SNJ54AC564FK TSSOP − PW −55°C −55 C to 125 125°C C TOP-SIDE MARKING Tube SOIC − DW −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA SN74AC564N AC564 AC564 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated 


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SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H L L ↑ L H L H or L X Q0 H X X Z logic diagram (positive logic) OE CLK 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

       
 
 
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) SN54AC564 VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL VI VO IOH IOL ∆t/∆v MIN MAX 2 6 Input voltage Low-level output current 2 6 3.15 3.15 3.85 3.85 0 High-level output current MAX 2.1 0 Output voltage MIN 2.1 VCC = 4.5 V VCC = 5.5 V Low-level input voltage SN74AC564 0.9 1.35 1.35 1.65 1.65 0 0 VCC VCC VCC = 3 V VCC = 4.5 V −12 −12 −24 −24 VCC = 5.5 V VCC = 3 V −24 −24 12 12 VCC = 4.5 V VCC = 5.5 V 24 24 24 24 8 8 Input transition rise or fall rate V V 0.9 VCC VCC UNIT V V V mA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −50 µA VOH VOL IOH = −12 mA VCC MIN TA = 25°C TYP MAX SN54AC564 MIN MAX SN74AC564 MIN 3V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 3V 2.56 2.4 2.46 MAX UNIT V 4.5 V 3.86 3.7 3.76 IOH = −24 mA 5.5 V 4.86 4.7 4.76 3V 0.1 0.1 0.1 IOL = 50 µA 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 5.5 V ±0.1 ±1 ±1 µA 5.5 V ±0.5 ±5 ±5 µA 4 80 40 µA IOL = 12 mA IOL = 24 mA II IOZ VI = VCC or GND VO = VCC or GND ICC Ci VI = VCC or GND, VI = VCC or GND IO = 0 5.5 V 5V 4.5 V pF   1 %'(#&% !%!$(% )("! % $ '(#&2$ ( $0% )&$ ' $2$+)#$%, &(&!$(! && &% $( )$!'!&% &($ $0% 0&+, $-& %("#$% ($$(2$ $ (0  !&%0$ ( !%%"$ $$ )("! ." %!$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

       
 
 
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock tw Clock frequency tsu th Setup time, data before CLK↑ SN54AC564 MIN 75 Pulse duration, CLK high or low Hold time, data after CLK↑ SN74AC564 MAX MIN 55 MAX 60 UNIT MHz 6 7.5 7 ns 2.5 4.5 3 ns 2 2.5 2 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54AC564 MIN 95 SN74AC564 MAX MIN Clock frequency Pulse duration, CLK high or low 4 5 5 ns tsu th Setup time, data before CLK↑ 2 3.5 2.5 ns Hold time, data after CLK↑ 2 2.5 2 ns PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX CLK Q OE Q OE Q fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN Q OE Q OE Q range, MAX MIN MAX 60 8.1 14 1 16.5 3.5 15.5 3.5 8.2 12.5 1 15 3.5 14 2.5 7.2 11.5 1 13 2.5 12.5 3 7.7 11 1 12.5 3.5 12 4 8.6 12.5 1 14 4.5 13.5 2 7.3 9.5 1 10.5 2.5 10.5 TA = 25°C MIN TYP MAX temperature SN54AC564 MIN UNIT MHz 3.5 free-air MHz SN74AC564 55 95 CLK temperature SN54AC564 75 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER free-air 85 UNIT fclock tw switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) 85 MAX ns ns ns range, SN74AC564 MAX 85 MIN MAX 85 UNIT MHz 2 4.9 10.5 1.5 11.5 2 11.5 2 5 9.5 1.5 10.5 2 10.5 2 5.1 9 1.5 9.5 2 9.5 1.5 5.2 8.5 1.5 9.5 2 9.5 2 5.7 10.5 1.5 11.5 2 11.5 1.5 4.8 8 1.5 9 1.5 9 ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF,   1 %'(#&% !%!$(% )("! % $ '(#&2$ ( $0% )&$ ' $2$+)#$%, &(&!$(! && &% $( )$!'!&% &($ $0% 0&+, $-& %("#$% ($$(2$ $ (0  !&%0$ ( !%%"$ $$ )("! ." %!$, 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP UNIT 50 pF 

       
 
 
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input th 50% VCC VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Output Control (low-level enabling) VCC Input 50% VCC 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) VOH 50% VCC VOL 50% VCC Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS ≈VCC VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC 0V tPZL tPHL tPHL Out-of-Phase Output 0V VCC 50% VCC 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AC564DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC564 SN74AC564DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC564 SN74AC564DWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC564 SN74AC564N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74AC564N SN74AC564PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC564 SN74AC564PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC564 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of