SN74AC573N

SN54AC573, SN74AC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 SN54AC573 . . . J OR W PACKAGE SN74AC573 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9 ns at 5 V 3-State Outputs Drive Bus Lines Directly OE 1D 2D 3D 4D 5D 6D 7D 8D GND description/ordering information These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D Inputs. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE 2D 1D OE VCC SN54AC573 . . . FK PACKAGE (TOP VIEW) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND LE 8Q 7Q 3D 4D 5D 6D 7D 1Q D D D D OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION PDIP − N SN74AC573N Tube SN74AC573DW Tape and reel SN74AC573DWR SOP − NS Tape and reel SN74AC573NSR AC573 SSOP − DB Tape and reel SN74AC573DBR AC573 Tube SN74AC573PW Tape and reel SN74AC573PWR CDIP − J Tube SNJ54AC573J SNJ54AC573J CFP − W Tube SNJ54AC573W SNJ54AC573W LCCC − FK Tube SNJ54AC573FK SNJ54AC573FK TSSOP − PW −55°C 55 C to 125 125°C C † TOP-SIDE MARKING Tube SOIC − DW −40°C 40 C to 85°C 85 C ORDERABLE PART NUMBER PACKAGE† TA SN74AC573N AC573 AC573 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AC573, SN74AC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to + 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through, VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AC573, SN74AC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) SN54AC573 VCC Supply voltage VCC = 3 V VIH High-level High level input voltage MIN MAX 2 6 Low-level Low level input voltage VI Input voltage VO Output voltage IOH High-level High level output current IOL Low-level Low level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature MIN MAX 2 6 2.1 2.1 VCC = 4.5 V 3.15 3.15 VCC = 5.5 V 3.85 3.85 VCC = 3 V VIL SN74AC573 UNIT V V 0.9 0.9 VCC = 4.5 V 1.35 1.35 VCC = 5.5 V 1.65 1.65 V 0 VCC 0 VCC V 0 VCC 0 VCC V VCC = 3 V −12 −12 VCC = 4.5 V −24 −24 VCC = 5.5 V −24 −24 VCC = 3 V 12 12 VCC = 4.5 V 24 24 VCC = 5.5 V 24 24 8 8 ns/V 85 °C −55 125 −40 mA mA NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −50 50 μA VOH IOH = −12 mA 24 mA IOH = −24 IOH = −75 mA† IOL = 12 mA IOL = 24 mA † TA = 25°C MIN TYP SN54AC573 MAX MIN MAX SN74AC573 MIN 3V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 3V 2.58 2.48 2.48 4.5 V 3.94 3.8 3.8 5.5 V 4.94 4.8 4.8 5.5 V IOL = 50 μA VOL VCC 3.85 MAX UNIT V 3.85 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 3V 0.36 0.44 0.44 4.5 V 0.36 0.44 0.44 5.5 V 0.36 0.44 0.44 1.65 1.65 ±1 ±1 μA V IOL = 75 mA 5.5 V II VI = VCC or GND 5.5 V ±0.1 IOZ VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 μA ICC VI = VCC or GND, 5.5 V 4 80 40 μA Ci VI = VCC or GND IO = 0 5V 5 pF Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AC573, SN74AC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN tw Pulse duration, LE high tsu Setup time, data before LE↓ th Hold time, data after LE↓ SN54AC573 MAX MIN SN74AC573 MAX MIN MAX UNIT 6 8 7 ns 3.5 5 4 ns 2 3 2 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN SN54AC573 MAX MIN SN74AC573 MAX MIN MAX UNIT tw Pulse duration, LE high 4 6 5 ns tsu Setup time, data before LE↓ 3 4.5 3.5 ns th Hold time, data after LE↓ 2 3 2 ns switching characteristics over recommended operating free-air temperature range, VCC = 3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) D Q LE Q OE Q OE Q TA = 25°C SN54AC573 SN74AC573 MIN MAX MIN MAX MIN MAX 2.5 13 1.5 16.5 2 15 2.5 12 1.5 15.5 2 14 2.5 13 1.5 16.5 2 15 2.5 12 1.5 15.5 2 14 2.5 11 1.5 13.5 2 12 2.5 11 1.5 14 2 12.5 2.5 12.5 1.5 15 2 13.5 2.5 9.5 1.5 12 2 10.5 UNIT ns ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) D Q LE Q OE Q OE Q TA = 25°C SN54AC573 SN74AC573 MIN MAX MIN MAX MIN MAX 2.5 10 1.5 13 2 11.5 2.5 9.5 1.5 12.5 2 11 2.5 9.5 1.5 12.5 2 11 2.5 8.5 1.5 11.5 2 10 2.5 9 1.5 11.5 2 10 2.5 8.5 1.5 11 2 9.5 2.5 11 1.5 13.5 2 12 2.5 8 1.5 10.5 2 9 UNIT ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF, PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP UNIT 25 pF SN54AC573, SN74AC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open 500 Ω LOAD CIRCUIT VCC 50% VCC Timing Input 0V tw tsu 3V Input 50% VCC 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS VCC Input 50% VCC 50% VCC 0V 50% VCC Out-of-Phase Output VOH 50% VCC VOL 50% VCC tPLZ ≈VCC 50% VCC tPZH VOH 50% VCC VOL 50% VCC 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL VCC 50% VCC tPZL tPHL tPLH In-Phase Output Output Control (low-level enabling) VOL tPHZ Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS VOL + 0.3 V 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74AC573DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC573 Samples SN74AC573DBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC573 Samples SN74AC573DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC573 Samples SN74AC573DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC573 Samples SN74AC573DWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC573 Samples SN74AC573N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74AC573N Samples SN74AC573NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC573 Samples SN74AC573PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC573 Samples SN74AC573PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC573 Samples SN74AC573PWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC573 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of