Product
Folder
Sample &
Buy
Technical
Documents
Support &
Community
Tools &
Software
SN74AHC132
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
SN74AHC132 Quadruple Positive-NAND Gates with Schmitt-Trigger Inputs
1 Features
3 Description
•
•
•
•
•
•
The SN7AHC132 device is a quadruple positiveNAND gate designed for 2-V to 5.5-V VCC operation.
This device performs the Boolean function
Y = A × B or Y = A + B in positive logic.
1
•
Operating Range 2-V to 5.5-V VCC
Operation From Very Slow Input Transitions
Temperature-Compensated Threshold Levels
High Noise Immunity
Same Pinouts as SNx4AHC00
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
Device Information(1)
PART NUMBER
SNx4AHC132
PACKAGE
BODY SIZE (NOM)
SOIC (14)
8.65 mm × 3.91 mm
SSOP (14)
6.20 mm x 5.30 mm
TVSOP (14)
3.60 mm x 4.40 mm
TSSOP (14)
5.00 mm x 4.40 mm
VQFN (14)
3.50 mm x 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
Electronic Points of Sale
Telecom Infrastructure
Network Switches
Tests and Measurements
4 Simplified Schematic
A
Y
B
A
Y
B
A
Y
B
A
Y
B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC132
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
3
4
4
4
4
5
5
5
6
6
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Noise Characteristics ................................................
Operating Characteristics..........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 7
9
Detailed Description .............................................. 8
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
8
8
10 Application and Implementation.......................... 9
10.1 Application Information............................................ 9
10.2 Typical Application ................................................. 9
11 Power Supply Recommendations ..................... 10
12 Layout................................................................... 10
12.1 Layout Guidelines ................................................. 10
12.2 Layout Example .................................................... 10
13 Device and Documentation Support ................. 11
13.1 Trademarks ........................................................... 11
13.2 Electrostatic Discharge Caution ............................ 11
13.3 Glossary ................................................................ 11
14 Mechanical, Packaging, and Orderable
Information ........................................................... 11
5 Revision History
Changes from Revision G (September 2002) to Revision H
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Deleted SN54AHC132 device from data sheet. .................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Pin Functions table...................................................................................................................................................... 3
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 4
•
Added Thermal Information table. .......................................................................................................................................... 4
•
Added –40°C to 125°C range for SN74AHC132 in Electrical Characteristics table............................................................... 4
•
Added TA = –40°C to 125°C for SN74AHC132 in both Switching Characteristics tables. ..................................................... 5
•
Added Typical Characteristics. ............................................................................................................................................... 6
•
Added Detailed Description section........................................................................................................................................ 8
•
Added Application and Implementation section...................................................................................................................... 9
•
Added Power Supply Recommendations and Layout sections............................................................................................ 10
2
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC132
SN74AHC132
www.ti.com
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
6 Pin Configuration and Functions
SN74AHC132 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
1B
1Y
2A
2B
2Y
VCC
13
1
14
2
13 4B
3
12 4A
4Y
4
11
5
10 3B
9 3A
6
7
8
3Y
14
2
1A
1
GND
1A
1B
1Y
2A
2B
2Y
GND
SN74AHC132 . . . RGY PACKAGE
(TOP VIEW)
Pin Functions
PIN
SN74AHC132
NAME
I/O
DESCRIPTION
D, DB, DGV,
N, NS, PW, RGY
1A
1
I
1A Input
1B
2
I
1B Input
1Y
3
O
1Y Output
2A
4
I
2A Input
2B
5
I
2B Input
2Y
6
O
2Y Output
3Y
8
O
3Y Output
3A
9
I
3A Input
3B
10
I
3B Input
4Y
11
O
4Y Output
4A
12
I
4A Input
4B
13
I
4B Input
GND
7
—
Ground Pin
VCC
14
—
Power Pin
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
7
V
VI
Input voltage range (2)
–0.5
7
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Output voltage range
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
Continuous current through VCC or GND
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC132
3
SN74AHC132
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
www.ti.com
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN74AHC132
MIN
MAX
UNIT
VCC
Supply voltage
2
5.5
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
–50
µA
IOH
High-level output current
VCC = 2 V
IOL
Low-level output current
TA
VCC = 3.3 V ± 0.3 V
–4
VCC = 5 V ± 0.5 V
–8
VCC = 2 V
50
VCC = 3.3 V ± 0.3 V
4
VCC = 5 V ± 0.5 V
8
Operating free-air temperature
(1)
–40
mA
µA
mA
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
7.4 Thermal Information
SN74AHC132
THERMAL METRIC (1)
D
DB
DR
N
NS
PW
RGY
UNIT
14 PINS
RθJA
Junction-to-ambient thermal
resistance
90.6
107.1
90.6
57.4
90.7
122.6
57.5
RθJC(top)
Junction-to-case (top) thermal
resistance
50.9
59.6
50.9
44.9
48.3
51.4
57.5
RθJB
Junction-to-board thermal
resistance
44.8
54.4
44.8
37.2
49.4
64.4
33.6
ψJT
Junction-to-top characterization
parameter
14.7
20.5
14.7
30.1
14.6
6.7
3.4
ψJB
Junction-to-board
characterization parameter
44.5
53.8
44.5
37.1
49.1
63.8
33.7
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
—
—
—
—
—
—
13.9
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
VT+
Positive-going
input threshold
voltage
4
TYP
–40°C to 125°C
SN74AHC132
SN74AHC132
MAX
MIN
MAX
MIN
UNIT
MAX
3V
1.2
2.2
1.2
2.2
1.2
2.2
4.5 V
1.75
3.15
1.75
3.15
1.75
3.15
5.5 V
2.15
3.85
2.15
3.85
2.15
3.85
Submit Documentation Feedback
V
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC132
SN74AHC132
www.ti.com
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
TYP
–40°C to 125°C
SN74AHC132
SN74AHC132
MAX
MIN
MAX
MIN
UNIT
MAX
VT–
Negative-going
input threshold
voltage
3V
0.9
1.9
0.9
1.9
0.9
1.9
4.5 V
1.35
2.75
1.35
2.75
1.35
2.75
5.5 V
1.65
3.35
1.65
3.35
1.65
3.35
ΔVT
Hysteresis
(VT+ – VT–)
3V
0.3
1.2
0.3
1.2
0.3
1.2
4.5 V
0.4
1.4
0.4
1.4
0.4
1.4
5.5 V
0.5
1.6
0.5
1.6
0.5
1.6
2V
1.9
IOH = –50 µA
2
1.9
1.9
2.9
3V
2.9
3
2.9
4.5 V
4.4
4.5
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
IOH = –8 mA
4.5 V
3.94
VOH
3.8
V
V
V
3.8
2V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
3V
0.36
0.44
0.44
IOL = 8 mA
4.5 V
0.36
0.44
0.44
II
VI = 5.5 V or GND
0 V to
5.5 V
±0.1
±1
±1
µA
ICC
VI = VCC or GND
IO = 0
5.5 V
2
20
20
µA
Ci
VI = VCC or GND
5V
10
10
10
pF
IOL = 50 µA
VOL
IOL = 4 mA
1.9
V
7.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
LOAD
CAPACITANCE
MIN
tPLH
A or B
Y
tPHL
tPLH
A or B
Y
tPHL
(1)
CL = 15 pF
TA = –40°C to 125°C
SN74AHC132
SN74AHC132
TYP
MAX
MIN
MAX
MIN
MAX
5.6 (1)
11.9 (1)
1
14
1
15
5.6 (1)
11.9 (1)
1
14
1
15
7.6
15.4
1
17.5
1
19
7.6
15.4
1
17.5
1
19
CL = 50 pF
UNIT
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.7 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
LOAD
CAPACITANCE
MIN
tPLH
A or B
Y
tPHL
tPLH
A or B
Y
tPHL
(1)
CL = 15 pF
CL = 50 pF
TA = –40°C to 125°C
SN74AHC132
SN74AHC132
UNIT
TYP
MAX
MIN
MAX
MIN
MAX
3.9 (1)
7.7 (1)
1
9
1
10
(1)
7.7 (1)
1
9
1
10
5.3
9.7
1
11
1
12
5.3
9.7
1
11
1
12
3.9
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.8 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
(1)
Characteristics are for surface-mount packages only.
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC132
5
SN74AHC132
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
www.ti.com
Noise Characteristics (continued)
VCC = 5 V, CL = 50 pF, TA = 25°C(1)
SN74AHC132
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.45
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.35
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
4.8
V
3.5
V
1.5
V
7.9 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
TYP
f = 1 MHz
11
UNIT
pF
7.10 Typical Characteristics
7
8
6
7
TPD in ns
6
TPD (ns)
TPD (ns)
5
4
3
5
4
3
2
2
1
1
TPD in ns
0
-100
0
-50
0
50
Temperature (qC)
100
150
0
D001
Figure 1. TPD vs Temperature
6
Submit Documentation Feedback
1
2
3
VCC (V)
4
5
6
D002
Figure 2. TPD vs VCC
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC132
SN74AHC132
www.ti.com
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
8 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
50% VCC
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC132
7
SN74AHC132
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
www.ti.com
9 Detailed Description
9.1 Overview
The SN74AHC132 is a quadruple 2-input positive-NAND gate with low drive that produces slow rise and fall
times. This reduces ringing on the output signal.
Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels
for positive- and negative-going signals.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give
clean, jitter-free output signals.
9.2 Functional Block Diagram
A
Y
B
Figure 4. Logic Diagram, Each Gate (Positive Logic)
9.3 Feature Description
•
•
Wide operating voltage range
– Operates from 2 V to 5.5 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
9.4 Device Functional Modes
Table 1. Function Table
(Each Gate)
INPUTS
8
OUTPUT
Y
A
B
H
H
L
L
X
H
X
L
H
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC132
SN74AHC132
www.ti.com
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74AHC132 is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages to 5.5 V at any valid VCC, thus making the device ideal for down
translation.
10.2 Typical Application
3.3- or 5-V Accessory
5-V Regulated
0.1 µF
Figure 5. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC132
9
SN74AHC132
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
www.ti.com
Typical Application (continued)
10.2.3 Application Curves
AC132
HC132
AHC132
Figure 6. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply-voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1μF is recommended. If there are multiple VCC pins then a 0.01 μF or a 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in the Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part
is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
10
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC132
SN74AHC132
www.ti.com
SCLS365H – MAY 1996 – REVISED OCTOBER 2014
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC132
11
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AHC132D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC132
SN74AHC132DBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA132
SN74AHC132DGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA132
SN74AHC132DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC132
SN74AHC132DRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC132
SN74AHC132N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC132N
SN74AHC132NSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC132
SN74AHC132PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA132
SN74AHC132PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA132
SN74AHC132PWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA132
SN74AHC132RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HA132
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
