SN74AHC174DGVR

SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002 D D D D D SN54AHC174 . . . J OR W PACKAGE SN74AHC174 . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) Operating Range 2-V to 5.5-V VCC Contain Six Flip-Flops With Single-Rail Outputs Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) CLR 1Q 1D 2D 2Q 3D 3Q GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 6Q 6D 5D 5Q 4D 4Q CLK SN54AHC174 . . . FK PACKAGE (TOP VIEW) 1Q CLR NC VCC 6Q description The ’AHC174 devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input and are designed for 2-V to 5.5-V VCC operation. 1D 2D NC 2Q 3D 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6D 5D NC 5Q 4D 3Q GND NC CLK 4Q Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. 4 NC – No internal connection ORDERING INFORMATION PDIP – N –55°C to 125°C TOP-SIDE MARKING Tube SN74AHC174N Tube SN74AHC174D Tape and reel SN74AHC174DR SOP – NS Tube SN74AHC174NSR AHC174 SSOP – DB Tape and reel SN74AHC174DBR HA174 TSSOP – PW Tape and reel SN74AHC174PWR HA174 TVSOP – DGV Tape and reel SN74AHC174DGVR HA174 CDIP – J Tube SNJ54AHC174J SNJ54AHC174J CFP – W Tube SNJ54AHC174W SNJ54AHC174W LCCC – FK Tube SNJ54AHC174FK SNJ54AHC174FK SOIC – D –40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SN74AHC174N AHC174 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002 FUNCTION TABLE (each flip-flop) INPUTS CLR CLK D OUTPUT Q L X X L H ↑ H H H ↑ L L H L X Q0 logic diagram (positive logic) CLR CLK 1D 1 9 3 1D C1 2 1Q R To Five Other Channels Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002 recommended operating conditions (see Note 3) SN54AHC174 VCC Supply voltage VIH VCC = 2 V VCC = 3 V High-level input voltage Low-level input voltage VI VO 2 5.5 Output voltage Dt /Dv 5.5 2.1 V V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC –50 0 VCC –50 mA VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V Input transition rise or fall rate 2 UNIT 1.5 3.85 VCC = 2 V VCC = 3.3 V ± 0.3 V Low-level output current MAX 2.1 VCC = 5 V ± 0.5 V VCC = 2 V IOL MIN 3.85 VCC = 3 V VCC = 5.5 V High-level output current SN74AHC174 0.5 Input voltage IOH MAX 1.5 VCC = 5.5 V VCC = 2 V VIL MIN VCC = 5 V ± 0.5 V –4 –4 –8 –8 50 50 4 4 8 8 100 100 20 20 V mA mA mA ns / V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TA = 25°C TYP MAX 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 IOH = –4 mA 3V 2.58 2.48 2.48 IOH = –8 mA 4.5 V 3.94 3.8 3.8 TEST CONDITIONS VCC IOH = –50 mA VOH IOL = 50 mA VOL IOL = 4 mA II ICC Ci IOL = 8 mA VI = 5.5 V or GND VI = VCC or GND, VI = VCC or GND IO = 0 SN54AHC174 MIN MAX SN74AHC174 MIN MAX UNIT V 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 3V 0.36 0.5 0.44 V 4.5 V 0.36 0.5 0.44 0 V to 5.5 V ± 0.1 ± 1* ±1 4 40 40 mA mA 10 pF 5.5 V 5V 1.7 10 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) TA = 25°C MIN MAX tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ SN54AHC174 MIN MAX SN74AHC174 MIN CLR low 5 5 5 CLK high or low 5 5 5 Data 5 6 6 CLR inactive 3 3 3 0 0 0 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) TA = 25°C MIN MAX tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ SN54AHC174 MIN MAX SN74AHC174 MIN CLR low 5 5 5 CLK high or low 5 5 5 Data 4.5 4.5 4.5 CLR inactive 2.5 2.5 2.5 0.5 0.5 0.5 MAX UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPHL tPLH tPHL tPHL tPLH tPHL 95* 170* 80* 80 CL = 50 pF 55 130 50 50 CL = 15 pF CLK Any Q CL = 15 pF CLR Any Q CL = 50 pF CL = 50 pF MAX MIN MAX 1* 13.5* 1 13.5 5.8* 11* 1* 13* 1 13 5.8* 11* 1* 13* 1 13 6 14.9 1 17 1 17 7.5 14.5 1 16.5 1 16.5 7.5 14.5 1 16.5 1 16.5 • DALLAS, TEXAS 75265 1.5** UNIT MHz 11.4* PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 MIN 4.5* tsk(o) CL = 50 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested. ** On products compliant to MIL-PRF-38535, this parameter does not apply. 4 SN74AHC174 CL = 15 pF Any Q Any Q SN54AHC174 MIN CLR CLK TA = 25°C TYP MAX LOAD CAPACITANCE 1.5 ns ns ns ns ns SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPHL tPHL tPLH tPHL SN54AHC174 SN74AHC174 MIN CL = 15 pF 130* 240* 110* 110 CL = 50 pF 90 180 80 80 fmax tPHL tPLH TA = 25°C TYP MAX LOAD CAPACITANCE CLR Any Q CL = 15 pF CLK Any Q CL = 15 pF CLR Any Q CL = 50 pF CLK Any Q CL = 50 pF MIN MAX MIN MAX MHz 3* 7.6* 1* 9* 1 9 4.1* 7.2* 1* 8.5* 1 8.5 4.1* 7.2* 1* 8.5* 1 8.5 4.2 9.6 1 11 1 11 5.5 9.2 1 10.5 1 10.5 5.5 9.2 1 10.5 1 10.5 tsk(o) CL = 50 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested. ** On products compliant to MIL-PRF-38535, this parameter does not apply. 1** UNIT 1 ns ns ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP UNIT 15.2 pF 5 SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL VCC Output Control Output Waveform 1 S1 at VCC (see Note B) 50% VCC 0V tPZL VOH 50% VCC VOL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AHC174D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHC174 SN74AHC174DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HA174 SN74AHC174DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHC174 SN74AHC174N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74AHC174N SN74AHC174PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HA174 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of