SN74AHCT08NSR

SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 SNx4AHCT08 Quadruple 2-Input Positive-AND Gates 1 Features 3 Description • • The SNx4AHCT08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function Y = A ´ B or Y = A + B in positive logic. • • Inputs are TTL-voltage compatible Latch-up performance exceeds 250 mA per JESD 17 ESD protection exceeds JESD 22: – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) On products compliant to MIL-PRF-38535, All parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. 2 Applications • • • • Package Information(1) PART NUMBER SNx4AHCT08 Servers Network switches PCs and notebooks Electronic points-of-sale (1) PACKAGE BODY SIZE (NOM) D (SOIC, 14) 8.65 mm × 3.91 mm DB (SSOP, 14) 6.20 mm × 5.30 mm NS (SOP, 14) 12.60 mm × 5.30 mm PW (TSSOP, 14) 5.00 mm × 4.40 mm RGY (VQFN, 14) 3.50 mm × 3.50 mm J (CDIP, 14) 19.56 mm × 6.67 mm W (CFP, 14) 9.21 mm × 5.97 mm DGV (TVSOP, 14) 3.60 mm × 4.40 mm N (PDIP, 14) 19.30 mm × 6.35 mm FK (LCCC, 20) 8.89 mm × 8.89 mm BQA (WQFN, 14) 3.00 mm × 2.50 mm For all available packages, see the orderable addendum at the end of the data sheet. A Y B Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................6 6.6 Switching Characteristics, VCC = 5 V ± 0.5 V..............6 6.7 Noise Characteristics.................................................. 7 6.8 Operating Characteristics........................................... 7 6.9 Typical Characteristics................................................ 7 7 Parameter Measurement Information............................ 8 8 Detailed Description........................................................9 8.1 Overview..................................................................... 9 8.2 Functional Block Diagram........................................... 9 8.3 Feature Description.....................................................9 8.4 Device Functional Modes............................................9 9 Application and Implementation.................................. 10 9.1 Application Information............................................. 10 9.2 Typical Application.................................................... 10 9.3 Power Supply Recommendations............................. 11 9.4 Layout....................................................................... 11 10 Device and Documentation Support..........................12 10.1 Receiving Notification of Documentation Updates..12 10.2 Support Resources................................................. 12 10.3 Trademarks............................................................. 12 10.4 Electrostatic Discharge Caution..............................12 10.5 Glossary..................................................................12 11 Mechanical, Packaging, and Orderable Information.................................................................... 12 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision N (September 2015) to Revision O (May 2023) Page • Updated the numbering format for tables, figures, and cross-references throughout the document................. 1 • Updated the package information table to include BQA (WQFN)...................................................................... 1 • Added BQA (WQFN) information to the Thermal Information table....................................................................6 Changes from Revision M (July 2014) to Revision N (September 2015) Page • Added TJ, Junction temperature ........................................................................................................................ 5 • Updated VIH and VIL MIN and MAX values.........................................................................................................5 Changes from Revision L (October 1995) to Revision M (July 2014) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 • Deleted Ordering Information table.................................................................................................................... 1 • Added Military Disclaimer to Features list.......................................................................................................... 1 • Added Applications. ...........................................................................................................................................1 • Added Pin Functions table..................................................................................................................................3 • Added ESD Ratings table. ................................................................................................................................. 5 • Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ...................... 5 • Added Thermal Information table....................................................................................................................... 6 • Added Typical Characteristics section................................................................................................................ 7 • Added Application and Implementation section................................................................................................10 • Added Power Supply Recommendations and Layout sections........................................................................ 11 2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 1 14 2 13 4B 3 12 4A 4Y 4 11 5 10 3B 9 3A 6 7 8 Figure 5-2. SN7AHCT08 RGY or BQA Package, 14Pin VQFN or WQFN (Top View) 1B 1A NC VCC 4B Figure 5-1. SN54AHCT08 J or W Package, 14-Pin CDIP or CFP SN74AHCT08 D, DB, DGV, N, NS, or PW Package, 14-Pin SOIC, SSOP, TVSOP, PDIP, SO, or TSSOP (Top View) VCC 14 3Y 1 GND 1A 1B 1Y 2A 2B 2Y GND 1A 5 Pin Configuration and Functions 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1Y NC 2A NC 2B NC − No internal connection Figure 5-3. SN54HACT08 FK Package, 20-Pin LCCC (Top View) Table 5-1. Pin Functions PIN SN74AHCT08 NAME SN54AHCT08 TYPE DESCRIPTION (1) D, DB, DGV, N, NS, PW RGY, BQA J, W FK 1A 1 1 1 2 I 1A Input 1B 2 2 2 3 I 1B Input 1Y 3 3 3 4 O 1Y Output 2A 4 4 4 6 I 2A Input 2B 5 5 5 8 I 2B Input 2Y 6 6 6 9 O 2Y Output 3Y 8 8 8 12 O 3Y Output 3A 9 9 9 13 I 3A Input 3B 10 10 10 14 I 3B Input 4Y 11 11 11 16 O 4Y Output 4A 12 12 12 18 I 4A Input 4B 13 13 13 19 I 4B Input GND 7 7 7 10 — Ground Pin Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 3 SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 Table 5-1. Pin Functions (continued) PIN SN74AHCT08 NAME D, DB, DGV, N, NS, PW SN54AHCT08 RGY, BQA J, W TYPE DESCRIPTION (1) FK 1 5 NC — — — 7 11 — No Connection — Power Pin 15 17 VCC (1) 4 14 14 14 20 I = input, O = output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC MIN MAX UNIT Supply voltage range –0.5 7 V range(2) –0.5 7 V –0.5 VCC + 0.5 V VI Input voltage VO Output voltage range(2) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA 150 °C 150 °C Continuous current through VCC or GND Tstg Storage temperature range TJ Junction temperature (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC V(ESD) (1) (2) Electrostatic discharge JS-001(1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101(2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)(1) SN54AHCT08 SN74AHCT08 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature (1) 2 2 0.8 –8 –55 V V –8 V mA 8 8 mA 20 20 ns/V 125 °C 125 –40 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI Application Report, Implications of Slow or Floating CMOS Inputs, (SCBA004). Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 5 SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 6.4 Thermal Information SN74AHCT08 THERMAL METRIC(1) D (SOIC) DB (SSOP) DGV (TVSOP) N (PDIP) BQA (WQFN) UNIT 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 97.5 109.5 133.3 59.7 88.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 58.7 62.1 55.6 47.3 90.9 °C/W RθJB Junction-to-board thermal resistance 51.8 56.9 66.3 39.5 56.8 °C/W ψJT Junction-to-top characterization parameter 22.6 22.6 7.8 32.4 9.9 °C/W ψJB Junction-to-board characterization parameter 51.6 56.3 56.6 39.4 56.7 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, (SPRA953). 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH 4.5 V IOH = –8 mA IOL = 50 µA VOL TA = 25°C VCC MIN TYP 4.4 4.5 SN54AHCT08 MAX 3.94 4.5 V IOL = 8 mA MIN SN74AHCT08 MAX MIN 4.4 4.4 3.8 3.8 MAX UNIT V 0.1 0.1 0.1 0.36 0.44 0.44 V II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1(1) ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 2 20 20 µA ΔICC (2) One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA Ci VI = VCC or GND 10 pF (1) (2) 5V 4 10 On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. 6.6 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL (1) 6 FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A or B Y CL = 15 pF A or B Y CL = 50 pF TA = 25°C MIN SN54AHCT08 SN74AHCT08 TYP MAX MIN MAX MIN MAX 5(1) 6.9(1) 1(1) 8(1) 1 8 5(1) 6.9(1) 1(1) 8(1) 1 8 5.5 7.9 1 9 1 9 5.5 7.9 1 9 1 9 UNIT ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 6.7 Noise Characteristics VCC = 5 V, CL = 50 pF, TA = 25°C(1) SN74AHCT08 PARAMETER VOL(P) Quiet output, maximum dynamic VOL VOL(V) Quiet output, minimum dynamic VOL VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) MIN UNIT TYP MAX 0.4 0.8 V –0.4 –0.8 V 4.4 V 2 V 0.8 V TYP UNIT Characteristics are for surface-mount packages only. 6.8 Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, f = 1 MHz 18 pF 6.9 Typical Characteristics 4.5 4 3.5 TPD (ns) 3 2.5 2 1.5 1 0.5 TPD in ns 0 -100 -50 0 50 Temperature (qC) 100 150 D001 Figure 6-1. TPD vs Temperature Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 7 SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 7 Parameter Measurement Information VCC Test Point From Output Under Test RL = 1 kΩ From Output Under Test S1 Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH In-Phase Output 50% VCC tPHL Out-of-Phase Output 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control VOL + 0.3 V VOL tPHZ Output Waveform 2 S1 at GND (see Note B) 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms 8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 8 Detailed Description 8.1 Overview The SNx4AHCT08 devices are quadruple 2-input positive-AND gates with low drive that will produce slow rise and fall times. This slow transition reduces ringing on the output signal. The device has TTL inputs that allow up translation from 3.3 V to 5 V. The inputs are high impedance when VCC = 0 V. 8.2 Functional Block Diagram A Y B 8.3 Feature Description • • Slow rise and fall time on outputs allow for low-noise outputs TTL inputs allow up translation from 3.3 V to 5 V 8.4 Device Functional Modes Table 8-1 is the function table for the SNx4AHCT08. Table 8-1. Function Table (Each Gate) INPUTS A B OUTPUT Y H H H L X L X L L Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 9 SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SNx4AHCT08 devices are low-drive CMOS devices that can be used for a multitude of bus-interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The TTL inputs can except voltages down to 3.3 V and translate up to 5 V. 9.2 Typical Application 3.3-V Bus Driver VCC 5 V Regulated 0.1 µF 5-V Accessory Figure 9-1. Typical Application Diagram 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended input conditions • Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table. • Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table. • Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC 2. Recommend output conditions • Load currents should not exceed 25 mA per output and 50 mA total for the part • Outputs should not be pulled above VCC 10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 9.2.3 Application Curves Figure 9-2. Switching Characteristics Comparison 9.3 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 9.4 Layout 9.4.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 9-3 are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the IOs, so they cannot float when disabled. 9.4.2 Layout Example Vcc Unused Input Input Output Unused Input Output Input Figure 9-3. Layout Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 11 SN54AHCT08, SN74AHCT08 www.ti.com SCLS237O – OCTOBER 1995 – REVISED MAY 2023 10 Device and Documentation Support 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN54AHCT08 SN74AHCT08 PACKAGE OPTION ADDENDUM www.ti.com 12-May-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9682101Q2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629682101Q2A SNJ54AHCT 08FK 5962-9682101QCA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9682101QC A SNJ54AHCT08J 5962-9682101QDA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9682101QD A SNJ54AHCT08W 5962-9682101VDA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9682101VD A SNV54AHCT08W SN74AHCT08BQAR ACTIVE WQFN BQA 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08 Samples SN74AHCT08DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB08 Samples SN74AHCT08DGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB08 Samples SN74AHCT08DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08 Samples SN74AHCT08DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08 Samples SN74AHCT08N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 SN74AHCT08N Samples SN74AHCT08NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08 Samples SN74AHCT08PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HB08 Samples SN74AHCT08PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB08 Samples SN74AHCT08RGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 HB08 Samples SNJ54AHCT08FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629682101Q2A SNJ54AHCT 08FK Addendum-Page 1 Samples Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 12-May-2023 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SNJ54AHCT08J ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9682101QC A SNJ54AHCT08J SNJ54AHCT08W ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9682101QD A SNJ54AHCT08W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of