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SN54AHCT126, SN74AHCT126
SCLS265P – DECEMBER 1995 – REVISED AUGUST 2014
SNx4AHCT126 Quadruple Bus Buffer Gates With 3-State Outputs
1 Features
3 Description
•
•
The SNxAHCT126 devices are quadruple-bus buffer
gates featuring independent line drivers with 3-state
outputs.
1
•
•
Inputs Are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
PART NUMBER
SNx4AHCT126
PACKAGE
BODY SIZE (NOM)
SOIC (14)
8.65 mm × 3.91 mm
SSOP (14)
6.20 mm × 5.30 mm
TVSOP (14)
3.60 mm × 4.40 mm
PDIP (14)
3.90 mm × 6.35 mm
SOP (14)
10.30 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
Device Information(1)
Servers
PCs and Notebooks
Network Switches
Wearable Health and Fitness Devices
Telecom Infrastructures
Electronic Points of Sale
4 Simplified Schematic
1OE
1A
3OE
1Y
2OE
2A
3A
3Y
4OE
2Y
4A
4Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54AHCT126, SN74AHCT126
SCLS265P – DECEMBER 1995 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
4
4
4
5
5
6
6
6
6
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 5 V ± 0.5 V ..........
Noise Characteristics ................................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
8
8
10 Application and Implementation.......................... 9
10.1 Application Information............................................ 9
10.2 Typical Application ................................................. 9
11 Power Supply Recommendations ..................... 10
12 Layout................................................................... 10
12.1 Layout Guidelines ................................................. 10
12.2 Layout Example .................................................... 10
13 Device and Documentation Support ................. 11
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
14 Mechanical, Packaging, and Orderable
Information ........................................................... 11
5 Revision History
Changes from Revision O (July 2003) to Revision P
Page
•
Updated document to new TI data sheet standards. ............................................................................................................. 1
•
Deleted Ordering Information Table. ...................................................................................................................................... 1
•
Added Military Disclaimer to Features list. ............................................................................................................................. 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Pin Functions table...................................................................................................................................................... 3
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 4
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added –40°C to 125°C for SN74AHCT126 in Electrical Characteristics table....................................................................... 5
•
Added –40°C to 125°C for SN74AHCT126 in the Switching Characteristics table................................................................ 6
•
Added Typical Characteristics. ............................................................................................................................................... 6
•
Added Detailed Description section. ...................................................................................................................................... 8
•
Added Application and Implementation section...................................................................................................................... 9
•
Added Power Supply Recommendations and Layout sections............................................................................................ 10
2
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SCLS265P – DECEMBER 1995 – REVISED AUGUST 2014
6 Pin Configuration and Functions
SN54AHCT126 . . . FK PACKAGE
SN54AHCT126 . . . J OR W PACKAGE
SN74AHCT126 . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
1A
1OE
NC
VCC
4OE
VCC
4OE
4A
4Y
3OE
3A
3Y
3
1Y
NC
2OE
NC
2A
4
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3OE
2Y
GND
NC
3Y
3A
1OE
1A
1Y
2OE
2A
2Y
GND
(TOP VIEW)
NC – No internal connection
Pin Functions
PIN
SN74AHCT126
NAME
SN54AHCT126
I/O
DESCRIPTION
D, DB, DGV,
N, NS, PW
J, W
FK
1A
2
2
3
I
1A Input
1OE
1
1
2
I
Output Enable 1
1Y
3
3
4
O
1Y Output
2A
5
5
8
I
2A Input
2OE
4
4
6
I
Output Enable 2
2Y
6
6
9
O
2Y Output
3A
9
9
13
I
3A Input
3OE
10
10
14
I
Output Enable 3
3Y
8
8
12
O
3Y Output
4A
12
12
18
I
4A Input
4OE
13
13
19
I
Output Enable 4
4Y
11
11
16
O
4Y Output
GND
7
7
10
—
Ground Pin
—
No Connection
—
Power Pin
1
5
NC
—
7
11
15
17
VCC
14
14
20
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Product Folder Links: SN54AHCT126 SN74AHCT126
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
Continuous current through VCC or GND
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
MIN
MAX
UNIT
–65
150
°C
0
2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54AHCT126 (2)
SN74AHCT126
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
IOH
High-level output current
–8
–8
mA
IOL
Low-level output current
8
8
mA
Δt/Δv
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
125
°C
(1)
(2)
4
2
2
0.8
125
V
0.8
V
0
5.5
V
0
VCC
20
–55
V
–40
V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI Application Report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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7.4 Thermal Information
SN74AHCT126
THERMAL METRIC (1)
D
DB
DGV
N
NS
PW
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
90.6
107.1
129.0
57.4
90.7
122.6
RθJC(top)
Junction-to-case (top) thermal resistance
50.9
59.6
52.1
44.9
48.3
51.4
RθJB
Junction-to-board thermal resistance
44.8
54.4
62.0
37.2
49.4
64.4
ψJT
Junction-to-top characterization parameter
14.7
20.5
6.5
30.1
14.6
6.7
ψJB
Junction-to-board characterization parameter
44.5
53.8
61.3
37.1
49.1
63.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
n/a
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
VOH
4.5 V
IOH = –8 mA
IOL = 50 µA
VOL
VCC
TA = 25°C
MIN
TYP
4.4
4.5
MAX
3.94
4.5 V
IOL = 8 mA
SN54AHCT126
MIN
MAX
SN74AHCT126
MIN
MAX
SN74AHCT126
–40 to 125°C
MIN
4.4
4.4
4.4
3.8
3.8
3.8
UNIT
MAX
V
0.1
0.1
0.1
0.1
0.36
0.44
0.44
0.44
V
II
VI = 5.5 V or GND
0 V to
5.5 V
±0.1
±1 (1)
±1
±1
µA
IOZ
VO = VCC or GND
5.5 V
±0.25
±2.5
±2.5
±2.5
µA
ICC
VI = VCC or
GND
5.5 V
2
20
20
20
µA
ΔICC (2)
One input at 3.4 V,
Other inputs at VCC or
GND
5.5 V
1.35
1.5
1.5
1.5
mA
Ci
VI = VCC or GND
5V
4
Co
VO = VCC or GND
5V
15
(1)
(2)
IO = 0
10
10
pF
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
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7.6 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(OUTPUT)
TO
(INPUT)
MIN
tPLH
A
Y
CL = 15 pF
tPHL
tPZH
OE
Y
tPHZ
OE
Y
CL = 15 pF
tPLZ
tPLH
A
Y
CL = 50 pF
tPHL
tPZH
OE
Y
tPHZ
OE
Y
tsk(o)
(1)
(2)
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.8 (1)
5.5 (1)
1 (1)
6.5 (1)
1
6.5
1
7
(1)
(1)
(1)
6.5 (1)
1
6.5
1
7
5.5
1
ns
3.6 (1)
5.1 (1)
1 (1)
6 (1)
1
6
1
6.5
3.6 (1)
5.1 (1)
1 (1)
6 (1)
1
6
1
6.5
4.6 (1)
6.8 (1)
1 (1)
8 (1)
1
8
1
8.5
4.6 (1)
6.8 (1)
1 (1)
8 (1)
1
8
1
8.5
5.3
7.5
1
8.5
1
8.5
1
9.5
5.3
7.5
1
8.5
1
8.5
1
9.5
5.1
7.1
1
8
1
8
1
9
5.1
7.1
1
8
1
8
1
9
6.1
8.8
1
10
1
10
1
11
6.1
8.8
1
10
1
10
1
11
ns
ns
ns
CL = 50 pF
tPLZ
SN74AHCT126
–40°C to 125°C
ns
CL = 50 pF
tPZL
SN74AHCT126
–40°C to 85°C
TYP
3.8
CL = 15 pF
tPZL
SN54AHCT126
–55°C to 125°C
TA = 25°C
LOAD
CAPACITANCE
ns
1 (2)
CL = 50 pF
1
1
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
7.7 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
SN74AHCT126
PARAMETER
MIN
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
4.4
V
2
V
0.8
V
Characteristics are for surface-mount packages only.
7.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
TYP
14
UNIT
pF
7.9 Typical Characteristics
5
TPD (ns)
4
3
2
1
TPD in ns
0
-100
-50
0
50
Temperature (qC)
100
150
D001
Figure 1. TPD vs Temperature
6
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SCLS265P – DECEMBER 1995 – REVISED AUGUST 2014
8 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage and Waveforms
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9 Detailed Description
9.1 Overview
The SNxAHCT126 devices are quadruple-bus buffer gates featuring independent line drivers with 3-state
outputs.
Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the respective
gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver.
9.2 Functional Block Diagram
1OE
3OE
1A
1Y
2OE
3A
3Y
4OE
2A
2Y
4A
4Y
9.3 Feature Description
•
•
TTL inputs
– Lowered switching threshold allows up translation from 3.3 V to 5 V
Slow edges reduce output ringing
9.4 Device Functional Modes
Table 1. Function Table
(Each Buffer)
INPUTS
8
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
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10 Application and Implementation
10.1 Application Information
The SNx4AHCT126 is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V
VIL and 2-V VIH. This feature makes it ideal for translating up from 3.3 V to 5 V. Figure 4 shows this type of
translation.
10.2 Typical Application
Regulated 5 V
Regulated 3.3 V
VCC
1OE
4OE
1A
1Y
µC or
5 V µC
System Logic
System Logic
4A
4Y
LEDs
GND
Figure 3. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended input conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
2. Recommend output conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part
– Outputs should not be pulled above VCC
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Typical Application (continued)
10.2.3 Application Curves
Figure 4. Up Translation
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1
μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified in Figure 5 are the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float
outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs
section of the part when asserted. This will not disable the input section of the IO’s so they cannot float when
disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 5. Layout Diagram
10
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54AHCT126
Click here
Click here
Click here
Click here
Click here
SN74AHCT126
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9686301QDA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9686301QD
A
SNJ54AHCT126W
SN74AHCT126D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT126
Samples
SN74AHCT126DBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB126
Samples
SN74AHCT126DG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT126
Samples
SN74AHCT126DGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB126
Samples
SN74AHCT126DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT126
Samples
SN74AHCT126N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHCT126N
Samples
SN74AHCT126NSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT126
Samples
SN74AHCT126PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB126
Samples
SN74AHCT126PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB126
Samples
SNJ54AHCT126W
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9686301QD
A
SNJ54AHCT126W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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