SN74AHCT16244DGGR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN74AHCT16244 SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 SN74AHCT16244 16-Bit Buffers/Drivers With 3-State Outputs 1 Features 2 Applications • • • • • • • 1 • • • • • • • Members of the Texas Instruments Widebus™ Family EPIC™ (Enhanced-Performance Implanted CMOS) Process Inputs are TTL-Voltage Compatible Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015 Package Options Include: – Plastic Shrink Small Outline (DL) Package – Thin Shrink Small Outline (DGG) Package – Thin Very Small Outline (DGV) Package – 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings Telecom Infrastructure Wireless Infrastructure Electronic Points of Sale Health and Fitness Printers and Other Peripherals Motor Drives 3 Description The SN74AHCT16244 device is a 16-bit buffer and line driver specifically designed to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Device Information(1) PART NUMBER SN74AHCT16244 PACKAGE BODY SIZE (NOM) TSSOP (48) 12.50 mm x 6.10 mm TVSOP (48) 9.70 mm x 4.40 mm SSOP (48) 15.80 mm x 7.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic 1OE 3OE 1A1 1Y1 3A1 3Y1 1A2 1Y2 3A2 3Y2 1A3 1Y3 3A3 3Y3 1A4 1Y4 3A4 3Y4 2OE 4OE 2A1 2Y1 4A1 4Y1 2A2 2Y2 4A2 4Y2 2A3 2Y3 4A3 4Y3 2A4 2Y4 4A4 4Y4 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AHCT16244 SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 5 5 5 6 6 6 7 7 7 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics, VCC = 5 V ± 0.5 V ........... Noise Characteristics ................................................ Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 8 9 Detailed Description .............................................. 9 9.1 9.2 9.3 9.4 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 9 9 9 9 10 Application and Implementation........................ 10 10.1 Application Information.......................................... 10 10.2 Typical Application ............................................... 10 11 Power Supply Recommendations ..................... 11 12 Layout................................................................... 11 12.1 Layout Guidelines ................................................. 11 12.2 Layout Example .................................................... 11 13 Device and Documentation Support ................. 12 13.1 Trademarks ........................................................... 12 13.2 Electrostatic Discharge Caution ............................ 12 13.3 Glossary ................................................................ 12 14 Mechanical, Packaging, and Orderable Information ........................................................... 12 5 Revision History Changes from Revision I (January 2000) to Revision J Page • Updated document to new TI data sheet format. ................................................................................................................... 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 • Deleted SN54AHCT16244 device from data sheet................................................................................................................ 1 • Added Applications. ................................................................................................................................................................ 1 • Added Pin Functions table...................................................................................................................................................... 3 • Added Handling Ratings table. ............................................................................................................................................... 5 • Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 5 • Added Thermal Information table. .......................................................................................................................................... 6 • Added –40°C to 125°C range for SN74AHCT16244 in Electrical Characteristics table. ....................................................... 6 • Added TA = –40°C to 125°C for SN74AHCT16244 in the Switching Characteristics table.................................................... 6 • Added Typical Characteristics. ............................................................................................................................................... 7 • Added Detailed Description section........................................................................................................................................ 9 • Added Application and Implementation section.................................................................................................................... 10 • Added Power Supply Recommendations and Layout sections............................................................................................ 11 2 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 SN74AHCT16244 www.ti.com SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 6 Pin Configuration and Functions SN74AHCT16244. . . DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE Pin Functions PIN I/O DESCRIPTION 1OE I Output Enable 1 2 1Y1 O 1Y1 Output 3 1Y2 O 1Y2 Output 4 GND — Ground Pin 5 1Y3 O 1Y3 Output 6 1Y4 O 1Y4 Output 7 VCC — Power Pin 8 2Y1 O 2Y1 Output 9 2Y2 O 2Y2 Output 10 GND — Ground Pin 11 2Y3 O 2Y3 Output 12 2Y4 O 2Y4 Output 13 3Y1 O 3Y1 Output 14 3Y2 O 3Y2 Output 15 GND — Ground Pin 16 3Y3 O 3Y3 Output 17 3Y4 O 3Y4 Output 18 VCC — Power Pin NO. NAME 1 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 3 SN74AHCT16244 SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 www.ti.com Pin Functions (continued) PIN 4 I/O DESCRIPTION 4Y1 O 4Y1 Output 4Y2 O 4Y2 Output 21 GND — Ground Pin 22 4Y3 O 4Y3 Output 23 4Y4 O 4Y4 Output 24 4OE I Output Enable 4 25 3OE I Output Enable 3 26 4A4 I 4A4 Input 27 4A3 I 4A3 Input 28 GND — 29 4A2 I 4A2 Input 30 4A1 I 4A1 Input 31 VCC — Power Pin 32 3A4 I 3A4 Input 33 3A3 I 3A3 Input 34 GND — 35 3A2 I 3A2 Input 36 3A1 I 3A1 Input 37 2A4 I 2A4 Input 38 2A3 I 2A3 Input 39 GND — 40 2A2 I 2A2 Input 41 2A1 I 2A1 Input 42 VCC — Power Pin 43 1A4 I 1A4 Input 44 1A3 I 1A3 Input 45 GND — 46 1A2 I 1A2 Input 47 1A1 I 1A1 Input 48 2OE I Output Enable 2 NO. NAME 19 20 Ground Pin Ground Pin Ground Pin Ground Pin Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 SN74AHCT16244 www.ti.com SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 7 UNIT V (2) –0.5 7 V –0.5 VCC + 0.5 VI Input voltage range VO Output voltage range (2) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±75 mA Continuous current through VCC or GND (1) (2) V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT °C –65 150 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) SN74AHCT16244 MIN MAX 4.5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH High-level output current –8 IOL Low-level output current 8 mA ∆t/∆v Input transition rise or fall rate 20 ns/V TA Operating free-air temperature 125 °C (1) 2 V V 0.8 V 0 5.5 V 0 VCC V –40 mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 5 SN74AHCT16244 SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 www.ti.com 7.4 Thermal Information SN74AHCT16244 THERMAL METRIC (1) DGG DGV DL 48 PINS 48 PINS 48 PINS RθJA Junction-to-ambient thermal resistance 72.5 83.5 64.6 RθJC(top) Junction-to-case (top) thermal resistance 26.8 35.7 34.5 RθJB Junction-to-board thermal resistance 39.4 46.6 36.4 ψJT Junction-to-top characterization parameter 2.6 4.3 11.1 ψJB Junction-to-board characterization parameter 39.1 46.0 36.1 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH 4.5 V IOH = –8 mA IOL = 50 µA VOL TA = 25°C VCC MIN TYP 4.4 4.5 MAX MIN 3.94 4.5 V IOL = 8 mA –40°C to 125°C SN74AHCT16244 SN74AHCT16244 MAX MIN 4.4 4.4 3.8 3.8 UNIT MAX V 0.1 0.1 0.1 0.36 0.44 0.44 V II VI = VCC or GND 0 V to 5.5 V ±0.1 ±1 ±1 µA IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5 µA ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40 µA One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA 10 10 10 pF ΔICC (1) Ci VI = VCC or GND 5V 2.5 Co VO = VCC or GND 5V 3 (1) pF This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. 7.6 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER tPLH FROM (INPUT) A TO (OUTPUT) Y tPHL tPZH Y OE Y tPLZ tPLH A Y tPHL tPZH OE Y tPZL tPHZ OE Y tPLZ tsk(o) (1) (2) 6 CL = 15 pF TA = 25°C CL = 15 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF TA = –40°C to 125°C SN74AHCT16244 SN74AHCT16244 UNIT TYP MAX MIN MAX MIN MAX 5.4 (1) 8.5 (1) 1 9.5 1 10.5 5.4 (1) 8.5 (1) 1 9.5 1 10.5 (1) (1) 1 12 1 13 7.7 (1) 10.4 (1) 1 12 1 13 5 (1) 10.4 (1) 1 12 1 13 5 (1) 10.4 (1) 1 12 1 13 7.7 OE tPZL tPHZ LOAD CAPACITANCE 10.4 ns ns ns 7 9.5 1 10.5 1 11.5 5.9 9.5 1 10.5 1 11.5 8.2 11.4 1 13 1 14.5 8.2 11.4 1 13 1 14.5 8.8 11.4 1 13 1 14 8.8 11.4 1 13 1 14 ns ns ns 1 (2) 1 1 ns On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply. Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 SN74AHCT16244 www.ti.com SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 7.7 Noise Characteristics VCC = 5 V, CL = 50 pF, TA = 25°C (1) SN74AHCT16244 PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.7 V VOL(V) Quiet output, minimum dynamic VOL –0.7 V VOH(V) Quiet output, minimum dynamic VOH 4.8 V VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 2 V 0.8 V TYP UNIT 8.2 pF Characteristics are for surface-mount packages only. 7.8 Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, f = 1 MHz 7.9 Typical Characteristics 7 TPD (in ns) 6 TPD (ns) 5 4 3 2 1 0 -100 -50 0 50 Temperature (RC) 100 150 D001 Figure 1. TPD vs Temperature Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 7 SN74AHCT16244 SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 www.ti.com 8 Parameter Measurement Information From Output Under Test Test Point From Output Under Test RL = 1 kΩ S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL 50% VCC 50% VCC 0V tPLZ tPZL ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC VCC Output Control 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 SN74AHCT16244 www.ti.com SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 9 Detailed Description 9.1 Overview The SN74AHCT16244 device is a 16-bit buffer and line driver specifically designed to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device can be used as a four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74AHCT16244 is characterized for operation from –40°C to 125°C. 9.2 Functional Block Diagram 1OE EN1 2OE EN2 3OE EN3 4OE EN4 1 1A1 1 1Y1 1A2 1Y2 1A3 1Y3 1Y4 1A4 2A1 1 2Y1 2 2A2 2Y2 2A3 2Y3 2Y4 2A4 3A1 1 3Y1 3 3A2 3Y2 3A3 3Y3 3Y4 3A4 1 4A1 4 4Y1 4A2 4Y2 4A3 4Y3 4A4 4Y4 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Figure 3. 9.3 Feature Description • • • • VCC is optimized at 5 V Allows up voltage translation from 3.3 V to 5 V – Inputs accept VIH levels of 2 V Slow edge rates minimize output ringing Inputs are TTL-voltage compatible 9.4 Device Functional Modes Table 1. Function Table (Each 4-bit Buffer/Driver) INPUTS OE A OUTPUT Y L H H L L L H X Z Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 9 SN74AHCT16244 SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The SN74HCT16244 is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V VIL and 2-V VIH. This feature makes it ideal for translating up from 3.3 V to 5 V. The figure below shows this type of translation 10.2 Typical Application 5V 3.3 V OE VCC A1 Y1 C or System Logic C/System Logic/LEDs A4 Y2 GND Figure 4. Typical Application Schematic 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended Input Conditions: – For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table. – For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC. 2. Recommended Output Conditions: – Load currents should not exceed 25 mA per output and 75 mA total for the part. – Outputs should not be pulled above VCC. 10 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 SN74AHCT16244 www.ti.com SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 Typical Application (continued) 10.2.3 Application Curves Voltage (1 V/ div) Output Voltage Input Voltage Time (5 ns/div), VCC = 5 V Figure 5. Up Translation 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF is recommended for each power terminal. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled. 12.2 Layout Example Vcc Unused Input Input Output Unused Input Output Input Figure 6. Layout Diagram Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 11 SN74AHCT16244 SCLS334J – MARCH 1996 – REVISED OCTOBER 2014 www.ti.com 13 Device and Documentation Support 13.1 Trademarks Widebus is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT16244 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74AHCT16244DGGRE4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT16244 Samples SN74AHCT16244DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT16244 Samples SN74AHCT16244DGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HF244 Samples SN74AHCT16244DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT16244 Samples SN74AHCT16244DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT16244 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of