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SN54AHCT240, SN74AHCT240
SCLS252N – OCTOBER 1995 – REVISED FEBRUARY 2018
SNx4AHCT240 Octal Inverting Buffers/Drivers With Tri-State Outputs
1 Features
3 Description
•
•
The SNx4AHCT240 octal buffers/drivers are
designed specifically to improve both the
performance and density of tri-state memory-address
drivers, clock drivers, and bus-oriented receivers and
transmitters.
1
•
Inputs are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA
Per JESD 17
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
2 Applications
•
•
•
•
Network Switches
Health and Fitness
Televisions
Power Infrastructures
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AHCT240DB
SSOP (20)
7.50 mm × 5.30 mm
SN74AHCT240NS
SO (20)
12.60 mm × 5.30 mm
SN74AHCT240PW
TSSOP (20)
6.50 mm × 4.40 mm
SN74AHCT240DW
SOIC (20)
12.80 mm × 7.50 mm
SN74AHCT240N
PDIP (20)
25.40 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1OE
2OE
1A1
1Y1
2A1
2Y1
1A2
1Y2
2A2
2Y2
1A3
1Y3
2A3
2Y3
1A4
1Y4
2A4
2Y4
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54AHCT240, SN74AHCT240
SCLS252N – OCTOBER 1995 – REVISED FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
5
5
5
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Noise Characteristics ................................................
Operating Characteristics..........................................
Typical Characteristics.......................................... 7
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
9.1 Overview ................................................................. 10
9.2 Functional Block Diagram ....................................... 10
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1
13.2
13.3
13.4
13.5
Community Resources..........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
Changes from Revision M (April 2016) to Revision N
Page
•
Added junction temperature to Absolute Maximum Ratings table.......................................................................................... 4
•
Moved storage temperature from ESD Ratings table to Absolute Maximum Ratings table................................................... 4
•
Changed the Function table layout....................................................................................................................................... 10
Changes from Revision L (October 2014) to Revision M
Page
•
Changed Handling Ratings table title to ESD Ratings .......................................................................................................... 4
•
Added –40°C to 85°C to SN74AHCT240 header in Electrical Characteristics table.............................................................. 5
•
Added –40°C to 85°C to SN74AHCT240 header in Switching Characteristics table............................................................. 6
Changes from Revision K (July 2003) to Revision L
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Added Military Disclaimer to Features list. ............................................................................................................................. 1
•
Added Applications. ................................................................................................................................................................ 1
•
Extended operating temperature range to 125°C................................................................................................................... 5
•
Added Thermal Information table ........................................................................................................................................... 5
•
Added –40°C to 125°C for SN74AHCT240 in the Electrical Specifications table. ................................................................ 5
•
Added –40°C to 125°C for SN74AHCT240 in the Switching Characteristics table. .............................................................. 6
•
Added Detailed Description section...................................................................................................................................... 10
•
Added Application and Implementation section.................................................................................................................... 11
•
Added Power Supply Recommendations and Layout sections............................................................................................ 12
2
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SCLS252N – OCTOBER 1995 – REVISED FEBRUARY 2018
5 Pin Configuration and Functions
SN54AHCT240, J or W Package
SN74AHCT240, DB, DGV, DW, N, NS, or PW Package (20) Pin
Top View
20
2
19
3
18
4
17
5
16
15
6
7
14
8
13
9
12
10
11
2Y4
1A1
1OE
VCC
2OE
1
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
3
1A2
2Y3
1A3
2Y2
1A4
4
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
1Y1
2A4
1Y2
2A3
1Y3
2Y1
GND
2A1
1Y4
2A2
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
SN54AHCT240 FK Package (20) Pin
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
I
Output Enable 1
1OE
1
1A1
2
I
1A1 Input
2Y4
3
O
2Y4 Output
1A2
4
I
1A2 Input
2Y3
5
O
2Y3 Output
1A3
6
I
1A3 Input
2Y2
7
O
2Y2 Output
1A4
8
I
1A4 Input
2Y1
9
O
2Y1 Output
GND
10
—
Ground Pin
2A1
11
I
2A1 Input
1Y4
12
O
1Y4 Output
2A2
13
I
2A2 Input
1Y3
14
O
1Y3 Output
2A3
15
I
2A3 Input
1Y2
16
O
1Y2 Output
2A4
17
I
2A4 Input
1Y1
18
O
1Y1 Output
2OE
19
I
Output Enable 2
VCC
20
—
Power Pin
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SCLS252N – OCTOBER 1995 – REVISED FEBRUARY 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCC
Input voltage, VI
(2)
Output voltage, VO (2)
MIN
MAX
–0.5
7
UNIT
V
–0.5
7
V
–0.5
VCC + 0.5
V
Input clamp current, IIK
VI < 0
–20
mA
Output clamp current, IOK
VO < 0 or VO > VCC
±20
mA
Continuous output current, IO
VO = 0 to VCC
±25
mA
±75
mA
150
°C
150
°C
Continuous current through VCC or GND
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
V(ESD)
(1)
(2)
4
Electrostatic discharge
MIN
MAX
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
1000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCLS252N – OCTOBER 1995 – REVISED FEBRUARY 2018
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54AHCT240
SN74AHCT240
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level Input voltage
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
2
UNIT
V
2
V
0.8
0.8
V
0
5.5
V
0
VCC
–8
mA
8
mA
125
°C
8
–55
125
–40
V
–8
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the Implications of Slow or Floating
CMOS Inputs application report.
6.4 Thermal Information
SN74AHCT240
THERMAL METRIC (1)
DW
DB
N
NS
PW
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
RθJA
Junction-to-ambient thermal
resistance
83.0
99.9
54.9
80.4
105.4
RθJC(top)
Junction-to-case (top) thermal
resistance
48.9
61.7
41.7
46.9
39.5
RθJB
Junction-to-board thermal
resistance
50.5
55.2
35.8
47.9
56.4
ψJT
Junction-to-top characterization
parameter
21.1
22.6
27.9
19.9
3.1
ψJB
Junction-to-board characterization
parameter
50.1
54.8
35.7
47.5
55.8
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
TYP
4.5
–40°C to 85°C
SN74AHCT240
SN54AHCT240
MAX
MIN
MAX
MIN
–40°C to 125°C
SN74AHCT240
MAX
MIN
VOH
High-level
output voltage
IOH = –50 µA, VCC = 4.5 V
4.4
IOH = –8 mA, VCC = 4.5 V
3.94
VOL
Low-level
output voltage
IOL = 50 µA, VCC = 4.5 V
0.1
0.1
0.1
0.1
IOL = 8 mA, VCC = 4.5 V
0.36
0.44
0.44
0.44
IOZ
Highimpedancestate output
current
VO = VCC or GND
VCC = 5.5 V
±0.25
±2.5
±2.5
±2.5
µA
II
Inflectionpoint current
VI = 5.5 V or GND
VCC = 0 V to 5.5 V
±0.1
±1 (1)
±1
±1
µA
ICC
Supply current
VI = VCC or GND
IO = 0,VCC = 5.5 V
4
40
40
40
µA
ΔICC (2)
One input at 3.4 V
Supply current other inputs at VCC or
change
GND
VCC = 5.5 V
1.35
1.5
1.5
1.5
mA
Ci
Input
capacitance
VI = VCC or GND
VCC = 5.5 V
10
10
pF
Co
Output
capacitance
VO = VCC or GND
VCC = 5.5 V
(1)
(2)
2.5
4.4
4.4
4.4
3.8
3.8
3.8
UNIT
MAX
10
V
3
V
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
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6.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Parameter
Measurement Information section)
PARAMETER
Propagation delay
time
(low-to-high output)
tPLH
tPHL
Propagation delay
time
(high-to-low output)
tPZH
Enable time
(to the high level)
tPZL
Enable time
(to the low level)
tPHZ
Disable time
(from high level)
tPLZ
Disable time
(from low level)
tPLH
Propagation delay
time
(low-to-high output)
tPHL
Propagation delay
time
(high-to-low output)
tPZH
Enable time
(to the high level)
tPZL
Enable time
(to the low level)
tPHZ
Disable time
(from high level)
tPLZ
Disable time
(from low level)
tsk(o)
Skew (time), output
(1)
(2)
TEST CONDITIONS
A-to-Y
TA = 25°C
–40°C to 85°C
SN74AHCT240
SN54AHCT240
–40°C to 125°C
SN74AHCT240
UNIT
TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
5.4 (1)
7.4 (1)
1 (1)
8.5 (1)
1
8.5
1
9.5
(1)
(1)
(1)
(1)
1
8.5
1
9.5
CL = 15 pF
ns
5.4
OE-to-Y
OE-to-Y
A-to-Y
7.4
1
8.5
7.7 (1)
10.4 (1)
1 (1)
12 (1)
1
12
1
13
7.7 (1)
10.4 (1)
1 (1)
12 (1)
1
12
1
13
8.3 (1)
10.4 (1)
1 (1)
12 (1)
1
12
1
13
8.3 (1)
10.4 (1)
1 (1)
12 (1)
1
12
1
13
5.9
8.4
1
9.5
1
9.5
1
10.5
5.9
8.4
1
9.5
1
9.5
1
10.5
8.2
11.4
1
13
1
13
1
14
8.2
11.4
1
13
1
13
1
14
8.8
11.4
1
13
1
13
1
14
8.8
11.4
1
13
1
13
1
14
CL = 15 pF
ns
CL = 15 pF
ns
CL = 50 pF
OE-to-Y
OE-to-Y
ns
CL = 50 pF
ns
CL = 50 pF
CL = 50 pF
ns
1 (2)
1
1
1
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
6.7 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
SN74AHCT240
PARAMETER
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
MIN
TYP
MAX
4.1
UNIT
V
2
V
0.8
V
Characteristics are for surface-mount packages only.
6.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
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TEST CONDITIONS
No load, f = 1 MHz
TYP
10
UNIT
pF
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SCLS252N – OCTOBER 1995 – REVISED FEBRUARY 2018
7 Typical Characteristics
7
6
TPD (ns)
5
4
3
2
1
TPD in ns
0
-100
-50
0
50
Temperature (qC)
100
150
D001
Figure 1. TPD vs Temperature
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8 Parameter Measurement Information
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• PRR ≤ 1 MHz
• ZO = 50 Ω
• tr ≤ 3 ns
• tf ≤ 3 ns
NOTE
All parameters and waveforms are not applicable to all devices.
Test
Point
From Output
Under Test
CL(1)
(1)
CL includes probe and jig capacitance.
(2)
The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit For Totem-Pole Outputs
VCC
S1
Open
RL = 1 kŸ
From Output
Under Test
GND
CL(1)
(1)
CL includes probe and jig capacitance.
(2)
The outputs are measured one at a time, with one transition per measurement.
Figure 3. Load Circuit For Tri-State And Open-Drain Outputs
Table 1. Loading Conditions For Parameter
TEST
S1
tPLH (1), tPHL (1)
Open
tPLZ (2), tPZL
(3)
VCC
(2)
(3)
GND
tPHZ
, tPZH
Open drain
(1)
(2)
(3)
VCC
tPLH and tPHL are the same as tpd.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
tw
3V
Input
1.5 V
1.5 V
0V
Figure 4. Voltage Waveforms Pulse Durations
8
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SCLS252N – OCTOBER 1995 – REVISED FEBRUARY 2018
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
In-Phase
Output
VOH
50% VCC
VOL
50% VCC
tPLH
tPHL
Out-of-Phase
Output
(1)
VOH
50% VCC
VOL
50% VCC
The outputs are measured one at a time, with one transition per measurement.
Figure 5. Voltage Waveforms Propagation Delay Times Inverting and Noninverting Outputs
3V
1.5 V
Timing Input
0V
th
tSU
3V
1.5 V
Data Input
1.5 V
0V
Figure 6. Voltage Waveforms Setup And Hold Times
3V
Output
Control
1.5 V
1.5 V
0V
Output
Waveform 1(1)
S1 at VCC
tPLZ
tPZL
§ 9CC
50% VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
Output
Waveform 2(2)
S1 at GND
VOH
50% VCC
VOH ± 0.3 V
§0V
(1)
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
(2)
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
(3)
The outputs are measured one at a time, with one transition per measurement.
Figure 7. Votlage Waveforms Enable And Disable Times Low- and High-Level Enabling
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9 Detailed Description
9.1 Overview
The SN74AHCT240 devices are organized as two 4-bit
inputs. When OE is low, the device passes inverted data
the outputs are in the high-impedance state. To ensure
down, OE should be tied to VCC through a pull-up resistor;
current-sinking capability of the driver.
buffers/line drivers with separate output-enable (OE)
from the A inputs to the Y outputs. When OE is high,
the high-impedance state during power up or power
the minimum value of the resistor is determined by the
9.2 Functional Block Diagram
1OE
2OE
1A1
1Y1
2A1
2Y1
1A2
1Y2
2A2
2Y2
1A3
1Y3
2A3
2Y3
1A4
1Y4
2A4
2Y4
Copyright © 2016, Texas Instruments Incorporated
9.3 Feature Description
•
•
•
•
VCC is optimized at 5 V
Allows up-voltage translation from 3.3 V to 5 V
– Inputs accept VIH levels of 2 V
Slow edge rates minimize output ringing
Inputs are TTL-voltage compatible
9.4 Device Functional Modes
Table 2. Function Table
(Each 4-bit Inverting Buffer/Driver)
INPUTS
10
OUTPUT
Y
OE
A
L
H
L
L
L
H
H
X
Z
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SNx4AHCT240 device is a low-drive CMOS device that may be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V
VIL and 2-V VIH. This feature makes the SNx4AHCT240 device ideal for translating up from 3.3 V to 5 V. Figure 8
shows this type of translation.
10.2 Typical Application
5V
3.3 V
C or System
Logic
OE
VCC
A1
Y1
SNx4AHCT240
A4
C/System
Logic/LEDs
Y2
GND
Copyright © 2018, Texas Instruments Incorporated
Figure 8. Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant, allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 25 mA per output and 75 mA total for the part.
– Outputs should not be pulled above VCC.
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Typical Application (continued)
10.2.3 Application Curves
Figure 9. Application Scope Capture
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1 μF and 1.0 μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for the best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Such examples are when only two inputs of a triple-input AND gate are used, or
only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states.
Specified in Figure 10 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 10. Layout Diagram
12
Submit Documentation Feedback
Copyright © 1995–2018, Texas Instruments Incorporated
Product Folder Links: SN54AHCT240 SN74AHCT240
SN54AHCT240, SN74AHCT240
www.ti.com
SCLS252N – OCTOBER 1995 – REVISED FEBRUARY 2018
13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54AHCT240
Click here
Click here
Click here
Click here
Click here
SN74AHCT240
Click here
Click here
Click here
Click here
Click here
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1995–2018, Texas Instruments Incorporated
Product Folder Links: SN54AHCT240 SN74AHCT240
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9680601Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629680601Q2A
SNJ54AHCT
240FK
5962-9680601QRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9680601QR
A
SNJ54AHCT240J
5962-9680601QSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9680601QS
A
SNJ54AHCT240W
SN74AHCT240DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB240
Samples
SN74AHCT240DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT240
Samples
SN74AHCT240DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT240
Samples
SN74AHCT240N
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHCT240N
Samples
SN74AHCT240NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT240
Samples
SN74AHCT240PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB240
Samples
SN74AHCT240PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB240
Samples
SN74AHCT240PWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB240
Samples
SNJ54AHCT240FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629680601Q2A
SNJ54AHCT
240FK
SNJ54AHCT240J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9680601QR
A
SNJ54AHCT240J
SNJ54AHCT240W
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9680601QS
A
SNJ54AHCT240W
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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