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SN54AHCT573, SN74AHCT573
SCLS243O – OCTOBER 1995 – REVISED SEPTEMBER 2014
SNx4AHCT573 Octal Transparent D-Type Latches With 3-State Outputs
1 Features
3 Description
•
•
The SNx4AHCT573 devices are octal transparent Dtype latches. When the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When
LE is low, the Q outputs are latched at the logic levels
of the D inputs.
1
•
•
Inputs are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Device Information(1)
PART NUMBER
SNx4AHCT573
BODY SIZE (NOM)
7.20 mm × 5.30 mm
TVSOP (20)
5.00 mm × 4.40 mm
SOIC (20)
12.80 mm × 7.50 mm
PDIP (20)
25.40 mm × 6.35 mm
TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
PACKAGE
SSOP (20)
Servers
PCs and Notebooks
Network Switches
Wearable Health and Fitness Devices
Telecom Infrastructures
Electronic Points of Sale
4 Simplified Schematic
OE
LE
C1
1Q
1D
1D
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54AHCT573, SN74AHCT573
SCLS243O – OCTOBER 1995 – REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
4
4
4
5
5
5
6
6
6
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
8
8
10 Application and Implementation.......................... 9
10.1 Application Information............................................ 9
10.2 Typical Application ................................................. 9
11 Power Supply Recommendations ..................... 10
12 Layout................................................................... 10
12.1 Layout Guidelines ................................................. 10
12.2 Layout Example .................................................... 10
13 Device and Documentation Support ................. 11
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
14 Mechanical, Packaging, and Orderable
Information ........................................................... 11
5 Revision History
Changes from Revision N (July 2003) to Revision O
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Added Military Disclaimer to Features list. ............................................................................................................................. 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Pin Functions table...................................................................................................................................................... 3
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 4
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added –40°C to 125°C temperature range for SN74AHCT573 in Electrical Characteristics table. ....................................... 5
•
Added –40°C to 125°C temperature range for SN74AHCT573 in Timing Requirements table. ............................................ 5
•
Added Typical Characteristics. ............................................................................................................................................... 6
•
Added Detailed Description section........................................................................................................................................ 8
•
Added Application and Implementation section...................................................................................................................... 9
•
Added Power Supply Recommendations and Layout sections............................................................................................ 10
2
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Product Folder Links: SN54AHCT573 SN74AHCT573
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SCLS243O – OCTOBER 1995 – REVISED SEPTEMBER 2014
6 Pin Configuration and Functions
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
2D
1D
OE
VCC
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
3D
4D
5D
6D
7D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
LE
8Q
7Q
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1Q
SN54AHCT573 . . . FK PACKAGE
(TOP VIEW)
SN54AHCT573 . . . J OR W PACKAGE
SN74AHCT573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
OE
I
Output Enable
2
1D
I
1D Input
3
2D
I
2D Input
4
3D
I
3D Input
5
4D
I
4D Input
6
5D
I
5D Input
7
6D
I
6D Input
8
7D
I
7D Input
9
8D
I
8D Input
10
GND
—
Ground
11
LE
I
Latch Enable
12
8Q
O
8Q Output
13
7Q
O
7Q Output
14
6Q
O
6Q Output
15
5Q
O
5Q Output
16
4Q
O
4Q Output
17
3Q
O
3Q Output
18
2Q
O
2Q Output
19
1Q
O
1Q Output
20
VCC
—
Power Pin
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SCLS243O – OCTOBER 1995 – REVISED SEPTEMBER 2014
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±75
mA
Continuous current through VCC or GND
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
°C
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54AHCT573
SN74AHCT573
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
IOH
High-level output current
–8
–8
IOL
Low-level output current
8
8
mA
∆t/∆v
Input transition rise or fall rate
20
20
ns/V
TA
Operating free-air temperature
125
°C
(1)
4
2
2
0.8
–55
V
125
V
0.8
V
0
5.5
V
0
VCC
V
–40
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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SCLS243O – OCTOBER 1995 – REVISED SEPTEMBER 2014
7.4 Thermal Information
SN74AHCT573
THERMAL METRIC (1)
DW
DB
DGV
N
NS
PW
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
79.4
97.9
117.2
53.3
79.2
103.3
RθJC(top)
Junction-to-case (top) thermal resistance
45.7
59.6
32.7
40.0
45.7
37.8
RθJB
Junction-to-board thermal resistance
46.9
53.1
58.7
34.2
46.8
54.3
ψJT
Junction-to-top characterization parameter
18.7
21.3
1.15
26.4
19.3
2.9
ψJB
Junction-to-board characterization parameter
46.5
52.7
58.0
34.1
46.4
53.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
n/a
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50 µA
VOH
IOH = −8 mA
IOL = 50 µA
VOL
IOL = 8 mA
TA = 25°C
VCC
4.5 V
MIN
TYP
4.4
4.5
SN54AHCT573
MAX
3.94
4.5 V
MIN
–40°C to 125°C
SN74AHCT573
SN74AHCT573
MAX
MIN
MAX
MIN
4.4
4.4
4.4
3.8
3.8
3.8
UNIT
MAX
V
0.1
0.1
0.1
0.1
0.36
0.44
0.44
0.44
V
II
VI = 5.5 V or GND
0 V to
5.5 V
±0.1
±1 (1)
±1
±2
µA
IOZ
VO = VCC or GND
5.5 V
±0.25
±2.5
±2.5
±2.5
µA
ICC
VI = VCC or GND, IO = 0
5.5 V
4
40
40
40
µA
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
1.35
1.5
1.5
1.5
mA
10
10
pF
ΔICC
(2)
Ci
VI = VCC or GND
5V
2.5
Co
VO = VCC or GND
5V
3
(1)
(2)
10
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
7.6 Timing Requirements
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
TA = 25°C
PARAMETER
MIN
MAX
SN54AHCT573
MIN
MAX
SN74AHCT573
MIN
MAX
–40°C to 125°C
SN74AHCT573
MIN
UNIT
MAX
tw
Pulse duration, LE high
5
5
5
5
ns
tsu
Setup time, data before LE↓
3.5
3.5
3.5
3.5
ns
th
Hold time, data after LE↓
1.5
1.5
1.5
1.5
ns
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7.7 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
D
Q
CL = 15 pF
LE
Q
CL = 15 pF
OE
Q
CL = 15 pF
OE
Q
CL = 15 pF
D
Q
CL = 50 pF
LE
Q
CL = 50 pF
OE
Q
CL = 50 pF
OE
Q
CL = 50 pF
tsk(o)
(1)
(2)
TA = 25°C
MIN
SN54AHCT573
TYP
MAX
MIN
MAX
MIN
MAX
MIN
4.2 (1)
6 (1)
1 (1)
6.5 (1)
1
6.5
1
7
5.1
(1)
7
(1)
1
(1)
9 (1)
1
9
1
9.5
4.7
(1)
6.5
(1)
1
(1)
(1)
7.5
UNIT
MAX
1
7.5
1
8
5.6 (1)
7.5 (1)
1 (1)
9 (1)
1
9
1
9.5
4.1 (1)
6.5 (1)
1 (1)
7 (1)
1
7
1
8
5.5 (1)
7.5 (1)
1 (1)
9 (1)
1
10
1
11
5.5 (1)
8 (1)
1 (1)
11 (1)
1
11
1
12
5.4 (1)
8 (1)
1 (1)
9.5 (1)
1
9.5
1
10.5
5.2
7
1
7.5
1
7.5
1
8.5
6.1
8
1
10
1
10
1
10.5
5.7
7.5
1
8.5
1
8.5
1
9.5
6.6
8.5
1
10
1
10
1
10.5
5.1
7.5
1
8
1
8
1
9
6.5
8.5
1
11
1
11
1
11.5
6.7
9
1
12
1
12
1
12.5
6.4
9
1
10.5
1
10.5
1
11.5
1.5 (2)
CL = 50 pF
TA = –40°C to 125°C
SN74AHCT573
SN74AHCT573
ns
ns
ns
ns
ns
ns
ns
ns
1.5
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
7.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
TYP
16
UNIT
pF
7.9 Typical Characteristics
6
5
TPD (ns)
4
3
2
1
TPD in ns
0
-100
-50
0
50
Temperature (qC)
100
150
D001
Figure 1. TPD vs Temperature at 5 V
6
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SCLS243O – OCTOBER 1995 – REVISED SEPTEMBER 2014
8 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SNx4AHCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pull-up components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
9.2 Functional Block Diagram
OE
LE
C1
1Q
1D
1D
To Seven Other Channels
9.3 Feature Description
•
•
TTL inputs
– Lowered switching threshold allows up translation 3.3 V to 5 V
Slow edges reduce output ringing
9.4 Device Functional Modes
Table 1. Function Table
(Each Latch)
INPUTS
8
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OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74AHCT573 is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V
VIL and 2-V VIH. This feature makes the device ideal for translating up from 3.3 V to 5 V. Figure 4 shows this type
of translation.
10.2 Typical Application
Regulated 5 V
Regulated 3.3 V
OE
VCC
LE
1D
1Q
µC or
5 V µC
System Logic
System Logic
8D
8Q
LEDs
GND
Figure 3. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended input conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend output conditions
– Load currents should not exceed 25 mA per output and 75 mA total for the part.
– Outputs should not be pulled above VCC.
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Typical Application (continued)
10.2.3 Application Curves
Figure 4. Up Translation
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF bypass capacitor is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is
recommended for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different
frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed
as close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified in Figure 5 are the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float
outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs
section of the part when asserted. This will not disable the input section of the IO’s so they cannot float when
disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 5. Layout Diagram
10
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54AHCT573
Click here
Click here
Click here
Click here
Click here
SN74AHCT573
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHCT573 SN74AHCT573
Submit Documentation Feedback
11
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9685501QRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9685501QR
A
SNJ54AHCT573J
5962-9685501QSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9685501QS
A
SNJ54AHCT573W
SN74AHCT573DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB573
Samples
SN74AHCT573DGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB573
Samples
SN74AHCT573DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT573
Samples
SN74AHCT573DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT573
Samples
SN74AHCT573N
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHCT573N
Samples
SN74AHCT573PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB573
Samples
SN74AHCT573PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
HB573
Samples
SN74AHCT573PWRE4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB573
Samples
SN74AHCT573PWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB573
Samples
SNJ54AHCT573J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9685501QR
A
SNJ54AHCT573J
SNJ54AHCT573W
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9685501QS
A
SNJ54AHCT573W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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