SN74ALS561ADWG4

SN54ALS561A, SN74ALS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995 • description These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading. All synchronous functions are executed on the positive-going edge of the clock. The clear function is initiated by applying a low level to either asynchronous clear (ACLR) or synchronous clear (SCLR). ACLR (direct clear) overrides all other functions of the device, while SCLR overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by applying a low level to asynchronous load (ALOAD) or by the combination of a low level at synchronous load (SLOAD) and a positive-going clock transition. The counting function is enabled only when enable P (ENP), enable T (ENT), ACLR, ALOAD, SCLR, and SLOAD are all high. ALOAD CLK A B C D ENP ACLR SCLR GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC RCO CCO OE QA QB QC QD ENT SLOAD SN54ALS561A . . . FK PACKAGE (TOP VIEW) B C D ENP ACLR RCO • SN54ALS561A . . . J PACKAGE SN74ALS561A . . . DW OR N PACKAGE (TOP VIEW) A CLK ALOAD VCC • Carry Output for n-Bit Cascading Buffer-Type Outputs Drive Bus Lines Directly Choice of Asynchronous or Synchronous Clearing and Loading Internal Look-Ahead Circuitry for Fast Cascading Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 CCO OE QA QB QC SCLR GND SLOAD ENT QD • • A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output (RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because CCO does not become active until the clock returns to the low level. The SN54ALS561A is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS561A is characterized for operation from 0°C to 70°C. Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS561A, SN74ALS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995 FUNCTION TABLE INPUTS OE ACLR ALOAD SCLR H L X X L X L L H H L H L L L OPERATION SLOAD ENT ENP CLK X X X X X Q outputs disabled X X X X X Asynchronous clear L X X X X X Asynchronous load H L X X X ↑ Synchronous clear H H L X X ↑ Synchronous load H H H H H H ↑ Count H H H H L X X Inhibit counting H H H H X L X Inhibit counting logic symbol† 17 OE ENT ENP SCLR SLOAD CLK 12 7 9 11 2 EN10 CTRDIV16 G1 G2 6CT=0 [SYNC CLR] M3 [COUNT] M4 [SYNC LOAD] M5 [COUNT] C6/1, 2, 3, 5+ Z7 8 ACLR 1 ALOAD A B C D 3 CT=0 C8 7, 1, 2, 9 1 (CT=15) G9 4,6D/8D 4 19 16 10 15 5 14 6 13 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CCO RCO QA QB QC QD SN54ALS561A, SN74ALS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995 logic diagram (positive logic) OE ENT ENP SCLR SLOAD CLK ACLR ALOAD A 17 12 7 18 9 11 19 RCO 2 8 1 3 R S C1 1D B CCO 16 QA 4 R S C1 1D C 15 QB 5 R S C1 1D D 14 QC 6 R S C1 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 QD 3 SN54ALS561A, SN74ALS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995 typical load, count, and inhibit sequences OE ACLR SCLR ALOAD ÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌ ÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ ÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ SLOAD ENP Don’t Care ENT Don’t Care CLK A Don’t Care Don’t Care B Don’t Care Don’t Care C Don’t Care Don’t Care D Don’t Care Don’t Care QA Hi-Z QB Hi-Z QC Hi-Z QD Hi-Z RCO CCO 12 Async Clear 4 13 Async Load 14 15 0 1 13 Sync Clear 14 Sync Load POST OFFICE BOX 655303 15 0 1 5 Hi-Z Continue Counting • DALLAS, TEXAS 75265 Inhibit Counting SN54ALS561A, SN74ALS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS561A . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS561A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS561A VCC VIH Supply voltage VIL Low-level input voltage High-level input voltage IOH High level output current High-level IOL Low level output current Low-level fclock Clock frequency tw Pulse duration MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 CCO and RCO Q outputs CCO and RCO 0 2 0.8 –1 – 2.6 – 0.4 – 0.4 12 24 4 8 20 0 20 15 CLK high 20 16.5 25 16.5 High 25 20 Low 25 20 SCLR SLOAD 25 20 Low 21 15 High (inactive) 35 30 Low 20 15 High (inactive) 35 30 12 10 0 0 ACLR or ALOAD inactive Hold time after CLK↑ for data, ENP, ENT, SCLR, or SLOAD Operating free-air temperature – 55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 0 UNIT V V 0.7 ACLR or ALOAD low Data at A, B, C, D th TA NOM Q outputs ENP ENT ENP, Setup time before CLK↑ ↑ MIN 2 CLK low tsu SN74ALS561A 30 V mA mA MHz ns ns ns 70 °C 5 SN54ALS561A, SN74ALS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA Q outputs 5V VCC = 4 4.5 IOH = – 1 mA IOH = – 2.6 mA Q outputs VCC = 4 4.5 5V IOL = 12 mA IOL = 24 mA 0.25 CCO and RCO VCC = 4 4.5 5V IOL = 4 mA IOL = 8 mA 0.25 VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V IOZH IOZL IIH ENP and ENT Other inputs ENP and ENT Other inputs IIL IO‡ ICC MIN All outputs VOL II SN54ALS561A TYP† MAX TEST CONDITIONS CCO and RCO Q VCC = 5 5.5 5V V, VI = 7 V VCC = 5 5.5 5V V, VI = 2 2.7 7V VCC = 5.5 V, VI = 0.4 V VCC = 5 5.5 5V V, VCC = 5.5 V SN74ALS561A TYP† MAX MIN – 1.5 VCC – 2 2.4 – 1.5 V VCC – 2 V 3.3 2.4 0.4 0.4 3.2 0.25 0.4 0.35 0.5 0.25 0.4 0.35 0.5 V 20 20 µA – 20 – 20 µA 0.2 0.2 0.1 0.1 40 40 20 20 – 0.2 VO = 2 2.25 25 V UNIT – 0.2 – 15 – 70 – 15 – 70 – 20 – 112 – 30 – 112 Outputs high 17 27 17 27 Outputs low 21 33 21 33 Outputs disabled 22 36 22 36 mA µA mA mA mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS561A, SN74ALS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† SN54ALS561A MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL MAX SN74ALS561A MIN 20 CLK Any Q CLK RCO CLK CCO ALOAD Any Q ALOAD RCO ALOAD CCO A B A, B, C C, or D Any Q ENT RCO ENT CCO ENP CCO ACLR Any Q tPZH tPZL OE Any Q tPHZ tPLZ OE Any Q UNIT MAX 30 MHz 4 15 4 12 5 21 5 18 9 35 9 29 8 29 8 24 8 35 8 26 5 20 5 16 10 38 10 35 7 27 7 23 15 50 15 40 12 35 12 30 25 65 25 55 12 42 12 33 8 35 8 30 7 27 7 22 5 20 5 16 4 18 4 14 12 35 12 32 4 15 4 12 5 22 5 18 4 14 4 12 7 28 7 22 5 24 5 19 8 28 8 23 2 12 2 10 2 20 4 15 ns ns ns ns ns ns ns ns ns ns ns ns ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ALS561A, SN74ALS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SN74ALS561AN ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type 0 to 70 SN74ALS561AN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of